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CoreSight Program Flow Trace Architecture Specification

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CoreSight Program Flow Trace Architecture Specification

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Feedback on the Program Flow Trace architecture

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Upgrading a nonwaypoint instruction on an exception

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Program Trace Macrocell Programmers Model

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EmbeddedICE watchpoint comparator input behavior

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Default behavior of EmbeddedICE watchpoint comparator inputs

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Pulse and latch behavior of EmbeddedICE watchpoint comparator inputs

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Examples of using EmbeddedICE watchpoint comparator inputs

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The Instrumentation resource event resources

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Instructions for controlling the Instrumentation resources

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Instrumentation resource behavior when tracing parallel execution

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Address Comparator Value Registers, ETMACVRn

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Address Comparator Access Type Registers, ETMACTRn

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Counter Reload Value Registers, ETMCNTRLDVRn

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Counter Enable Event Registers, ETMCNTENRn

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Counter Reload Event Registers, ETMCNTRLDEVRn

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Sequencer State Transition Event Registers, ETMSQabEVR

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Current Sequencer State Register, ETMSQR

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External Output Event Registers, ETMEXTOUTEVRn

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About the Context ID comparator registers

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Context ID Comparator Value Registers, ETMCIDCVRn

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Context ID Comparator Mask Register, ETMCIDCMR

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Configuration Code Extension Register, ETMCCER

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Extended External Input Selection Register, ETMEXTINSELR

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EmbeddedICE Behavior Control Register, ETMEIBCR

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CoreSight Trace ID Register, ETMTRACEIDR

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VMID Comparator Value Register, ETMVMIDCVR

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About the Operating System Save and Restore registers

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Device Power-Down Control Register, ETMPDCR

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Device Power-Down Status Register, ETMPDSR

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Integration Mode Control Register, ETMITCTRL

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About the Peripheral Identification Registers

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Peripheral ID5 to Peripheral ID7 Registers, ETMPIDR5 to ETMPIDR7

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About the Component Identification Registers

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Guidelines for the PTM trace registers to be saved and restored

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About the access permissions for PTM registers

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Meanings of terms and abbreviations used in this section

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Restrictions on accesses using a Direct JTAG connection

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Effect of DBGSWENABLE on register access

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Access permissions for PFTv1.0 SinglePower implementations

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PTM state definitions, PFTv1.0 SinglePower implementations

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Access permissions for PFTv1.0 with multiple power implementations

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PTM state definitions, PFTv1.0 with multiple power implementations

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Debugger accesses, PFTv1.0 with multiple power implementations

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Memory-mapped accesses, PFTv1.0 with multiple power implementations

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Coprocessor accesses, PFTv1.0 with multiple power implementations

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Access permissions for PFTv1.1 SinglePower implementations

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PTM state definitions, PFTv1.1 SinglePower implementations

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Access permissions for PFTv1.1 with multiple power implementations

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PTM state definitions, PFTv1.1 with multiple power implementations

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Debugger accesses, PFTv1.1 with multiple power implementations

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Memory-mapped accesses, PFTv1.1 with multiple power implementations

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Coprocessor accesses, PFTv1.1 with multiple power implementations

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Programming the PTM to trace all execution

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Behavior of the PTM when the processor is in a prohibited region

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Changing from Non-secure to Secure state

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Changing from Secure to Non-secure state

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Setting the Programming bit or the OS Lock

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About exception tracing in the PFT architecture

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Exception occurs after a nonwaypoint instruction

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Exception occurs immediately after a waypoint instruction

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Exception occurs immediately after another exception

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Exception occurs immediately after trace turn-on

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SVC (Supervisor Call) or SMC (Secure Monitor Call) exception

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Asynchronous Data Abort, FIQ or IRQ exception

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Debug state entry, when Halting debug-mode is enabled

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ThumbEE check that goes to a handler, including the CHKA instruction

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Jazelle exception that goes to an ARM or Thumb state handler

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Resource identification and event encoding

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Summary of implementation defined PTM features

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Details of PFT trace decompression operations

# metadata.contentDescription
This is the Architecture Specification for Program Flow Trace. It defines the architecture for a Program Trace Macrocell (PTM).