# topic.topics[].topics[].topics[].label
Instrumentation resources, ETMv3.3 and later

# topic.topics[].topics[].topics[].label
TraceEnable and filtering the instruction trace

# topic.topics[].topics[].topics[].label
Comparator access size field behavior, in ETMv3.1 and later

# topic.topics[].topics[].topics[].label
Comparator access size field behavior, in ETMv3.0 and earlier

# topic.topics[].topics[].topics[].label
Access types for address range comparators

# topic.topics[].topics[].topics[].label
Operation of data value comparators, in ETMv3.2 and earlier

# topic.topics[].topics[].topics[].label
Operation of data value comparators, in ETMv3.3 and later

# topic.topics[].topics[].topics[].label
Summary of alignment and endianness considerations for different ETM versions

# topic.topics[].topics[].topics[].label
The Instrumentation resource event resources

# topic.topics[].topics[].topics[].label
Instructions for controlling the Instrumentation resources

# topic.topics[].topics[].topics[].label
Instrumentation resource behavior when tracing parallel execution

# topic.topics[].topics[].label
Considerations for advanced processors, ETMv2 and later only

# topic.topics[].topics[].topics[].label
Consequences of parallel execution on counters

# topic.topics[].topics[].topics[].label
Consequences of parallel execution on the sequencer

# topic.topics[].topics[].label
Supported standard configurations in ETMv1

# topic.topics[].topics[].label
Behavior when non-invasive debug is disabled

# topic.topics[].topics[].topics[].label
Restrictions on the type of access to ETM registers

# topic.topics[].topics[].topics[].label
ETM Trace and ETM Management registers, from ETMv3.3

# topic.topics[].topics[].topics[].label
ETM Programming bit and associated state

# topic.topics[].topics[].topics[].label
ETM Status Register, ETMSR, ETMv1.1 and later

# topic.topics[].topics[].topics[].label
System Configuration Register, ETMSCR, ETMv1.2 and later

# topic.topics[].topics[].topics[].label
TraceEnable Start/Stop Control Register, ETMTSSCR, ETMv1.2 and later

# topic.topics[].topics[].topics[].label
TraceEnable Control 2 Register, ETMTECR2, ETMv1.2 and later

# topic.topics[].topics[].topics[].label
TraceEnable Control 1 Register, ETMTECR1

# topic.topics[].topics[].topics[].label
Controlling FIFO overflow using the FIFOFULL registers

# topic.topics[].topics[].topics[].label
Address Comparator Value Registers, ETMACVRn

# topic.topics[].topics[].topics[].label
Address Comparator Access Type Registers, ETMACTRn

# topic.topics[].topics[].topics[].label
About the data value comparator registers

# topic.topics[].topics[].topics[].label
Data Comparator Value Registers, ETMDCVRn

# topic.topics[].topics[].topics[].label
Data Comparator Mask Registers, ETMDCMRn

# topic.topics[].topics[].topics[].label
Counter Reload Value Registers, ETMCNTRLDVRn

# topic.topics[].topics[].topics[].label
Counter Reload Event Registers, ETMCNTRLDEVRn

# topic.topics[].topics[].topics[].label
Sequencer State Transition Event Registers, ETMSQabEVR

# topic.topics[].topics[].topics[].label
Current Sequencer State Register, ETMSQR

# topic.topics[].topics[].topics[].label
External Output Event Registers, ETMEXTOUTEVRn

# topic.topics[].topics[].topics[].label
About the Context ID comparator registers, ETMv2.0 and later

# topic.topics[].topics[].topics[].label
Context ID Comparator Value Registers, ETMCIDCVRn

# topic.topics[].topics[].topics[].label
Context ID Comparator Mask Register, ETMCIDCMR

# topic.topics[].topics[].topics[].label
Synchronization Frequency Register, ETMSYNCFR, ETMv2.0 and later

# topic.topics[].topics[].topics[].label
Configuration Code Extension Register, ETMCCER, ETMv3.1 and later

# topic.topics[].topics[].topics[].label
Extended External Input Selection Register, ETMEXTINSELR, ETMv3.1 and later

# topic.topics[].topics[].topics[].label
EmbeddedICE Behavior Control Register, ETMEIBCR, ETMv3.4 and later

# topic.topics[].topics[].topics[].label
Timestamp Event Register, ETMTSEVR, ETMv3.5

# topic.topics[].topics[].topics[].label
Auxiliary Control Register, ETMAUXCR, ETMv3.5

# topic.topics[].topics[].topics[].label
CoreSight Trace ID Register, ETMTRACEIDR, ETMv3.2 and later

# topic.topics[].topics[].topics[].label
VMID Comparator Value Register, ETMVMIDCVR, ETMv3.5

# topic.topics[].topics[].topics[].label
About the Operating System Save and Restore Registers, ETMv3.3 and later

# topic.topics[].topics[].topics[].label
OS Lock Access Register, ETMOSLAR, ETMv3.3 and later

# topic.topics[].topics[].topics[].label
OS Lock Status Register, ETMOSLSR, ETMv3.3 and later

# topic.topics[].topics[].topics[].label
OS Save and Restore Register, ETMOSSRR, ETMv3.3 and later

# topic.topics[].topics[].topics[].label
Device Power-Down Status Register, ETMPDSR, ETMv3.3 and later

# topic.topics[].topics[].topics[].label
Power Down Control Register, ETMPDCR, ETMv3.5

# topic.topics[].topics[].topics[].label
Integration Mode Control Register, ETMITCTRL, ETMv3.2 and later

# topic.topics[].topics[].topics[].label
About the claim tag registers, ETMv3.2 and later

# topic.topics[].topics[].topics[].label
About the lock registers, ETMv3.2 and later

# topic.topics[].topics[].topics[].label
Lock Access Register, ETMLAR, ETMv3.2 and later

# topic.topics[].topics[].topics[].label
Lock Status Register, ETMLSR, ETMv3.2 and later

# topic.topics[].topics[].topics[].label
Authentication Status Register, ETMAUTHSTATUS, ETMv3.2 and later

# topic.topics[].topics[].topics[].label
CoreSight Device Configuration Register, ETMDEVID, ETMv3.2 and later

# topic.topics[].topics[].topics[].label
CoreSight Device Type Register, ETMDEVTYPE, ETMv3.2 and later

# topic.topics[].topics[].topics[].label
About the CoreSight Peripheral Identification Registers, ETMv3.2 and later

# topic.topics[].topics[].topics[].label
Peripheral ID5 to Peripheral ID7 Registers, ETMPIDR5 to ETMPIDR7

# topic.topics[].topics[].topics[].label
About the CoreSight component identification registers, ETMv3.2 and later

# topic.topics[].topics[].topics[].label
Boolean combinations for defining events

# topic.topics[].topics[].topics[].label
Examples of event and resource programming

# topic.topics[].topics[].label
Example ViewData and TraceEnable configurations

# topic.topics[].topics[].topics[].label
Power down support in ETMv3.3 and ETMv3.4

# topic.topics[].topics[].topics[].label
Guidelines for the ETM trace registers to be saved and restored

# topic.topics[].topics[].label
About the access permissions for ETM registers

# topic.topics[].topics[].topics[].label
Meanings of terms and abbreviations used in this section

# topic.topics[].topics[].topics[].label
Restrictions on accesses using a Direct JTAG connection

# topic.topics[].topics[].topics[].label
Effect of DBGSWENABLE on register access

# topic.topics[].topics[].label
Access permissions for ETMv3.3 and ETMv3.4, SinglePower

# topic.topics[].topics[].topics[].label
ETM state definitions, ETMv3.3 and ETMv3.4, SinglePower

# topic.topics[].topics[].topics[].label
Debugger accesses, ETMv3.3 and ETMv3.4, SinglePower

# topic.topics[].topics[].topics[].label
Memory-mapped accesses, ETMv3.3 and ETMv3.4, SinglePower

# topic.topics[].topics[].topics[].label
Coprocessor accesses, ETMv3.3 and ETMv3.4, SinglePower

# topic.topics[].topics[].label
Access permissions for ETMv3.3 and ETMv3.4, multiple power domains

# topic.topics[].topics[].topics[].label
ETM state definitions, ETMv3.3 and ETMv3.4, multiple power domains

# topic.topics[].topics[].topics[].label
Debugger accesses, ETMv3.3 and ETMv3.4, multiple power domains

# topic.topics[].topics[].topics[].label
Memory-mapped accesses, ETMv3.3 and ETMv3.4, multiple power domains

# topic.topics[].topics[].topics[].label
Coprocessor accesses, ETMv3.3 and ETMv3.4, multiple power domains

# topic.topics[].topics[].label
Access permissions for ETMv3.5, SinglePower

# topic.topics[].topics[].topics[].label
ETM state definitions, ETMv3.5, SinglePower

# topic.topics[].topics[].label
Access permissions for ETMv3.5, multiple power domains

# topic.topics[].topics[].topics[].label
ETM state definitions, ETMv3.5, multiple power domains

# topic.topics[].topics[].topics[].label
Debugger accesses, ETMv3.5, multiple power domains

# topic.topics[].topics[].topics[].label
Memory-mapped accesses, ETMv3.5, multiple power domains

# topic.topics[].topics[].topics[].label
Coprocessor accesses, ETMv3.5, multiple power domains

# topic.topics[].topics[].topics[].label
Multiplexed trace port (ETMv1.x and ETMv2.x only)

# topic.topics[].topics[].topics[].label
Demultiplexed trace port (ETMv1.x and ETMv2.x only)

# topic.topics[].topics[].label
Decoding required by trace capture devices

# topic.topics[].topics[].label
Rules for generating and analyzing the trace in ETMv1

# topic.topics[].topics[].topics[].label
Additional considerations for 16-bit ports

# topic.topics[].topics[].label
Pipeline status and trace packet association in ETMv1

# topic.topics[].topics[].topics[].label
Direct branches to the exception vector table

# topic.topics[].topics[].topics[].label
Compressed branch address packet structure

# topic.topics[].topics[].topics[].label
PIPESTAT signals indicating data accesses in the pipeline

# topic.topics[].topics[].topics[].label
Address compression performed by the ETM

# topic.topics[].topics[].topics[].label
Instruction Not Executed PIPESTAT signals

# topic.topics[].topics[].label
Rules for generating and analyzing the trace in ETMv2

# topic.topics[].topics[].label
Tracing through regions with no code image

# topic.topics[].topics[].topics[].label
Address compression performed by the ETM

# topic.topics[].topics[].topics[].label
Condition codes on canceled and undefined instructions

# topic.topics[].topics[].topics[].label
Cycle information, for cycle-accurate tracing

# topic.topics[].topics[].label
Additional trace features for ARMv7-M processors, from ETMv3.4

# topic.topics[].topics[].topics[].label
Support for a large number of exceptions

# topic.topics[].topics[].topics[].label
Instructions that can be paused for continuation

# topic.topics[].topics[].topics[].label
Automatic stack push on exception entry and pop on exception exit

# topic.topics[].topics[].label
Behavior of EmbeddedICE inputs, from ETMv3.4

# topic.topics[].topics[].topics[].label
EmbeddedICE watchpoint comparator input behavior

# topic.topics[].topics[].topics[].label
Default behavior of EmbeddedICE watchpoint inputs

# topic.topics[].topics[].topics[].label
Implementation of pulse and latch behavior of EmbeddedICE inputs

# topic.topics[].topics[].label
Tracing through regions with no code image

# topic.topics[].topics[].topics[].label
Tracing long gaps in cycle-accurate trace

# topic.topics[].topics[].topics[].label
Support for cycle-accurate tracing, ETMv3.3 and later

# topic.topics[].topics[].topics[].label
ETMv2 PIPESTAT encodings and ETMv3 P-headers compared

# topic.topics[].topics[].topics[].label
ETMv2 TFO packets and ETMv3 I-sync packets compared

# topic.topics[].topics[].topics[].label
Assignment of trace information pins between ETM architecture versions

# topic.topics[].topics[].topics[].label
Multiplexed trace port, single target connector pinout (ETMv1.x and ETMv2.x)

# topic.topics[].topics[].topics[].label
Demultiplexed trace port target connector pinout

# topic.topics[].topics[].topics[].label
Resource identification and event encoding

# topic.topics[].topics[].label
Summary of implementation defined ETM features

# metadata.contentDescription
This specification describes the ARM Embedded Trace Macrocell (ETM) architecture.