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About the Arm Compiler toolchain assemblers

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Directives that can be omitted in pass 2 of the assembler

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Changing between AArch64 and AArch32 states

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Changing between A32 and T32 instruction set states

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Processor modes, and privileged and unprivileged software execution

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Processor modes in Armv6-M, Armv7-M, and Armv8-M

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General-purpose registers in AArch32 state

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Predeclared core register names in AArch32 state

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Predeclared extension register names in AArch32 state

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Current Program Status Register in AArch32 state

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Saved Program Status Registers in AArch32 state

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Access to the inline barrel shifter in AArch32 state

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Predeclared core register names in AArch64 state

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Predeclared extension register names in AArch64 state

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Saved Program Status Registers in AArch64 state

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Syntax of source lines in assembly language

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An example armasm syntax assembly language module

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Syntax differences between UAL and A64 assembly language

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Load immediate values using LDR Rd, =const

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Load addresses to a register using LDR Rd, =label

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Load and store multiple register instructions

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Load and store multiple register instructions in A32 and T32

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Updates to the condition flags in A32/T32 code

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Updates to the condition flags in A64 code

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Floating-point instructions that update the condition flags

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Condition code suffixes and related flags

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Comparison of condition code meanings in integer and floating-point code

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Benefits of using conditional execution in A32 and T32 code

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Example showing the benefits of conditional instructions in A32 and T32 code

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Specify command-line options with an environment variable

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Using stdin to input source code to the assembler

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Identifying versions of armasm in source code

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Automatic IT block generation in T32 code

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A32 and T32 instruction portability diagnostics

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Extension register bank mapping for Advanced SIMD in AArch32 state

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Extension register bank mapping for Advanced SIMD in AArch64 state

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Views of the Advanced SIMD register bank in AArch32 state

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Views of the Advanced SIMD register bank in AArch64 state

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Differences between A32/T32 and A64 Advanced SIMD instruction syntax

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Conditional execution of A32/T32 Advanced SIMD instructions

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Floating-point exceptions for Advanced SIMD in A32/T32 instructions

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Advanced SIMD data types in A32/T32 instructions

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Normal, long, wide, and narrow Advanced SIMD instructions

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Extended notation extension for Advanced SIMD in A32/T32 code

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Advanced SIMD system registers in AArch32 state

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When to use flush-to-zero mode in Advanced SIMD

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The effects of using flush-to-zero mode in Advanced SIMD

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Advanced SIMD operations not affected by flush-to-zero mode

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Extension register bank mapping for floating-point in AArch32 state

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Extension register bank mapping in AArch64 state

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Views of the floating-point extension register bank in AArch32 state

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Views of the floating-point extension register bank in AArch64 state

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Differences between A32/T32 and A64 floating-point instruction syntax

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Conditional execution of A32/T32 floating-point instructions

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Floating-point exceptions for floating-point in A32/T32 instructions

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Floating-point data types in A32/T32 instructions

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Extended notation extension for floating-point in A32/T32 code

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Floating-point system registers in AArch32 state

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When to use flush-to-zero mode in floating-point

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The effects of using flush-to-zero mode in floating-point

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Floating-point operations not affected by flush-to-zero mode

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Symbols, Literals, Expressions, and Operators

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Addition, subtraction, and logical operators

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Difference between operator precedence in assembly language and C

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Syntax of Operand2 as a register with optional shift

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MRS (PSR to general-purpose register) (A32)

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MRS (system coprocessor register to general-purpose register) (A32)

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MSR (general-purpose register to system coprocessor register) (A32)

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MSR (general-purpose register to PSR) (A32)

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Summary of shared Advanced SIMD and floating-point instructions

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Interleaving provided by load and store element and structure instructions

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Alignment restrictions in load and store element and structure instructions

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VCVT (between fixed-point or integer, and floating-point) (A32)

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VCVT (between half-precision and single-precision floating-point) (A32)

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VCVT (from floating-point to integer with directed rounding modes) (A32)

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VCVTB, VCVTT (between half-precision and double-precision) (A32)

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VLDn (single n-element structure to one lane) (A32)

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VLDn (single n-element structure to all lanes) (A32)

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VLDn (multiple n-element structures) (A32)

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VLDR (post-increment and pre-decrement) (A32)

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VMOV (between two general-purpose registers and a 64-bit extension register) (A32)

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VMOV (between a general-purpose register and an Advanced SIMD scalar) (A32)

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VQDMLAL and VQDMLSL (by vector or by scalar) (A32)

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VQRSHRN and VQRSHRUN (by immediate) (A32)

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VSTn (multiple n-element structures) (A32)

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VSTn (single n-element structure to one lane) (A32)

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VSTR (post-increment and pre-decrement) (A32)

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VCVT (between single-precision and double-precision) (A32)

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VCVT (between floating-point and integer) (A32)

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VCVT (from floating-point to integer with directed rounding modes) (A32 FP)

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VCVT (between floating-point and fixed-point) (A32)

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VCVTB, VCVTT (half-precision extension) (A32)

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VCVTB, VCVTT (between half-precision and double-precision) (A32 FP)

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VFMA, VFMS, VFNMA, VFNMS (floating-point) (A32)

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VMOV (between one general-purpose register and single precision floating-point register) (A32)

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VMOV (between two general-purpose registers and one or two extension registers) (A32)

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VMOV (between a general-purpose register and half a double precision floating-point register) (A32)

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Register restrictions for A64 instructions

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AUTIA, AUTIZA, AUTIA1716, AUTIASP, AUTIAZ (A64)

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AUTIB, AUTIZB, AUTIB1716, AUTIBSP, AUTIBZ (A64)

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PACIA, PACIZA, PACIA1716, PACIASP, PACIAZ (A64)

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PACIB, PACIZB, PACIB1716, PACIBSP, PACIBZ (A64)

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A64 data transfer instructions in alphabetical order

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CASA, CASAL, CAS, CASL, CASAL, CAS, CASL (A64)

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CASPA, CASPAL, CASP, CASPL, CASPAL, CASP, CASPL (A64)

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LDADDA, LDADDAL, LDADD, LDADDL, LDADDAL, LDADD, LDADDL (A64)

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LDADDAB, LDADDALB, LDADDB, LDADDLB (A64)

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LDADDAH, LDADDALH, LDADDH, LDADDLH (A64)

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LDCLRA, LDCLRAL, LDCLR, LDCLRL, LDCLRAL, LDCLR, LDCLRL (A64)

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LDCLRAB, LDCLRALB, LDCLRB, LDCLRLB (A64)

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LDCLRAH, LDCLRALH, LDCLRH, LDCLRLH (A64)

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LDEORA, LDEORAL, LDEOR, LDEORL, LDEORAL, LDEOR, LDEORL (A64)

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LDEORAB, LDEORALB, LDEORB, LDEORLB (A64)

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LDEORAH, LDEORALH, LDEORH, LDEORLH (A64)

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LDSETA, LDSETAL, LDSET, LDSETL, LDSETAL, LDSET, LDSETL (A64)

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LDSETAB, LDSETALB, LDSETB, LDSETLB (A64)

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LDSETAH, LDSETALH, LDSETH, LDSETLH (A64)

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LDSMAXA, LDSMAXAL, LDSMAX, LDSMAXL, LDSMAXAL, LDSMAX, LDSMAXL (A64)

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LDSMAXAB, LDSMAXALB, LDSMAXB, LDSMAXLB (A64)

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LDSMAXAH, LDSMAXALH, LDSMAXH, LDSMAXLH (A64)

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LDSMINA, LDSMINAL, LDSMIN, LDSMINL, LDSMINAL, LDSMIN, LDSMINL (A64)

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LDSMINAB, LDSMINALB, LDSMINB, LDSMINLB (A64)

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LDSMINAH, LDSMINALH, LDSMINH, LDSMINLH (A64)

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LDUMAXA, LDUMAXAL, LDUMAX, LDUMAXL, LDUMAXAL, LDUMAX, LDUMAXL (A64)

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LDUMAXAB, LDUMAXALB, LDUMAXB, LDUMAXLB (A64)

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LDUMAXAH, LDUMAXALH, LDUMAXH, LDUMAXLH (A64)

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LDUMINA, LDUMINAL, LDUMIN, LDUMINL, LDUMINAL, LDUMIN, LDUMINL (A64)

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LDUMINAB, LDUMINALB, LDUMINB, LDUMINLB (A64)

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LDUMINAH, LDUMINALH, LDUMINH, LDUMINLH (A64)

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SWPA, SWPAL, SWP, SWPL, SWPAL, SWP, SWPL (A64)

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A64 floating-point instructions in alphabetical order

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A64 SIMD scalar instructions in alphabetical order

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SQRDMLAH (scalar, by element) (A64 SIMD)

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SQRDMLSH (scalar, by element) (A64 SIMD)

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SQRDMULH (scalar, by element) (A64 SIMD)

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A64 SIMD Vector instructions in alphabetical order

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SMLAL, SMLAL2 (vector, by element) (A64)

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SMLSL, SMLSL2 (vector, by element) (A64)

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SMULL, SMULL2 (vector, by element) (A64)

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SQDMLAL, SQDMLAL2 (vector, by element) (A64)

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SQDMLSL, SQDMLSL2 (vector, by element) (A64)

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SQDMULL, SQDMULL2 (vector, by element) (A64)

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UMLAL, UMLAL2 (vector, by element) (A64)

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UMLSL, UMLSL2 (vector, by element) (A64)

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UMULL, UMULL2 (vector, by element) (A64)

# metadata.contentDescription
Arm Compiler armasm User Guide. This document provides topic based documentation for using the Arm assembler ( armasm ). It contains information on command line options, assembler directives, and supports the Armv6-M, Armv7, and Armv8 architectures.