# title
Arm Cortex-M7 Devices Generic User Guide r1p2

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Arm Cortex-M7 Devices Generic User Guide

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About the Cortex-M7 processor and core peripherals

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Cortex-M7 processor features and benefits summary

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Processor mode and privilege levels for software execution

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The Cortex Microcontroller Software Interface Standard

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Memory system ordering of memory accesses

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Programming hints for the synchronization primitives

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Fault status registers and fault address registers

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The optional Wakeup Interrupt Controller

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Binary compatibility with other Cortex processors

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SMLAWB, SMLAWT, SMLABB, SMLABT, SMLATB, and SMLATT

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SMLALD, SMLALDX, SMLALBB, SMLALBT, SMLALTB, and SMLALTT

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VCVT and VCVTR between floating-point and integer

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VCVT between floating-point and fixed-point

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VMOV Arm Core register to single-precision

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VMOV two Arm Core registers to two single-precision registers

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VMOV two Arm core registers and a double-precision register

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VRINTA, VRINTN, VRINTP, VRINTM, and VRINTZ

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Accessing the Cortex-M7 NVIC registers using CMSIS

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Application Interrupt and Reset Control Register

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System Handler Control and State Register

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System control block design hints and tips

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Floating-point Default Status Control Register

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Instruction and data cache operations by address

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Accessing the Cortex-M7 NVIC cache maintenance operations using CMSIS

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Instruction and Data Tightly-Coupled Memory Control Registers

# metadata.contentDescription
This book is a generic user guide for devices that implement the ARM Cortex-M7 processor. 