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Cortex-M0 Devices Generic User Guide Version 1.0

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About the Cortex-M0 processor and core peripherals

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The Cortex Microcontroller Software Interface Standard

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Memory system ordering of memory accesses

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The optional Wakeup Interrupt Controller

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Accessing the Cortex-M0 NVIC registers using CMSIS

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The CMSIS mapping of the Cortex-M0 SCB registers

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Application Interrupt and Reset Control Register

# metadata.contentDescription
This book is a generic user guide for devices that implement the ARM Cortex-M0 processor. Implementers of Cortex-M0 designs make a number of implementation choices, that can affect the functionality of the device.