# title
Cortex-M1 FPGA Development Kit Cortex-M1 User Guide

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Cortex-M1 FPGA Development Kit Cortex-M1 User Guide

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About processor instantiation and configuration

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Application Interrupt and Reset Control Register

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System Handler Control and State Register

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Using memory barrier instructions for memory transactions

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Example of how to configure and enable an external interrupt

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Example of how to configure and schedule a PendSV exception

# metadata.contentDescription
This is the Cortex-M1 User Guide (UG) for the processor in the Cortex-M1 FPGA Development Kit Altera Edition.