# title
Arm A-profile A32/T32 Instruction Set Architecture

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Arm A-profile A32/T32 Instruction Set Architecture

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ADC, ADCS (immediate): Add with Carry (immediate).

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ADC, ADCS (register): Add with Carry (register).

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ADC, ADCS (register-shifted register): Add with Carry (register-shifted register).

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ADD (immediate, to PC): Add to PC: an alias of ADR.

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ADD, ADDS (register-shifted register): Add (register-shifted register).

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ADD, ADDS (SP plus immediate): Add to SP (immediate).

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ADD, ADDS (SP plus register): Add to SP (register).

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AND, ANDS (immediate): Bitwise AND (immediate).

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AND, ANDS (register): Bitwise AND (register).

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AND, ANDS (register-shifted register): Bitwise AND (register-shifted register).

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ASR (immediate): Arithmetic Shift Right (immediate): an alias of MOV, MOVS (register).

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ASR (register): Arithmetic Shift Right (register): an alias of MOV, MOVS (register-shifted register).

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ASRS (immediate): Arithmetic Shift Right, setting flags (immediate): an alias of MOV, MOVS (register).

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ASRS (register): Arithmetic Shift Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).

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BIC, BICS (immediate): Bitwise Bit Clear (immediate).

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BIC, BICS (register): Bitwise Bit Clear (register).

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BIC, BICS (register-shifted register): Bitwise Bit Clear (register-shifted register).

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BL, BLX (immediate): Branch with Link and optional Exchange (immediate).

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BLX (register): Branch with Link and Exchange (register).

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BXJ: Branch and Exchange, previously Branch and Exchange Jazelle.

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CBNZ, CBZ: Compare and Branch on Nonzero or Zero.

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CMN (immediate): Compare Negative (immediate).

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CMN (register): Compare Negative (register).

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CSDB: Consumption of Speculative Data Barrier.

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EOR, EORS (immediate): Bitwise Exclusive-OR (immediate).

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EOR, EORS (register): Bitwise Exclusive-OR (register).

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LDC (immediate): Load data to System register (immediate).

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LDC (literal): Load data to System register (literal).

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LDM (exception return): Load Multiple (exception return).

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LDM (User registers): Load Multiple (User registers).

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LDM, LDMIA, LDMFD: Load Multiple (Increment After, Full Descending).

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LDMDA, LDMFA: Load Multiple Decrement After (Full Ascending).

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LDMDB, LDMEA: Load Multiple Decrement Before (Empty Ascending).

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LDMIB, LDMED: Load Multiple Increment Before (Empty Descending).

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LDR (immediate): Load Register (immediate).

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LDR (register): Load Register (register).

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LDRB (immediate): Load Register Byte (immediate).

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LDRB (literal): Load Register Byte (literal).

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LDRB (register): Load Register Byte (register).

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LDRD (immediate): Load Register Dual (immediate).

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LDRD (literal): Load Register Dual (literal).

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LDRD (register): Load Register Dual (register).

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LDREXD: Load Register Exclusive Doubleword.

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LDREXH: Load Register Exclusive Halfword.

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LDRH (immediate): Load Register Halfword (immediate).

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LDRH (literal): Load Register Halfword (literal).

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LDRH (register): Load Register Halfword (register).

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LDRHT: Load Register Halfword Unprivileged.

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LDRSB (immediate): Load Register Signed Byte (immediate).

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LDRSB (literal): Load Register Signed Byte (literal).

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LDRSB (register): Load Register Signed Byte (register).

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LDRSBT: Load Register Signed Byte Unprivileged.

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LDRSH (immediate): Load Register Signed Halfword (immediate).

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LDRSH (literal): Load Register Signed Halfword (literal).

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LDRSH (register): Load Register Signed Halfword (register).

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LDRSHT: Load Register Signed Halfword Unprivileged.

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LSL (immediate): Logical Shift Left (immediate): an alias of MOV, MOVS (register).

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LSL (register): Logical Shift Left (register): an alias of MOV, MOVS (register-shifted register).

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LSLS (immediate): Logical Shift Left, setting flags (immediate): an alias of MOV, MOVS (register).

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LSLS (register): Logical Shift Left, setting flags (register): an alias of MOV, MOVS (register-shifted register).

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LSR (immediate): Logical Shift Right (immediate): an alias of MOV, MOVS (register).

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LSR (register): Logical Shift Right (register): an alias of MOV, MOVS (register-shifted register).

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LSRS (immediate): Logical Shift Right, setting flags (immediate): an alias of MOV, MOVS (register).

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LSRS (register): Logical Shift Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).

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MCR: Move to System register from general-purpose register or execute a System instruction.

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MCRR: Move to System register from two general-purpose registers.

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MOV, MOVS (immediate): Move (immediate).

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MOV, MOVS (register-shifted register): Move (register-shifted register).

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MRC: Move to general-purpose register from System register.

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MRRC: Move to two general-purpose registers from System register.

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MRS: Move Special register to general-purpose register.

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MRS (Banked register): Move Banked or Special register to general-purpose register.

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MSR (Banked register): Move general-purpose register to Banked or Special register.

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MSR (immediate): Move immediate value to Special register.

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MSR (register): Move general-purpose register to Special register.

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MVN, MVNS (immediate): Bitwise NOT (immediate).

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MVN, MVNS (register): Bitwise NOT (register).

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MVN, MVNS (register-shifted register): Bitwise NOT (register-shifted register).

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ORN, ORNS (immediate): Bitwise OR NOT (immediate).

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ORN, ORNS (register): Bitwise OR NOT (register).

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ORR, ORRS (immediate): Bitwise OR (immediate).

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ORR, ORRS (register): Bitwise OR (register).

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ORR, ORRS (register-shifted register): Bitwise OR (register-shifted register).

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PLD, PLDW (immediate): Preload Data (immediate).

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PLD, PLDW (register): Preload Data (register).

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PLI (immediate, literal): Preload Instruction (immediate, literal).

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PLI (register): Preload Instruction (register).

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POP (multiple registers): Pop Multiple Registers from Stack: an alias of LDM, LDMIA, LDMFD.

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POP (single register): Pop Single Register from Stack: an alias of LDR (immediate).

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PSSBB: Physical Speculative Store Bypass Barrier.

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PUSH (multiple registers): Push multiple registers to Stack: an alias of STMDB, STMFD.

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PUSH (single register): Push Single Register to Stack: an alias of STR (immediate).

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QASX: Saturating Add and Subtract with Exchange.

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QSAX: Saturating Subtract and Add with Exchange.

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RFE, RFEDA, RFEDB, RFEIA, RFEIB: Return From Exception.

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ROR (immediate): Rotate Right (immediate): an alias of MOV, MOVS (register).

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ROR (register): Rotate Right (register): an alias of MOV, MOVS (register-shifted register).

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RORS (immediate): Rotate Right, setting flags (immediate): an alias of MOV, MOVS (register).

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RORS (register): Rotate Right, setting flags (register): an alias of MOV, MOVS (register-shifted register).

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RRX: Rotate Right with Extend: an alias of MOV, MOVS (register).

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RRXS: Rotate Right with Extend, setting flags: an alias of MOV, MOVS (register).

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RSB, RSBS (immediate): Reverse Subtract (immediate).

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RSB, RSBS (register): Reverse Subtract (register).

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RSB, RSBS (register-shifted register): Reverse Subtract (register-shifted register).

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RSC, RSCS (immediate): Reverse Subtract with Carry (immediate).

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RSC, RSCS (register): Reverse Subtract with Carry (register).

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RSC, RSCS (register-shifted register): Reverse Subtract (register-shifted register).

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SASX: Signed Add and Subtract with Exchange.

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SBC, SBCS (immediate): Subtract with Carry (immediate).

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SBC, SBCS (register): Subtract with Carry (register).

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SBC, SBCS (register-shifted register): Subtract with Carry (register-shifted register).

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SHASX: Signed Halving Add and Subtract with Exchange.

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SHSAX: Signed Halving Subtract and Add with Exchange.

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SMLABB, SMLABT, SMLATB, SMLATT: Signed Multiply Accumulate (halfwords).

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SMLAD, SMLADX: Signed Multiply Accumulate Dual.

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SMLAL, SMLALS: Signed Multiply Accumulate Long.

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SMLALBB, SMLALBT, SMLALTB, SMLALTT: Signed Multiply Accumulate Long (halfwords).

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SMLALD, SMLALDX: Signed Multiply Accumulate Long Dual.

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SMLAWB, SMLAWT: Signed Multiply Accumulate (word by halfword).

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SMLSD, SMLSDX: Signed Multiply Subtract Dual.

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SMLSLD, SMLSLDX: Signed Multiply Subtract Long Dual.

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SMMLA, SMMLAR: Signed Most Significant Word Multiply Accumulate.

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SMMLS, SMMLSR: Signed Most Significant Word Multiply Subtract.

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SMMUL, SMMULR: Signed Most Significant Word Multiply.

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SMUAD, SMUADX: Signed Dual Multiply Add.

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SMULBB, SMULBT, SMULTB, SMULTT: Signed Multiply (halfwords).

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SMULWB, SMULWT: Signed Multiply (word by halfword).

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SMUSD, SMUSDX: Signed Multiply Subtract Dual.

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SRS, SRSDA, SRSDB, SRSIA, SRSIB: Store Return State.

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SSAX: Signed Subtract and Add with Exchange.

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STM (User registers): Store Multiple (User registers).

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STM, STMIA, STMEA: Store Multiple (Increment After, Empty Ascending).

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STMDA, STMED: Store Multiple Decrement After (Empty Descending).

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STMDB, STMFD: Store Multiple Decrement Before (Full Descending).

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STMIB, STMFA: Store Multiple Increment Before (Full Ascending).

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STR (immediate): Store Register (immediate).

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STR (register): Store Register (register).

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STRB (immediate): Store Register Byte (immediate).

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STRB (register): Store Register Byte (register).

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STRBT: Store Register Byte Unprivileged.

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STRD (immediate): Store Register Dual (immediate).

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STRD (register): Store Register Dual (register).

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STREXD: Store Register Exclusive Doubleword.

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STREXH: Store Register Exclusive Halfword.

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STRH (immediate): Store Register Halfword (immediate).

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STRH (register): Store Register Halfword (register).

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STRHT: Store Register Halfword Unprivileged.

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SUB (immediate, from PC): Subtract from PC: an alias of ADR.

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SUB, SUBS (immediate): Subtract (immediate).

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SUB, SUBS (register): Subtract (register).

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SUB, SUBS (SP minus immediate): Subtract from SP (immediate).

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SUB, SUBS (SP minus register): Subtract from SP (register).

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TBB, TBH: Table Branch Byte or Halfword.

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TEQ (immediate): Test Equivalence (immediate).

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TEQ (register): Test Equivalence (register).

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UASX: Unsigned Add and Subtract with Exchange.

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UHASX: Unsigned Halving Add and Subtract with Exchange.

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UHSAX: Unsigned Halving Subtract and Add with Exchange.

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UMAAL: Unsigned Multiply Accumulate Accumulate Long.

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UMLAL, UMLALS: Unsigned Multiply Accumulate Long.

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UQASX: Unsigned Saturating Add and Subtract with Exchange.

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UQSAX: Unsigned Saturating Subtract and Add with Exchange.

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UQSUB16: Unsigned Saturating Subtract 16.

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USAD8: Unsigned Sum of Absolute Differences.

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USADA8: Unsigned Sum of Absolute Differences and Accumulate.

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USAX: Unsigned Subtract and Add with Exchange.

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UXTAB16: Unsigned Extend and Add Byte 16.

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UXTAH: Unsigned Extend and Add Halfword.

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VABA: Vector Absolute Difference and Accumulate.

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VABAL: Vector Absolute Difference and Accumulate Long.

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VABD (integer): Vector Absolute Difference (integer).

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VABDL (integer): Vector Absolute Difference Long (integer).

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VACGE: Vector Absolute Compare Greater Than or Equal.

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VACGT: Vector Absolute Compare Greater Than.

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VACLE: Vector Absolute Compare Less Than or Equal: an alias of VACGE.

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VACLT: Vector Absolute Compare Less Than: an alias of VACGT.

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VADDHN: Vector Add and Narrow, returning High Half.

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VAND (immediate): Vector Bitwise AND (immediate): an alias of VBIC (immediate).

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VAND (register): Vector Bitwise AND (register).

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VBIC (immediate): Vector Bitwise Bit Clear (immediate).

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VBIC (register): Vector Bitwise Bit Clear (register).

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VCEQ (immediate #0): Vector Compare Equal to Zero.

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VCGE (immediate #0): Vector Compare Greater Than or Equal to Zero.

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VCGE (register): Vector Compare Greater Than or Equal.

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VCGT (immediate #0): Vector Compare Greater Than Zero.

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VCGT (register): Vector Compare Greater Than.

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VCLE (immediate #0): Vector Compare Less Than or Equal to Zero.

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VCLE (register): Vector Compare Less Than or Equal: an alias of VCGE (register).

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VCLT (immediate #0): Vector Compare Less Than Zero.

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VCLT (register): Vector Compare Less Than: an alias of VCGT (register).

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VCMLA: Vector Complex Multiply Accumulate.

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VCMLA (by element): Vector Complex Multiply Accumulate (by element).

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VCMPE: Vector Compare, raising Invalid Operation on NaN.

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VCVT (between double-precision and single-precision): Convert between double-precision and single-precision.

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VCVT (between floating-point and fixed-point, Advanced SIMD): Vector Convert between floating-point and fixed-point.

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VCVT (between floating-point and fixed-point, floating-point): Convert between floating-point and fixed-point.

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VCVT (between floating-point and integer, Advanced SIMD): Vector Convert between floating-point and integer.

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VCVT (between half-precision and single-precision, Advanced SIMD): Vector Convert between half-precision and single-precision.

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VCVT (floating-point to integer, floating-point): Convert floating-point to integer with Round towards Zero.

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VCVT (from single-precision to BFloat16, Advanced SIMD): Vector Convert from single-precision to BFloat16.

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VCVT (integer to floating-point, floating-point): Convert integer to floating-point.

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VCVTA (Advanced SIMD): Vector Convert floating-point to integer with Round to Nearest with Ties to Away.

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VCVTA (floating-point): Convert floating-point to integer with Round to Nearest with Ties to Away.

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VCVTB: Convert to or from a half-precision value in the bottom half of a single-precision register.

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VCVTB (BFloat16): Converts from a single-precision value to a BFloat16 value in the bottom half of a single-precision register.

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VCVTM (Advanced SIMD): Vector Convert floating-point to integer with Round towards -Infinity.

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VCVTM (floating-point): Convert floating-point to integer with Round towards -Infinity.

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VCVTN (Advanced SIMD): Vector Convert floating-point to integer with Round to Nearest.

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VCVTN (floating-point): Convert floating-point to integer with Round to Nearest.

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VCVTP (Advanced SIMD): Vector Convert floating-point to integer with Round towards +Infinity.

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VCVTP (floating-point): Convert floating-point to integer with Round towards +Infinity.

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VCVTR: Convert floating-point to integer.

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VCVTT: Convert to or from a half-precision value in the top half of a single-precision register.

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VCVTT (BFloat16): Converts from a single-precision value to a BFloat16 value in the top half of a single-precision register.

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VDOT (by element): BFloat16 floating-point indexed dot product (vector, by element).

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VDOT (vector): BFloat16 floating-point (BF16) dot product (vector).

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VDUP (general-purpose register): Duplicate general-purpose register to vector.

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VDUP (scalar): Duplicate vector element to vector.

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VEXT (multibyte elements): Vector Extract: an alias of VEXT (byte elements).

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VFMAB, VFMAT (BFloat16, by scalar): BFloat16 floating-point widening multiply-add long (by scalar).

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VFMAB, VFMAT (BFloat16, vector): BFloat16 floating-point widening multiply-add long (vector).

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VFMAL (by scalar): Vector Floating-point Multiply-Add Long to accumulator (by scalar).

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VFMAL (vector): Vector Floating-point Multiply-Add Long to accumulator (vector).

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VFMSL (by scalar): Vector Floating-point Multiply-Subtract Long from accumulator (by scalar).

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VFMSL (vector): Vector Floating-point Multiply-Subtract Long from accumulator (vector).

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VFNMA: Vector Fused Negate Multiply Accumulate.

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VFNMS: Vector Fused Negate Multiply Subtract.

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VJCVT: Javascript Convert to signed fixed-point, rounding toward Zero.

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VLD1 (multiple single elements): Load multiple single 1-element structures to one, two, three, or four registers.

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VLD1 (single element to all lanes): Load single 1-element structure and replicate to all lanes of one register.

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VLD1 (single element to one lane): Load single 1-element structure to one lane of one register.

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VLD2 (multiple 2-element structures): Load multiple 2-element structures to two or four registers.

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VLD2 (single 2-element structure to all lanes): Load single 2-element structure and replicate to all lanes of two registers.

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VLD2 (single 2-element structure to one lane): Load single 2-element structure to one lane of two registers.

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VLD3 (multiple 3-element structures): Load multiple 3-element structures to three registers.

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VLD3 (single 3-element structure to all lanes): Load single 3-element structure and replicate to all lanes of three registers.

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VLD3 (single 3-element structure to one lane): Load single 3-element structure to one lane of three registers.

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VLD4 (multiple 4-element structures): Load multiple 4-element structures to four registers.

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VLD4 (single 4-element structure to all lanes): Load single 4-element structure and replicate to all lanes of four registers.

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VLD4 (single 4-element structure to one lane): Load single 4-element structure to one lane of four registers.

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VLDM, VLDMDB, VLDMIA: Load Multiple SIMD&FP registers.

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VLDR (immediate): Load SIMD&FP register (immediate).

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VLDR (literal): Load SIMD&FP register (literal).

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VMAX (integer): Vector Maximum (integer).

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VMIN (integer): Vector Minimum (integer).

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VMLA (by scalar): Vector Multiply Accumulate (by scalar).

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VMLA (integer): Vector Multiply Accumulate (integer).

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VMLAL (by scalar): Vector Multiply Accumulate Long (by scalar).

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VMLAL (integer): Vector Multiply Accumulate Long (integer).

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VMLS (by scalar): Vector Multiply Subtract (by scalar).

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VMLS (integer): Vector Multiply Subtract (integer).

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VMLSL (by scalar): Vector Multiply Subtract Long (by scalar).

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VMLSL (integer): Vector Multiply Subtract Long (integer).

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VMOV (between general-purpose register and half-precision): Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&FP register.

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VMOV (between general-purpose register and single-precision): Copy a general-purpose register to or from a 32-bit SIMD&FP register.

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VMOV (between two general-purpose registers and a doubleword floating-point register): Copy two general-purpose registers to or from a SIMD&FP register.

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VMOV (between two general-purpose registers and two single-precision registers): Copy two general-purpose registers to a pair of 32-bit SIMD&FP registers.

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VMOV (general-purpose register to scalar): Copy a general-purpose register to a vector element.

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VMOV (immediate): Copy immediate value to a SIMD&FP register.

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VMOV (register): Copy between FP registers.

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VMOV (register, SIMD): Copy between SIMD registers: an alias of VORR (register).

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VMOV (scalar to general-purpose register): Copy a vector element to a general-purpose register with sign or zero extension.

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VMRS: Move SIMD&FP Special register to general-purpose register.

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VMSR: Move general-purpose register to SIMD&FP Special register.

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VMUL (by scalar): Vector Multiply (by scalar).

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VMUL (integer and polynomial): Vector Multiply (integer and polynomial).

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VMULL (by scalar): Vector Multiply Long (by scalar).

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VMULL (integer and polynomial): Vector Multiply Long (integer and polynomial).

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VMVN (immediate): Vector Bitwise NOT (immediate).

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VMVN (register): Vector Bitwise NOT (register).

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VNMLA: Vector Negate Multiply Accumulate.

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VORN (immediate): Vector Bitwise OR NOT (immediate): an alias of VORR (immediate).

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VORN (register): Vector bitwise OR NOT (register).

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VORR (immediate): Vector Bitwise OR (immediate).

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VORR (register): Vector bitwise OR (register).

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VPADAL: Vector Pairwise Add and Accumulate Long.

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VPADD (integer): Vector Pairwise Add (integer).

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VPMAX (integer): Vector Pairwise Maximum (integer).

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VPMIN (integer): Vector Pairwise Minimum (integer).

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VPOP: Pop SIMD&FP registers from stack: an alias of VLDM, VLDMDB, VLDMIA.

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VPUSH: Push SIMD&FP registers to stack: an alias of VSTM, VSTMDB, VSTMIA.

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VQDMLAL: Vector Saturating Doubling Multiply Accumulate Long.

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VQDMLSL: Vector Saturating Doubling Multiply Subtract Long.

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VQDMULH: Vector Saturating Doubling Multiply Returning High Half.

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VQDMULL: Vector Saturating Doubling Multiply Long.

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VQMOVN, VQMOVUN: Vector Saturating Move and Narrow.

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VQRDMLAH: Vector Saturating Rounding Doubling Multiply Accumulate Returning High Half.

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VQRDMLSH: Vector Saturating Rounding Doubling Multiply Subtract Returning High Half.

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VQRDMULH: Vector Saturating Rounding Doubling Multiply Returning High Half.

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VQRSHL: Vector Saturating Rounding Shift Left.

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VQRSHRN (zero): Vector Saturating Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.

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VQRSHRN, VQRSHRUN: Vector Saturating Rounding Shift Right, Narrow.

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VQRSHRUN (zero): Vector Saturating Rounding Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.

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VQSHL (register): Vector Saturating Shift Left (register).

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VQSHL, VQSHLU (immediate): Vector Saturating Shift Left (immediate).

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VQSHRN (zero): Vector Saturating Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.

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VQSHRN, VQSHRUN: Vector Saturating Shift Right, Narrow.

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VQSHRUN (zero): Vector Saturating Shift Right, Narrow: an alias of VQMOVN, VQMOVUN.

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VRADDHN: Vector Rounding Add and Narrow, returning High Half.

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VRINTA (Advanced SIMD): Vector Round floating-point to integer towards Nearest with Ties to Away.

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VRINTA (floating-point): Round floating-point to integer to Nearest with Ties to Away.

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VRINTM (Advanced SIMD): Vector Round floating-point to integer towards -Infinity.

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VRINTM (floating-point): Round floating-point to integer towards -Infinity.

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VRINTN (Advanced SIMD): Vector Round floating-point to integer to Nearest.

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VRINTN (floating-point): Round floating-point to integer to Nearest.

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VRINTP (Advanced SIMD): Vector Round floating-point to integer towards +Infinity.

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VRINTP (floating-point): Round floating-point to integer towards +Infinity.

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VRINTR: Round floating-point to integer.

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VRINTX (Advanced SIMD): Vector round floating-point to integer inexact.

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VRINTX (floating-point): Round floating-point to integer inexact.

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VRINTZ (Advanced SIMD): Vector round floating-point to integer towards Zero.

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VRINTZ (floating-point): Round floating-point to integer towards Zero.

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VRSHR (zero): Vector Rounding Shift Right: an alias of VORR (register).

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VRSHRN: Vector Rounding Shift Right and Narrow.

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VRSHRN (zero): Vector Rounding Shift Right and Narrow: an alias of VMOVN.

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VRSQRTE: Vector Reciprocal Square Root Estimate.

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VRSQRTS: Vector Reciprocal Square Root Step.

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VRSRA: Vector Rounding Shift Right and Accumulate.

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VRSUBHN: Vector Rounding Subtract and Narrow, returning High Half.

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VSDOT (by element): Dot Product index form with signed integers.

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VSDOT (vector): Dot Product vector form with signed integers.

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VSELEQ, VSELGE, VSELGT, VSELVS: Floating-point conditional select.

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VSHL (immediate): Vector Shift Left (immediate).

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VSHL (register): Vector Shift Left (register).

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VSHR (zero): Vector Shift Right: an alias of VORR (register).

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VSHRN (zero): Vector Shift Right Narrow: an alias of VMOVN.

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VSMMLA: Widening 8-bit signed integer matrix multiply-accumulate into 2x2 matrix.

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VSRA: Vector Shift Right and Accumulate.

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VST1 (multiple single elements): Store multiple single elements from one, two, three, or four registers.

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VST1 (single element from one lane): Store single element from one lane of one register.

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VST2 (multiple 2-element structures): Store multiple 2-element structures from two or four registers.

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VST2 (single 2-element structure from one lane): Store single 2-element structure from one lane of two registers.

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VST3 (multiple 3-element structures): Store multiple 3-element structures from three registers.

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VST3 (single 3-element structure from one lane): Store single 3-element structure from one lane of three registers.

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VST4 (multiple 4-element structures): Store multiple 4-element structures from four registers.

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VST4 (single 4-element structure from one lane): Store single 4-element structure from one lane of four registers.

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VSTM, VSTMDB, VSTMIA: Store multiple SIMD&FP registers.

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VSUB (integer): Vector Subtract (integer).

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VSUBHN: Vector Subtract and Narrow, returning High Half.

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VSUDOT (by element): Dot Product index form with signed and unsigned integers (by element).

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VTBL, VTBX: Vector Table Lookup and Extension.

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VUDOT (by element): Dot Product index form with unsigned integers.

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VUDOT (vector): Dot Product vector form with unsigned integers.

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VUMMLA: Widening 8-bit unsigned integer matrix multiply-accumulate into 2x2 matrix.

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VUSDOT (by element): Dot Product index form with unsigned and signed integers (by element).

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VUSDOT (vector): Dot Product vector form with mixed-sign integers.

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VUSMMLA: Widening 8-bit mixed integer matrix multiply-accumulate into 2x2 matrix.

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VUZP (alias): Vector Unzip: an alias of VTRN.

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VZIP (alias): Vector Zip: an alias of VTRN.

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Load/Store Word, Unsigned Byte (immediate, literal)

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Load/Store Word, Unsigned Byte (register)

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Branch, branch with link, and block data transfer

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System register access, Advanced SIMD, floating-point, and Supervisor call

# metadata.contentDescription
This document provides descriptions in HTML format for the A-profile A32 and T32 Instruction Set Architecture.