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Cortex-A17 MPCore Processor Technical Reference Manual r1p1

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ARM Cortex-A17 MPCore Processor Technical Reference Manual

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About the Cortex-A17 MPCore processor functions

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Accelerator Coherency Port AXI slave interface

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Performance Monitoring Unit (PMU) interface

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Security Extensions write access disable

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Large Physical Address Extension architecture

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Auxiliary Instruction Fault Status Register

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Hyp Auxiliary Data Fault Status Syndrome Register

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Hyp Auxiliary Instruction Fault Status Syndrome Register

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Auxiliary Memory Attribute Indirection Register 0

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Auxiliary Memory Attribute Indirection Register 1

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Hyp Auxiliary Memory Attribute Indirection Register 0

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Hyp Auxiliary Memory Attribute Indirection Register 1

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Instruction cache speculative memory accesses

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Inter-dependencies between the Peripheral Port and the ACE master interface

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Device Powerdown and Reset Control Register

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Interaction with the performance monitoring unit

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Effect of debug OS double lock on trace register access

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Extended External Input Selection Register

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Programmers model for NEON and floating-point unit

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Accessing the Advanced SIMD and VFP feature identification registers

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Enabling Advanced SIMD and VFP extensions

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Peripheral port AXI master interface signals

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This is the Technical Reference Manual for the ARM Cortex-A17 MPCore processor.