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Arm Cortex-A53 MPCore Processor Technical Reference Manual r0p4

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Arm Cortex-A53 MPCore Processor Technical Reference Manual

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About the Cortex-A53 processor functions

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Advanced SIMD and floating-point Extension

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Communication to the Power Management Controller

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Advanced SIMD and floating-point support

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AArch32 registers affected by CP15SDISABLE

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AArch64 virtual memory control registers

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AArch32 Instruction Set Attribute Register 0

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AArch32 Instruction Set Attribute Register 1

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AArch32 Instruction Set Attribute Register 2

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AArch32 Instruction Set Attribute Register 3

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AArch32 Instruction Set Attribute Register 4

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AArch32 Instruction Set Attribute Register 5

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AArch64 Instruction Set Attribute Register 0, EL1

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AArch64 Memory Model Feature Register 0, EL1

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Architectural Feature Access Control Register

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Architectural Feature Trap Register, EL2

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Architectural Feature Trap Register, EL3

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Monitor Debug Configuration Register, EL3

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Virtualization Translation Control Register, EL2

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Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3

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Auxiliary Fault Status Register 0, EL1, EL2 and EL3

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Auxiliary Fault Status Register 1, EL1, EL2 and EL3

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Hypervisor IPA Fault Address Register, EL2

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Memory Attribute Indirection Register, EL1

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Memory Attribute Indirection Register, EL2

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Memory Attribute Indirection Register, EL3

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Configuration Base Address Register, EL1

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AArch32 Virtual memory control registers

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Architectural Feature Access Control Register

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Auxiliary Instruction Fault Status Register

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Hyp Auxiliary Data Fault Status Syndrome Register

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Hyp Auxiliary Instruction Fault Status Syndrome Register

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Memory Attribute Indirection Registers 0 and 1

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Auxiliary Memory Attribute Indirection Register 0

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Auxiliary Memory Attribute Indirection Register 1

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Hyp Auxiliary Memory Attribute Indirection Register 0

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Hyp Auxiliary Memory Attribute Indirection Register 1

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Instruction cache speculative memory accesses

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Generic Interrupt Controller CPU Interface

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Virtual interface control register summary

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Virtual interface control register descriptions

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Virtual CPU interface register descriptions

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External Debug Integration Mode Control Register

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Performance Monitors Common Event Identification Register 0

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Performance Monitors Common Event Identification Register 1

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Performance Monitors Common Event Identification Register 0

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Performance Monitors Common Event Identification Register 1

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ETM trace unit generation options and resources

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Programming and reading ETM trace unit registers

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Sequencer State Transition Control Registers 0-2

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Resource Selection Control Registers 2-16

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Single-Shot Comparator Control Register 0

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Single-Shot Comparator Status Register 0

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Address Comparator Access Type Registers 0-7

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Context ID Comparator Control Register 0

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Integration Instruction ATB Data Register

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Integration Instruction ATB Out Register

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Interaction with debug and performance monitoring unit

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Interaction with the performance monitoring unit

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Effect of debug double lock on trace register access

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Transmit request virtual channel signals

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Transmit response virtual channel signals

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Receive response virtual channel signals

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Coherency data channel handshake signals

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unpredictable instructions within an IT Block

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Load/Store accesses crossing page boundaries

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Crossing a page boundary with different memory types or shareability attributes

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Crossing a 4KB boundary with a Device (or Strongly-Ordered) accesses

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A32 BKPT instruction with condition code not AL

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Address match breakpoint match only on second halfword of an instruction

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Address matching breakpoint on A32 instruction with DBGBCRn.BAS=1100

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Address match breakpoint match on T32 instruction at DBGBCRn+2 with DBGBCRn.BAS=1111

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Address mismatch breakpoint match on T32 instruction at DBGBCRn +2 with DBGBCRn.BAS=1111

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Other mismatch breakpoint matches any address in current mode and state

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Link to nonexistent breakpoint or breakpoint that is not context-aware

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Address-matching  Vector catch on 32-bit T32 instruction at (vector-2)

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Address-matching Vector catch on 32-bit T32 instruction at (vector+2)

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Address-matching Vector catch and Breakpoint on same instruction

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DBGWCRn_EL1.BAS specifies a non-contiguous set of bytes within a double-word

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A32 HLT instruction with condition code not AL

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Execute instruction at a given EL when the corresponding EDECCR bit is 1 and Halting is allowed

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Unlinked Context matching and Address mismatch breakpoints taken to Abort mode

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Vector catch on Data or Prefetch abort, and taken to Abort mode

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H > N or H = 0 at Non-secure EL1 and EL0, including value read from PMCR_EL0.N

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H > N or H = 0: value read back in MDCR_EL2.HPMN

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P ≥ M and P ≠ 31: reads and writes of PMXEVTYPER_EL0 and PMXEVCNTR_EL0

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P ≥ M and P ≠ 31: value read in PMSELR_EL0.SEL

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P = 31: reads and writes of PMXEVCNTR_EL0

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n ≥ M: Direct access to PMEVCNTRn_EL0 and PMEVTYPERn_EL0

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Exiting Debug state while instruction issued through EDITR is in flight

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Using memory-access mode with a non-word-aligned address

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Access to memory-mapped registers mapped to Normal memory

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Not word-sized accesses or (AArch64 only) doubleword-sized accesses

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External debug write to register that is being reset

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Clearing the clear-after-read EDPRSR bits when Core power domain is on, and DoubleLockStatus() is TRUE

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CSSELR indicates a cache that is not implemented

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HDCR.HPMN is set to 0, or to a value larger than PMCR.N

# metadata.contentDescription
This book is the Technical Reference Manual (TRM) for the Embedded Trace Macrocell for the Cortex-A53 MPCore processor.