# title
Arm Architecture Reference Manual for A-profile architecture

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Arm® Architecture Reference Manual, for A-profile
architecture

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Part A,
Introduction and Architecture Overview

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Part A,
Introduction and Architecture Overview

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Part B, The
AArch64 Application Level Architecture

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Part B, The
AArch64 Application Level Architecture

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Part D, The
AArch64 System Level Architecture

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Part D, The
AArch64 System Level Architecture

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Part E, The
AArch32 Application Level Architecture

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Part E, The
AArch32 Application Level Architecture

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Part G, The
AArch32 System Level Architecture

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Part G, The
AArch32 System Level Architecture

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Part I,
Memory-mapped Components of the Arm architecture

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Part I,
Memory-mapped Components of the Arm architecture

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​Part A Arm Architecture Introduction and
Overview

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​Chapter A1 Introduction to the Arm
Architecture

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​A1.4.8 Conversion between floating-point
and fixed-point values

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​A1.4.8 Conversion between floating-point
and fixed-point values

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​A1.4.9 Polynomial arithmetic over {0,
1}

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​A1.4.9 Polynomial arithmetic over {0,
1}

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​A1.5.3 Arm standard floating-point input
and output values

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​A1.5.3 Arm standard floating-point input
and output values

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​A1.5.4 Summary of BFloat16 instruction
behaviors

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​A1.5.4 Summary of BFloat16 instruction
behaviors

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​A1.5.5
Summary of FP8 instruction behaviors

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​A1.5.5
Summary of FP8 instruction behaviors

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​A1.5.6 Flushing denormalized numbers to
zero

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​A1.5.6 Flushing denormalized numbers to
zero

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​A1.5.7 NaN handling and the Default
NaN

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​A1.5.7 NaN handling and the Default
NaN

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​A1.5.9 Floating-point exceptions and
exception traps

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​A1.5.9 Floating-point exceptions and
exception traps

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​A1.5.11 BFloat16 behaviors for instructions
that compute sum-of-products

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​A1.5.11 BFloat16 behaviors for instructions
that compute sum-of-products

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​Chapter A1 Introduction to the Arm
Architecture

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​Chapter A2 A-profile Architecture
Extensions

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​A2.1 About the A-profile architecture
extensions

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​A2.1.1 Permitted implementation of subsets
of the A-profile architectural features

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​A2.1.1 Permitted implementation of subsets
of the A-profile architectural features

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​A2.1 About the A-profile architecture
extensions

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​A2.2.1 The
Armv8.0 architecture extension

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​A2.2.1 The
Armv8.0 architecture extension

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​A2.2.2 The
Armv8.1 architecture extension

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​A2.2.2 The
Armv8.1 architecture extension

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​A2.2.3 The
Armv8.2 architecture extension

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​A2.2.3 The
Armv8.2 architecture extension

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​A2.2.4 The
Armv8.3 architecture extension

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​A2.2.4 The
Armv8.3 architecture extension

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​A2.2.5 The
Armv8.4 architecture extension

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​A2.2.5 The
Armv8.4 architecture extension

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​A2.2.6 The
Armv8.5 architecture extension

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​A2.2.6 The
Armv8.5 architecture extension

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​A2.2.7 The
Armv8.6 architecture extension

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​A2.2.7 The
Armv8.6 architecture extension

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​A2.2.8 The
Armv8.7 architecture extension

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​A2.2.8 The
Armv8.7 architecture extension

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​A2.2.9 The
Armv8.8 architecture extension

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​A2.2.9 The
Armv8.8 architecture extension

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​A2.2.10 The
Armv8.9 architecture extension

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​A2.2.10 The
Armv8.9 architecture extension

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​A2.3.1 The
Armv9.0 architecture extension

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​A2.3.1 The
Armv9.0 architecture extension

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​A2.3.2 The
Armv9.1 architecture extension

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​A2.3.2 The
Armv9.1 architecture extension

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​A2.3.3 The
Armv9.2 architecture extension

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​A2.3.3 The
Armv9.2 architecture extension

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​A2.3.4 The
Armv9.3 architecture extension

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​A2.3.4 The
Armv9.3 architecture extension

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​A2.3.5 The
Armv9.4 architecture extension

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​A2.3.5 The
Armv9.4 architecture extension

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​A2.3.6 The
Armv9.5 architecture extension

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​A2.3.6 The
Armv9.5 architecture extension

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​A2.3.7 The
Armv9.6 architecture extension

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​A2.3.7 The
Armv9.6 architecture extension

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​Chapter A2 A-profile Architecture
Extensions

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​Part A Arm Architecture Introduction and
Overview

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​Part B The AArch64 Application Level
Architecture

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​Chapter B1 The AArch64 Application Level
Programmers’ Model

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​B1.1 About the Application level
programmers’ model

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​B1.1 About the Application level
programmers’ model

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​B1.2 Registers in AArch64 Execution
state

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​B1.2.3 Pseudocode description of registers
in AArch64 state

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​B1.2.3 Pseudocode description of registers
in AArch64 state

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​B1.2 Registers in AArch64 Execution
state

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​B1.3.2 SVE use of PSTATE N, Z, C, and V
Condition flags

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​B1.3.2 SVE use of PSTATE N, Z, C, and V
Condition flags

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​B1.4 The Scalable Vector and Scalable
Matrix Extensions (SVE & SME)

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​B1.4.1 Maximum implemented SVE vector
lengths

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​B1.4.1 Maximum implemented SVE vector
lengths

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​B1.4.3 Treatment of SVE scalable vector
registers

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​B1.4.3 Treatment of SVE scalable vector
registers

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​B1.4.4 SVE writes of scalar values to
registers

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​B1.4.4 SVE writes of scalar values to
registers

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​B1.4 The Scalable Vector and Scalable
Matrix Extensions (SVE & SME)

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​B1.5.2 Wait for Interrupt and Wait for
Event

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​B1.5.2 Wait for Interrupt and Wait for
Event

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​B1.5.4 Application level cache
management

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​B1.5.4 Application level cache
management

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​Chapter B1 The AArch64 Application Level
Programmers’ Model

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​Chapter B2 The AArch64 Application Level
Memory Model

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​B2.2.1 Requirements for single-copy
atomicity

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​B2.2.1 Requirements for single-copy
atomicity

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​B2.2.2 Properties of single-copy atomic
accesses

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​B2.2.2 Properties of single-copy atomic
accesses

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​B2.2.4 Requirements for multi-copy
atomicity

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​B2.2.4 Requirements for multi-copy
atomicity

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​B2.2.5 Concurrent modification and
execution of instructions (CMODX)

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​B2.2.5 Concurrent modification and
execution of instructions (CMODX)

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​B2.2.6 Possible implementation restrictions
on using atomic instructions

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​B2.2.6 Possible implementation restrictions
on using atomic instructions

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​B2.3 Ordering requirements defined by the
formal concurrency model

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​B2.3.9 Definition of an Architecturally
Allowed Execution

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​B2.3.9 Definition of an Architecturally
Allowed Execution

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​B2.3.10 Alternative formulations of the
External visibility requirement for Explicit Memory Effects

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​B2.3.10 Alternative formulations of the
External visibility requirement for Explicit Memory Effects

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​B2.3 Ordering requirements defined by the
formal concurrency model

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​B2.4 Additional ordering requirements
outside of the scope of the formal concurrency model

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​B2.4.1 Completion and endpoint
ordering

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​B2.4.1 Completion and endpoint
ordering

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​B2.4.5 Streaming SVE mode memory ordering
relaxations

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​B2.4.5 Streaming SVE mode memory ordering
relaxations

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​B2.4 Additional ordering requirements
outside of the scope of the formal concurrency model

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​B2.5 Restrictions on the effects of
speculation

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​B2.5.1 AArch64 Speculative Store Bypass
Safe

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​B2.5.1 AArch64 Speculative Store Bypass
Safe

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​B2.5.2 Definition of exploitative control
of speculative execution

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​B2.5.2 Definition of exploitative control
of speculative execution

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​B2.5.3 Definition of predictive leakage to
speculative execution

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​B2.5.3 Definition of predictive leakage to
speculative execution

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​B2.5.4 Restrictions on the effects of
speculation from Armv8.5

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​B2.5.4 Restrictions on the effects of
speculation from Armv8.5

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​B2.5.5 Restrictions on the effects of
speculation from Armv9.5

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​B2.5.5 Restrictions on the effects of
speculation from Armv9.5

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​B2.5.7 Execution, data prediction and
prefetching restriction System instructions

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​B2.5.7 Execution, data prediction and
prefetching restriction System instructions

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​B2.5 Restrictions on the effects of
speculation

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​B2.6.4 Consumption of Speculative Data
Barrier

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​B2.6.4 Consumption of Speculative Data
Barrier

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​B2.6.5 Speculative Store Bypass
Barrier

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​B2.6.5 Speculative Store Bypass
Barrier

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​B2.6.7 Physical Speculative Store Bypass
Barrier

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​B2.6.7 Physical Speculative Store Bypass
Barrier

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​B2.6.10 Shareability and access limitations
on the data barrier operations

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​B2.6.10 Shareability and access limitations
on the data barrier operations

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​B2.6.13 Guarded Control Stack Barrier
(GCSB)

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​B2.6.13 Guarded Control Stack Barrier
(GCSB)

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​B2.7.3 Application level access to
functionality related to caches

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​B2.7.3 Application level access to
functionality related to caches

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​B2.7.4 Implication of caches for the
application programmer

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​B2.7.4 Implication of caches for the
application programmer

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​B2.9.1 General description of endianness in
the Arm architecture

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​B2.9.1 General description of endianness in
the Arm architecture

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​B2.9.4 Endianness of memory-mapped
peripherals

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​B2.9.4 Endianness of memory-mapped
peripherals

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​B2.12.1 Exclusive access instructions and
Non-shareable memory locations

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​B2.12.1 Exclusive access instructions and
Non-shareable memory locations

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​B2.12.2 Exclusive access instructions and
Shareable memory locations

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​B2.12.2 Exclusive access instructions and
Shareable memory locations

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​B2.12.3 Marking and the size of the marked
memory block

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​B2.12.3 Marking and the size of the marked
memory block

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​B2.12.6 Use of WFE and SEV instructions by
spin-locks

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​B2.12.6 Use of WFE and SEV instructions by
spin-locks

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​Chapter B2 The AArch64 Application Level
Memory Model

# topic.topics[].anchors[].title
​Part B The AArch64 Application Level
Architecture

# topic.topics[].topics[].topics[].label
​C1.2 Structure of the A64 assembler
language

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​C1.2 Structure of the A64 assembler
language

# topic.topics[].topics[].label
​Chapter C2 About the A64 Instruction
Descriptions

# topic.topics[].topics[].topics[].label
​C2.1 Understanding the A64 instruction
descriptions

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​C2.1.2 An introduction to the
instruction

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​C2.1.2 An introduction to the
instruction

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​C2.1.3 The instruction encoding or
encodings

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​C2.1.3 The instruction encoding or
encodings

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​C2.1.4 Any alias conditions, if
applicable

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​C2.1.4 Any alias conditions, if
applicable

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​C2.1.5 A list of the assembler symbols for
the instruction

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​C2.1.5 A list of the assembler symbols for
the instruction

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​C2.1.6 Pseudocode describing how the
instruction operates

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​C2.1.6 Pseudocode describing how the
instruction operates

# topic.topics[].topics[].topics[].anchors[].title
​C2.1 Understanding the A64 instruction
descriptions

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​C2.2 General information about the A64
instruction descriptions

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​C2.2.1 Execution of instructions in Debug
state

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​C2.2.1 Execution of instructions in Debug
state

# topic.topics[].topics[].topics[].topics[].label
​C2.2.2 Fixed values in AArch64 instruction
and System register descriptions

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​C2.2.2 Fixed values in AArch64 instruction
and System register descriptions

# topic.topics[].topics[].topics[].topics[].label
​C2.2.3 Modified immediate constants in A64
floating-point instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C2.2.3 Modified immediate constants in A64
floating-point instructions

# topic.topics[].topics[].topics[].anchors[].title
​C2.2 General information about the A64
instruction descriptions

# topic.topics[].topics[].anchors[].title
​Chapter C2 About the A64 Instruction
Descriptions

# topic.topics[].topics[].label
​Chapter C3 A64 Instruction Set Overview

# topic.topics[].topics[].topics[].label
​C3.1 Branches, Exception generating, and
System instructions

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​C3.1.11 Checked Pointer Arithmetic
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.1.11 Checked Pointer Arithmetic
instructions

# topic.topics[].topics[].topics[].anchors[].title
​C3.1 Branches, Exception generating, and
System instructions

# topic.topics[].topics[].topics[].topics[].label
​C3.2.2 Load/store register (unscaled
offset)

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​C3.2.2 Load/store register (unscaled
offset)

# topic.topics[].topics[].topics[].topics[].label
​C3.2.8 Single-copy atomic 64-byte
load/store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.2.8 Single-copy atomic 64-byte
load/store

# topic.topics[].topics[].topics[].topics[].label
​C3.2.14 Load/store scalar SIMD and
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.2.14 Load/store scalar SIMD and
floating-point

# topic.topics[].topics[].topics[].topics[].label
​C3.2.19 Memory Copy and Memory Set
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.2.19 Memory Copy and Memory Set
instructions

# topic.topics[].topics[].topics[].topics[].label
​C3.3.1 Predicated single vector contiguous
element accesses

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.3.1 Predicated single vector contiguous
element accesses

# topic.topics[].topics[].topics[].topics[].label
​C3.3.2 Predicated multiple vector
contiguous structure load/store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.3.2 Predicated multiple vector
contiguous structure load/store

# topic.topics[].topics[].topics[].topics[].label
​C3.3.4 Predicated replicating element
loads

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.3.4 Predicated replicating element
loads

# topic.topics[].topics[].topics[].topics[].label
​C3.3.5 Unpredicated vector register
load/store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.3.5 Unpredicated vector register
load/store

# topic.topics[].topics[].topics[].label
​C3.4 Loads and stores - SME, SME2,
SVE2p1

# topic.topics[].topics[].topics[].topics[].label
​C3.4.1 Array vector/table load and
store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.4.1 Array vector/table load and
store

# topic.topics[].topics[].topics[].topics[].label
​C3.4.2 Contiguous multi-vector loads and
stores

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.4.2 Contiguous multi-vector loads and
stores

# topic.topics[].topics[].topics[].topics[].label
​C3.4.3 SVE2.1 quadword loads and
stores

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.4.3 SVE2.1 quadword loads and
stores

# topic.topics[].topics[].topics[].anchors[].title
​C3.4 Loads and stores - SME, SME2,
SVE2p1

# topic.topics[].topics[].topics[].topics[].label
​C3.5.2 Integer minimum and maximum
(immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.5.2 Integer minimum and maximum
(immediate)

# topic.topics[].topics[].topics[].topics[].label
​C3.7.4 Integer maximum and minimum
(register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.7.4 Integer maximum and minimum
(register)

# topic.topics[].topics[].topics[].label
​C3.8 Data processing - SIMD and
floating-point

# topic.topics[].topics[].topics[].topics[].label
​C3.8.1 Common features of SIMD
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.8.1 Common features of SIMD
instructions

# topic.topics[].topics[].topics[].topics[].label
​C3.8.5 Floating-point round to integral
value

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.8.5 Floating-point round to integral
value

# topic.topics[].topics[].topics[].topics[].label
​C3.8.7 Floating-point arithmetic (one
source)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.8.7 Floating-point arithmetic (one
source)

# topic.topics[].topics[].topics[].topics[].label
​C3.8.8 Floating-point arithmetic (two
sources)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.8.8 Floating-point arithmetic (two
sources)

# topic.topics[].topics[].topics[].topics[].label
​C3.8.9 Floating-point minimum and
maximum

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.8.9 Floating-point minimum and
maximum

# topic.topics[].topics[].topics[].topics[].label
​C3.8.15 SIMD widening and narrowing
arithmetic

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.8.15 SIMD widening and narrowing
arithmetic

# topic.topics[].topics[].topics[].topics[].label
​C3.8.22 SIMD reduce (across vector
lanes)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.8.22 SIMD reduce (across vector
lanes)

# topic.topics[].topics[].topics[].topics[].label
​C3.8.27 SIMD complex number arithmetic
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.8.27 SIMD complex number arithmetic
instructions

# topic.topics[].topics[].topics[].topics[].label
​C3.8.30
The Cryptographic Extension in AArch64 state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.8.30
The Cryptographic Extension in AArch64 state

# topic.topics[].topics[].topics[].anchors[].title
​C3.8 Data processing - SIMD and
floating-point

# topic.topics[].topics[].topics[].topics[].label
​C3.9.4 SVE Bitwise shift, reverse, and
count

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.9.4 SVE Bitwise shift, reverse, and
count

# topic.topics[].topics[].topics[].topics[].label
​C3.9.5 SVE Vector floating-point
operations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.9.5 SVE Vector floating-point
operations

# topic.topics[].topics[].topics[].topics[].label
​C3.10.9 Bitwise ternary logical
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.10.9 Bitwise ternary logical
instructions

# topic.topics[].topics[].topics[].topics[].label
​C3.10.11 Multiplication by indexed
elements

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.10.11 Multiplication by indexed
elements

# topic.topics[].topics[].topics[].topics[].label
​C3.10.29
Floating-point round to integral value

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.10.29
Floating-point round to integral value

# topic.topics[].topics[].topics[].topics[].label
​C3.11.4 Element concatenate and
interleave

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.11.4 Element concatenate and
interleave

# topic.topics[].topics[].topics[].topics[].label
​C3.11.16 Multi-vector shift and
convert

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.11.16 Multi-vector shift and
convert

# topic.topics[].topics[].topics[].topics[].label
​C3.11.19 Structured sparsity outer
product

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C3.11.19 Structured sparsity outer
product

# topic.topics[].topics[].anchors[].title
​Chapter C3 A64 Instruction Set Overview

# topic.topics[].topics[].label
​Chapter C4
A64 Instruction Set Encoding

# topic.topics[].topics[].anchors[].title
​Chapter C4
A64 Instruction Set Encoding

# topic.topics[].topics[].label
​Chapter C5 The A64 System Instruction
Class

# topic.topics[].topics[].topics[].label
​C5.1 The System instruction class encoding
space

# topic.topics[].topics[].topics[].topics[].label
​C5.1.1 Principles of the System instruction
class encoding

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.1.1 Principles of the System instruction
class encoding

# topic.topics[].topics[].topics[].topics[].label
​C5.1.2 System instruction class encoding
overview

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.1.2 System instruction class encoding
overview

# topic.topics[].topics[].topics[].topics[].label
​C5.1.3 op0==
0b00, architectural hints, barriers and CLREX,
and PSTATE access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.1.3 op0==
0b00, architectural hints, barriers and CLREX,
and PSTATE access

# topic.topics[].topics[].topics[].topics[].label
​C5.1.4 op0==
0b01, cache maintenance, TLB maintenance, address
translation, prediction restriction, BRBE, Trace Extension, and Guarded
Control Stack instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.1.4 op0==
0b01, cache maintenance, TLB maintenance, address
translation, prediction restriction, BRBE, Trace Extension, and Guarded
Control Stack instructions

# topic.topics[].topics[].topics[].topics[].label
​C5.1.5 op0==
0b11, Moves to and from Special-purpose registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.1.5 op0==
0b11, Moves to and from Special-purpose registers

# topic.topics[].topics[].topics[].anchors[].title
​C5.1 The System instruction class encoding
space

# topic.topics[].topics[].topics[].topics[].label
​C5.2.2
CurrentEL, Current Exception Level

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.2
CurrentEL, Current Exception Level

# topic.topics[].topics[].topics[].topics[].label
​C5.2.5
ELR_EL1, Exception Link Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.5
ELR_EL1, Exception Link Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​C5.2.6
ELR_EL2, Exception Link Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.6
ELR_EL2, Exception Link Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​C5.2.7
ELR_EL3, Exception Link Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.7
ELR_EL3, Exception Link Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​C5.2.8
FPCR, Floating-point Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.8
FPCR, Floating-point Control Register

# topic.topics[].topics[].topics[].topics[].label
​C5.2.9
FPMR, Floating-point Mode Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.9
FPMR, Floating-point Mode Register

# topic.topics[].topics[].topics[].topics[].label
​C5.2.10
FPSR, Floating-point Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.10
FPSR, Floating-point Status Register

# topic.topics[].topics[].topics[].topics[].label
​C5.2.19
SPSR_abt, Saved Program Status Register (Abort mode)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.19
SPSR_abt, Saved Program Status Register (Abort mode)

# topic.topics[].topics[].topics[].topics[].label
​C5.2.20
SPSR_EL1, Saved Program Status Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.20
SPSR_EL1, Saved Program Status Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​C5.2.21
SPSR_EL2, Saved Program Status Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.21
SPSR_EL2, Saved Program Status Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​C5.2.22
SPSR_EL3, Saved Program Status Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.22
SPSR_EL3, Saved Program Status Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​C5.2.23
SPSR_fiq, Saved Program Status Register (FIQ mode)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.23
SPSR_fiq, Saved Program Status Register (FIQ mode)

# topic.topics[].topics[].topics[].topics[].label
​C5.2.24
SPSR_irq, Saved Program Status Register (IRQ mode)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.24
SPSR_irq, Saved Program Status Register (IRQ mode)

# topic.topics[].topics[].topics[].topics[].label
​C5.2.25
SPSR_und, Saved Program Status Register (Undefined mode)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.25
SPSR_und, Saved Program Status Register (Undefined mode)

# topic.topics[].topics[].topics[].topics[].label
​C5.2.26
SSBS, Speculative Store Bypass Safe

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.26
SSBS, Speculative Store Bypass Safe

# topic.topics[].topics[].topics[].topics[].label
​C5.2.27
SVCR, Streaming Vector Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.2.27
SVCR, Streaming Vector Control Register

# topic.topics[].topics[].topics[].label
​C5.3 A64 System instructions for cache
maintenance

# topic.topics[].topics[].topics[].topics[].label
​C5.3.1
DC CGDSW, Clean of Data and Allocation Tags by Set/Way

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.1
DC CGDSW, Clean of Data and Allocation Tags by Set/Way

# topic.topics[].topics[].topics[].topics[].label
​C5.3.2
DC CGDVAC, Clean of Data and Allocation Tags by VA to
PoC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.2
DC CGDVAC, Clean of Data and Allocation Tags by VA to
PoC

# topic.topics[].topics[].topics[].topics[].label
​C5.3.3
DC CGDVADP, Clean of Data and Allocation Tags by VA to
PoDP

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.3
DC CGDVADP, Clean of Data and Allocation Tags by VA to
PoDP

# topic.topics[].topics[].topics[].topics[].label
​C5.3.4
DC CGDVAOC, Clean of Data and Allocation Tags by VA to Outer
Cache level

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.4
DC CGDVAOC, Clean of Data and Allocation Tags by VA to Outer
Cache level

# topic.topics[].topics[].topics[].topics[].label
​C5.3.5
DC CGDVAP, Clean of Data and Allocation Tags by VA to
PoP

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.5
DC CGDVAP, Clean of Data and Allocation Tags by VA to
PoP

# topic.topics[].topics[].topics[].topics[].label
​C5.3.6
DC CGSW, Clean of Allocation Tags by Set/Way

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.6
DC CGSW, Clean of Allocation Tags by Set/Way

# topic.topics[].topics[].topics[].topics[].label
​C5.3.7
DC CGVAC, Clean of Allocation Tags by VA to PoC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.7
DC CGVAC, Clean of Allocation Tags by VA to PoC

# topic.topics[].topics[].topics[].topics[].label
​C5.3.8
DC CGVADP, Clean of Allocation Tags by VA to PoDP

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.8
DC CGVADP, Clean of Allocation Tags by VA to PoDP

# topic.topics[].topics[].topics[].topics[].label
​C5.3.9
DC CGVAP, Clean of Allocation Tags by VA to PoP

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.9
DC CGVAP, Clean of Allocation Tags by VA to PoP

# topic.topics[].topics[].topics[].topics[].label
​C5.3.10
DC CIGDPAE, Clean and invalidate of data and allocation tags by
PA to PoE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.10
DC CIGDPAE, Clean and invalidate of data and allocation tags by
PA to PoE

# topic.topics[].topics[].topics[].topics[].label
​C5.3.11
DC CIGDPAPA, Clean and Invalidate of Data and Allocation Tags by
PA to PoPA

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.11
DC CIGDPAPA, Clean and Invalidate of Data and Allocation Tags by
PA to PoPA

# topic.topics[].topics[].topics[].topics[].label
​C5.3.12
DC CIGDSW, Clean and Invalidate of Data and Allocation Tags by
Set/Way

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.12
DC CIGDSW, Clean and Invalidate of Data and Allocation Tags by
Set/Way

# topic.topics[].topics[].topics[].topics[].label
​C5.3.13
DC CIGDVAC, Clean and Invalidate of Data and Allocation Tags by
VA to PoC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.13
DC CIGDVAC, Clean and Invalidate of Data and Allocation Tags by
VA to PoC

# topic.topics[].topics[].topics[].topics[].label
​C5.3.14
DC CIGDVAOC, Clean and Invalidate of Data and Allocation Tags by
VA to Outer Cache level

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.14
DC CIGDVAOC, Clean and Invalidate of Data and Allocation Tags by
VA to Outer Cache level

# topic.topics[].topics[].topics[].topics[].label
​C5.3.15
DC CIGDVAPS, Clean and Invalidate of Data and Allocation Tags by
VA to PoPS

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.15
DC CIGDVAPS, Clean and Invalidate of Data and Allocation Tags by
VA to PoPS

# topic.topics[].topics[].topics[].topics[].label
​C5.3.16
DC CIGSW, Clean and Invalidate of Allocation Tags by
Set/Way

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.16
DC CIGSW, Clean and Invalidate of Allocation Tags by
Set/Way

# topic.topics[].topics[].topics[].topics[].label
​C5.3.17
DC CIGVAC, Clean and Invalidate of Allocation Tags by VA to
PoC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.17
DC CIGVAC, Clean and Invalidate of Allocation Tags by VA to
PoC

# topic.topics[].topics[].topics[].topics[].label
​C5.3.18
DC CIPAE, Data or unified Cache line Clean and Invalidate by PA
to PoE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.18
DC CIPAE, Data or unified Cache line Clean and Invalidate by PA
to PoE

# topic.topics[].topics[].topics[].topics[].label
​C5.3.19
DC CIPAPA, Data or unified Cache line Clean and Invalidate by PA
to PoPA

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.19
DC CIPAPA, Data or unified Cache line Clean and Invalidate by PA
to PoPA

# topic.topics[].topics[].topics[].topics[].label
​C5.3.20
DC CISW, Data or unified Cache line Clean and Invalidate by
Set/Way

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.20
DC CISW, Data or unified Cache line Clean and Invalidate by
Set/Way

# topic.topics[].topics[].topics[].topics[].label
​C5.3.21
DC CIVAC, Data or unified Cache line Clean and Invalidate by VA
to PoC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.21
DC CIVAC, Data or unified Cache line Clean and Invalidate by VA
to PoC

# topic.topics[].topics[].topics[].topics[].label
​C5.3.22
DC CIVAOC, Data or unified Cache line Clean and Invalidate by VA
to Outer Cache level

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.22
DC CIVAOC, Data or unified Cache line Clean and Invalidate by VA
to Outer Cache level

# topic.topics[].topics[].topics[].topics[].label
​C5.3.23
DC CIVAPS, Clean and Invalidate of Data by VA to PoPS

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.23
DC CIVAPS, Clean and Invalidate of Data by VA to PoPS

# topic.topics[].topics[].topics[].topics[].label
​C5.3.24
DC CSW, Data or unified Cache line Clean by Set/Way

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.24
DC CSW, Data or unified Cache line Clean by Set/Way

# topic.topics[].topics[].topics[].topics[].label
​C5.3.25
DC CVAC, Data or unified Cache line Clean by VA to PoC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.25
DC CVAC, Data or unified Cache line Clean by VA to PoC

# topic.topics[].topics[].topics[].topics[].label
​C5.3.26
DC CVADP, Data or unified Cache line Clean by VA to PoDP

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.26
DC CVADP, Data or unified Cache line Clean by VA to PoDP

# topic.topics[].topics[].topics[].topics[].label
​C5.3.27
DC CVAOC, Data or unified Cache line Clean by VA to Outer Cache
level

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.27
DC CVAOC, Data or unified Cache line Clean by VA to Outer Cache
level

# topic.topics[].topics[].topics[].topics[].label
​C5.3.28
DC CVAP, Data or unified Cache line Clean by VA to PoP

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.28
DC CVAP, Data or unified Cache line Clean by VA to PoP

# topic.topics[].topics[].topics[].topics[].label
​C5.3.29
DC CVAU, Data or unified Cache line Clean by VA to PoU

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.29
DC CVAU, Data or unified Cache line Clean by VA to PoU

# topic.topics[].topics[].topics[].topics[].label
​C5.3.30
DC GVA, Data Cache set Allocation Tag by VA

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.30
DC GVA, Data Cache set Allocation Tag by VA

# topic.topics[].topics[].topics[].topics[].label
​C5.3.31
DC GZVA, Data Cache set Allocation Tags and Zero by VA

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.31
DC GZVA, Data Cache set Allocation Tags and Zero by VA

# topic.topics[].topics[].topics[].topics[].label
​C5.3.32
DC IGDSW, Invalidate of Data and Allocation Tags by
Set/Way

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.32
DC IGDSW, Invalidate of Data and Allocation Tags by
Set/Way

# topic.topics[].topics[].topics[].topics[].label
​C5.3.33
DC IGDVAC, Invalidate of Data and Allocation Tags by VA to
PoC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.33
DC IGDVAC, Invalidate of Data and Allocation Tags by VA to
PoC

# topic.topics[].topics[].topics[].topics[].label
​C5.3.34
DC IGSW, Invalidate of Allocation Tags by Set/Way

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.34
DC IGSW, Invalidate of Allocation Tags by Set/Way

# topic.topics[].topics[].topics[].topics[].label
​C5.3.35
DC IGVAC, Invalidate of Allocation Tags by VA to PoC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.35
DC IGVAC, Invalidate of Allocation Tags by VA to PoC

# topic.topics[].topics[].topics[].topics[].label
​C5.3.36
DC ISW, Data or unified Cache line Invalidate by Set/Way

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.36
DC ISW, Data or unified Cache line Invalidate by Set/Way

# topic.topics[].topics[].topics[].topics[].label
​C5.3.37
DC IVAC, Data or unified Cache line Invalidate by VA to
PoC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.37
DC IVAC, Data or unified Cache line Invalidate by VA to
PoC

# topic.topics[].topics[].topics[].topics[].label
​C5.3.39
IC IALLU, Instruction Cache Invalidate All to PoU

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.39
IC IALLU, Instruction Cache Invalidate All to PoU

# topic.topics[].topics[].topics[].topics[].label
​C5.3.40
IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.40
IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.3.41
IC IVAU, Instruction Cache line Invalidate by VA to PoU

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.3.41
IC IVAU, Instruction Cache line Invalidate by VA to PoU

# topic.topics[].topics[].topics[].anchors[].title
​C5.3 A64 System instructions for cache
maintenance

# topic.topics[].topics[].topics[].label
​C5.4 A64 System instructions for address
translation

# topic.topics[].topics[].topics[].topics[].label
​C5.4.1
AT S12E0R, Address Translate Stages 1 and 2 EL0 Read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.1
AT S12E0R, Address Translate Stages 1 and 2 EL0 Read

# topic.topics[].topics[].topics[].topics[].label
​C5.4.2
AT S12E0W, Address Translate Stages 1 and 2 EL0 Write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.2
AT S12E0W, Address Translate Stages 1 and 2 EL0 Write

# topic.topics[].topics[].topics[].topics[].label
​C5.4.3
AT S12E1R, Address Translate Stages 1 and 2 EL1 Read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.3
AT S12E1R, Address Translate Stages 1 and 2 EL1 Read

# topic.topics[].topics[].topics[].topics[].label
​C5.4.4
AT S12E1W, Address Translate Stages 1 and 2 EL1 Write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.4
AT S12E1W, Address Translate Stages 1 and 2 EL1 Write

# topic.topics[].topics[].topics[].topics[].label
​C5.4.5
AT S1E0R, Address Translate Stage 1 EL0 Read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.5
AT S1E0R, Address Translate Stage 1 EL0 Read

# topic.topics[].topics[].topics[].topics[].label
​C5.4.6
AT S1E0W, Address Translate Stage 1 EL0 Write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.6
AT S1E0W, Address Translate Stage 1 EL0 Write

# topic.topics[].topics[].topics[].topics[].label
​C5.4.7
AT S1E1A, Address Translate Stage 1 EL1 Without Permission
checks

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.7
AT S1E1A, Address Translate Stage 1 EL1 Without Permission
checks

# topic.topics[].topics[].topics[].topics[].label
​C5.4.8
AT S1E1R, Address Translate Stage 1 EL1 Read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.8
AT S1E1R, Address Translate Stage 1 EL1 Read

# topic.topics[].topics[].topics[].topics[].label
​C5.4.9
AT S1E1RP, Address Translate Stage 1 EL1 Read PAN

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.9
AT S1E1RP, Address Translate Stage 1 EL1 Read PAN

# topic.topics[].topics[].topics[].topics[].label
​C5.4.10
AT S1E1W, Address Translate Stage 1 EL1 Write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.10
AT S1E1W, Address Translate Stage 1 EL1 Write

# topic.topics[].topics[].topics[].topics[].label
​C5.4.11
AT S1E1WP, Address Translate Stage 1 EL1 Write PAN

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.11
AT S1E1WP, Address Translate Stage 1 EL1 Write PAN

# topic.topics[].topics[].topics[].topics[].label
​C5.4.12
AT S1E2A, Address Translate Stage 1 EL2 Without Permission
checks

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.12
AT S1E2A, Address Translate Stage 1 EL2 Without Permission
checks

# topic.topics[].topics[].topics[].topics[].label
​C5.4.13
AT S1E2R, Address Translate Stage 1 EL2 Read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.13
AT S1E2R, Address Translate Stage 1 EL2 Read

# topic.topics[].topics[].topics[].topics[].label
​C5.4.14
AT S1E2W, Address Translate Stage 1 EL2 Write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.14
AT S1E2W, Address Translate Stage 1 EL2 Write

# topic.topics[].topics[].topics[].topics[].label
​C5.4.15
AT S1E3A, Address Translate Stage 1 EL3 Without Permission
checks

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.15
AT S1E3A, Address Translate Stage 1 EL3 Without Permission
checks

# topic.topics[].topics[].topics[].topics[].label
​C5.4.16
AT S1E3R, Address Translate Stage 1 EL3 Read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.16
AT S1E3R, Address Translate Stage 1 EL3 Read

# topic.topics[].topics[].topics[].topics[].label
​C5.4.17
AT S1E3W, Address Translate Stage 1 EL3 Write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.4.17
AT S1E3W, Address Translate Stage 1 EL3 Write

# topic.topics[].topics[].topics[].anchors[].title
​C5.4 A64 System instructions for address
translation

# topic.topics[].topics[].topics[].label
​C5.5 A64 System instructions for TLB
maintenance

# topic.topics[].topics[].topics[].topics[].label
​C5.5.1
TLBI ALLE1, TLBI ALLE1NXS, TLB Invalidate All, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.1
TLBI ALLE1, TLBI ALLE1NXS, TLB Invalidate All, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.2
TLBI ALLE1IS, TLBI ALLE1ISNXS, TLB Invalidate All, EL1, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.2
TLBI ALLE1IS, TLBI ALLE1ISNXS, TLB Invalidate All, EL1, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.3
TLBI ALLE1OS, TLBI ALLE1OSNXS, TLB Invalidate All, EL1, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.3
TLBI ALLE1OS, TLBI ALLE1OSNXS, TLB Invalidate All, EL1, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.4
TLBI ALLE2, TLBI ALLE2NXS, TLB Invalidate All, EL2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.4
TLBI ALLE2, TLBI ALLE2NXS, TLB Invalidate All, EL2

# topic.topics[].topics[].topics[].topics[].label
​C5.5.5
TLBI ALLE2IS, TLBI ALLE2ISNXS, TLB Invalidate All, EL2, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.5
TLBI ALLE2IS, TLBI ALLE2ISNXS, TLB Invalidate All, EL2, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.6
TLBI ALLE2OS, TLBI ALLE2OSNXS, TLB Invalidate All, EL2, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.6
TLBI ALLE2OS, TLBI ALLE2OSNXS, TLB Invalidate All, EL2, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.7
TLBI ALLE3, TLBI ALLE3NXS, TLB Invalidate All, EL3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.7
TLBI ALLE3, TLBI ALLE3NXS, TLB Invalidate All, EL3

# topic.topics[].topics[].topics[].topics[].label
​C5.5.8
TLBI ALLE3IS, TLBI ALLE3ISNXS, TLB Invalidate All, EL3, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.8
TLBI ALLE3IS, TLBI ALLE3ISNXS, TLB Invalidate All, EL3, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.9
TLBI ALLE3OS, TLBI ALLE3OSNXS, TLB Invalidate All, EL3, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.9
TLBI ALLE3OS, TLBI ALLE3OSNXS, TLB Invalidate All, EL3, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.10
TLBI ASIDE1, TLBI ASIDE1NXS, TLB Invalidate by ASID, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.10
TLBI ASIDE1, TLBI ASIDE1NXS, TLB Invalidate by ASID, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.11
TLBI ASIDE1IS, TLBI ASIDE1ISNXS, TLB Invalidate by ASID, EL1,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.11
TLBI ASIDE1IS, TLBI ASIDE1ISNXS, TLB Invalidate by ASID, EL1,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.12
TLBI ASIDE1OS, TLBI ASIDE1OSNXS, TLB Invalidate by ASID, EL1,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.12
TLBI ASIDE1OS, TLBI ASIDE1OSNXS, TLB Invalidate by ASID, EL1,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.13
TLBI IPAS2E1, TLBI IPAS2E1NXS, TLB Invalidate by Intermediate
Physical Address, Stage 2, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.13
TLBI IPAS2E1, TLBI IPAS2E1NXS, TLB Invalidate by Intermediate
Physical Address, Stage 2, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.14
TLBI IPAS2E1IS, TLBI IPAS2E1ISNXS, TLB Invalidate by Intermediate
Physical Address, Stage 2, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.14
TLBI IPAS2E1IS, TLBI IPAS2E1ISNXS, TLB Invalidate by Intermediate
Physical Address, Stage 2, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.15
TLBI IPAS2E1OS, TLBI IPAS2E1OSNXS, TLB Invalidate by Intermediate
Physical Address, Stage 2, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.15
TLBI IPAS2E1OS, TLBI IPAS2E1OSNXS, TLB Invalidate by Intermediate
Physical Address, Stage 2, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.16
TLBI IPAS2LE1, TLBI IPAS2LE1NXS, TLB Invalidate by Intermediate
Physical Address, Stage 2, Last level, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.16
TLBI IPAS2LE1, TLBI IPAS2LE1NXS, TLB Invalidate by Intermediate
Physical Address, Stage 2, Last level, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.17
TLBI IPAS2LE1IS, TLBI IPAS2LE1ISNXS, TLB Invalidate by
Intermediate Physical Address, Stage 2, Last level, EL1, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.17
TLBI IPAS2LE1IS, TLBI IPAS2LE1ISNXS, TLB Invalidate by
Intermediate Physical Address, Stage 2, Last level, EL1, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.18
TLBI IPAS2LE1OS, TLBI IPAS2LE1OSNXS, TLB Invalidate by
Intermediate Physical Address, Stage 2, Last level, EL1, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.18
TLBI IPAS2LE1OS, TLBI IPAS2LE1OSNXS, TLB Invalidate by
Intermediate Physical Address, Stage 2, Last level, EL1, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.19
TLBI PAALL, TLB Invalidate GPT Information by PA, All Entries,
Local

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.19
TLBI PAALL, TLB Invalidate GPT Information by PA, All Entries,
Local

# topic.topics[].topics[].topics[].topics[].label
​C5.5.20
TLBI PAALLOS, TLB Invalidate GPT Information by PA, All Entries,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.20
TLBI PAALLOS, TLB Invalidate GPT Information by PA, All Entries,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.21
TLBI RIPAS2E1, TLBI RIPAS2E1NXS, TLB Range Invalidate by
Intermediate Physical Address, Stage 2, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.21
TLBI RIPAS2E1, TLBI RIPAS2E1NXS, TLB Range Invalidate by
Intermediate Physical Address, Stage 2, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.22
TLBI RIPAS2E1IS, TLBI RIPAS2E1ISNXS, TLB Range Invalidate by
Intermediate Physical Address, Stage 2, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.22
TLBI RIPAS2E1IS, TLBI RIPAS2E1ISNXS, TLB Range Invalidate by
Intermediate Physical Address, Stage 2, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.23
TLBI RIPAS2E1OS, TLBI RIPAS2E1OSNXS, TLB Range Invalidate by
Intermediate Physical Address, Stage 2, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.23
TLBI RIPAS2E1OS, TLBI RIPAS2E1OSNXS, TLB Range Invalidate by
Intermediate Physical Address, Stage 2, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.24
TLBI RIPAS2LE1, TLBI RIPAS2LE1NXS, TLB Range Invalidate by
Intermediate Physical Address, Stage 2, Last level, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.24
TLBI RIPAS2LE1, TLBI RIPAS2LE1NXS, TLB Range Invalidate by
Intermediate Physical Address, Stage 2, Last level, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.25 TLBI RIPAS2LE1IS, TLBI
RIPAS2LE1ISNXS, TLB Range Invalidate by Intermediate Physical Address,
Stage 2, Last level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.25 TLBI RIPAS2LE1IS, TLBI
RIPAS2LE1ISNXS, TLB Range Invalidate by Intermediate Physical Address,
Stage 2, Last level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.26 TLBI RIPAS2LE1OS, TLBI
RIPAS2LE1OSNXS, TLB Range Invalidate by Intermediate Physical Address,
Stage 2, Last level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.26 TLBI RIPAS2LE1OS, TLBI
RIPAS2LE1OSNXS, TLB Range Invalidate by Intermediate Physical Address,
Stage 2, Last level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.27
TLBI RPALOS, TLB Range Invalidate GPT Information by PA, Last
level, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.27
TLBI RPALOS, TLB Range Invalidate GPT Information by PA, Last
level, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.28
TLBI RPAOS, TLB Range Invalidate GPT Information by PA, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.28
TLBI RPAOS, TLB Range Invalidate GPT Information by PA, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.29
TLBI RVAAE1, TLBI RVAAE1NXS, TLB Range Invalidate by VA, All
ASID, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.29
TLBI RVAAE1, TLBI RVAAE1NXS, TLB Range Invalidate by VA, All
ASID, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.30
TLBI RVAAE1IS, TLBI RVAAE1ISNXS, TLB Range Invalidate by VA, All
ASID, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.30
TLBI RVAAE1IS, TLBI RVAAE1ISNXS, TLB Range Invalidate by VA, All
ASID, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.31
TLBI RVAAE1OS, TLBI RVAAE1OSNXS, TLB Range Invalidate by VA, All
ASID, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.31
TLBI RVAAE1OS, TLBI RVAAE1OSNXS, TLB Range Invalidate by VA, All
ASID, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.32
TLBI RVAALE1, TLBI RVAALE1NXS, TLB Range Invalidate by VA, All
ASID, Last level, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.32
TLBI RVAALE1, TLBI RVAALE1NXS, TLB Range Invalidate by VA, All
ASID, Last level, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.33
TLBI RVAALE1IS, TLBI RVAALE1ISNXS, TLB Range Invalidate by VA,
All ASID, Last Level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.33
TLBI RVAALE1IS, TLBI RVAALE1ISNXS, TLB Range Invalidate by VA,
All ASID, Last Level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.34
TLBI RVAALE1OS, TLBI RVAALE1OSNXS, TLB Range Invalidate by VA,
All ASID, Last Level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.34
TLBI RVAALE1OS, TLBI RVAALE1OSNXS, TLB Range Invalidate by VA,
All ASID, Last Level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.35
TLBI RVAE1, TLBI RVAE1NXS, TLB Range Invalidate by VA,
EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.35
TLBI RVAE1, TLBI RVAE1NXS, TLB Range Invalidate by VA,
EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.36
TLBI RVAE1IS, TLBI RVAE1ISNXS, TLB Range Invalidate by VA, EL1,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.36
TLBI RVAE1IS, TLBI RVAE1ISNXS, TLB Range Invalidate by VA, EL1,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.37
TLBI RVAE1OS, TLBI RVAE1OSNXS, TLB Range Invalidate by VA, EL1,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.37
TLBI RVAE1OS, TLBI RVAE1OSNXS, TLB Range Invalidate by VA, EL1,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.38
TLBI RVAE2, TLBI RVAE2NXS, TLB Range Invalidate by VA,
EL2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.38
TLBI RVAE2, TLBI RVAE2NXS, TLB Range Invalidate by VA,
EL2

# topic.topics[].topics[].topics[].topics[].label
​C5.5.39
TLBI RVAE2IS, TLBI RVAE2ISNXS, TLB Range Invalidate by VA, EL2,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.39
TLBI RVAE2IS, TLBI RVAE2ISNXS, TLB Range Invalidate by VA, EL2,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.40
TLBI RVAE2OS, TLBI RVAE2OSNXS, TLB Range Invalidate by VA, EL2,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.40
TLBI RVAE2OS, TLBI RVAE2OSNXS, TLB Range Invalidate by VA, EL2,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.41
TLBI RVAE3, TLBI RVAE3NXS, TLB Range Invalidate by VA,
EL3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.41
TLBI RVAE3, TLBI RVAE3NXS, TLB Range Invalidate by VA,
EL3

# topic.topics[].topics[].topics[].topics[].label
​C5.5.42
TLBI RVAE3IS, TLBI RVAE3ISNXS, TLB Range Invalidate by VA, EL3,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.42
TLBI RVAE3IS, TLBI RVAE3ISNXS, TLB Range Invalidate by VA, EL3,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.43
TLBI RVAE3OS, TLBI RVAE3OSNXS, TLB Range Invalidate by VA, EL3,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.43
TLBI RVAE3OS, TLBI RVAE3OSNXS, TLB Range Invalidate by VA, EL3,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.44
TLBI RVALE1, TLBI RVALE1NXS, TLB Range Invalidate by VA, Last
level, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.44
TLBI RVALE1, TLBI RVALE1NXS, TLB Range Invalidate by VA, Last
level, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.45
TLBI RVALE1IS, TLBI RVALE1ISNXS, TLB Range Invalidate by VA, Last
level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.45
TLBI RVALE1IS, TLBI RVALE1ISNXS, TLB Range Invalidate by VA, Last
level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.46
TLBI RVALE1OS, TLBI RVALE1OSNXS, TLB Range Invalidate by VA, Last
level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.46
TLBI RVALE1OS, TLBI RVALE1OSNXS, TLB Range Invalidate by VA, Last
level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.47
TLBI RVALE2, TLBI RVALE2NXS, TLB Range Invalidate by VA, Last
level, EL2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.47
TLBI RVALE2, TLBI RVALE2NXS, TLB Range Invalidate by VA, Last
level, EL2

# topic.topics[].topics[].topics[].topics[].label
​C5.5.48
TLBI RVALE2IS, TLBI RVALE2ISNXS, TLB Range Invalidate by VA, Last
level, EL2, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.48
TLBI RVALE2IS, TLBI RVALE2ISNXS, TLB Range Invalidate by VA, Last
level, EL2, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.49
TLBI RVALE2OS, TLBI RVALE2OSNXS, TLB Range Invalidate by VA, Last
level, EL2, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.49
TLBI RVALE2OS, TLBI RVALE2OSNXS, TLB Range Invalidate by VA, Last
level, EL2, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.50
TLBI RVALE3, TLBI RVALE3NXS, TLB Range Invalidate by VA, Last
level, EL3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.50
TLBI RVALE3, TLBI RVALE3NXS, TLB Range Invalidate by VA, Last
level, EL3

# topic.topics[].topics[].topics[].topics[].label
​C5.5.51
TLBI RVALE3IS, TLBI RVALE3ISNXS, TLB Range Invalidate by VA, Last
level, EL3, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.51
TLBI RVALE3IS, TLBI RVALE3ISNXS, TLB Range Invalidate by VA, Last
level, EL3, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.52
TLBI RVALE3OS, TLBI RVALE3OSNXS, TLB Range Invalidate by VA, Last
level, EL3, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.52
TLBI RVALE3OS, TLBI RVALE3OSNXS, TLB Range Invalidate by VA, Last
level, EL3, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.53
TLBI VAAE1, TLBI VAAE1NXS, TLB Invalidate by VA, All ASID,
EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.53
TLBI VAAE1, TLBI VAAE1NXS, TLB Invalidate by VA, All ASID,
EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.54
TLBI VAAE1IS, TLBI VAAE1ISNXS, TLB Invalidate by VA, All ASID,
EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.54
TLBI VAAE1IS, TLBI VAAE1ISNXS, TLB Invalidate by VA, All ASID,
EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.55
TLBI VAAE1OS, TLBI VAAE1OSNXS, TLB Invalidate by VA, All ASID,
EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.55
TLBI VAAE1OS, TLBI VAAE1OSNXS, TLB Invalidate by VA, All ASID,
EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.56
TLBI VAALE1, TLBI VAALE1NXS, TLB Invalidate by VA, All ASID, Last
level, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.56
TLBI VAALE1, TLBI VAALE1NXS, TLB Invalidate by VA, All ASID, Last
level, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.57
TLBI VAALE1IS, TLBI VAALE1ISNXS, TLB Invalidate by VA, All ASID,
Last Level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.57
TLBI VAALE1IS, TLBI VAALE1ISNXS, TLB Invalidate by VA, All ASID,
Last Level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.58
TLBI VAALE1OS, TLBI VAALE1OSNXS, TLB Invalidate by VA, All ASID,
Last Level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.58
TLBI VAALE1OS, TLBI VAALE1OSNXS, TLB Invalidate by VA, All ASID,
Last Level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.59
TLBI VAE1, TLBI VAE1NXS, TLB Invalidate by VA, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.59
TLBI VAE1, TLBI VAE1NXS, TLB Invalidate by VA, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.60
TLBI VAE1IS, TLBI VAE1ISNXS, TLB Invalidate by VA, EL1, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.60
TLBI VAE1IS, TLBI VAE1ISNXS, TLB Invalidate by VA, EL1, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.61
TLBI VAE1OS, TLBI VAE1OSNXS, TLB Invalidate by VA, EL1, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.61
TLBI VAE1OS, TLBI VAE1OSNXS, TLB Invalidate by VA, EL1, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.62
TLBI VAE2, TLBI VAE2NXS, TLB Invalidate by VA, EL2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.62
TLBI VAE2, TLBI VAE2NXS, TLB Invalidate by VA, EL2

# topic.topics[].topics[].topics[].topics[].label
​C5.5.63
TLBI VAE2IS, TLBI VAE2ISNXS, TLB Invalidate by VA, EL2, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.63
TLBI VAE2IS, TLBI VAE2ISNXS, TLB Invalidate by VA, EL2, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.64
TLBI VAE2OS, TLBI VAE2OSNXS, TLB Invalidate by VA, EL2, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.64
TLBI VAE2OS, TLBI VAE2OSNXS, TLB Invalidate by VA, EL2, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.65
TLBI VAE3, TLBI VAE3NXS, TLB Invalidate by VA, EL3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.65
TLBI VAE3, TLBI VAE3NXS, TLB Invalidate by VA, EL3

# topic.topics[].topics[].topics[].topics[].label
​C5.5.66
TLBI VAE3IS, TLBI VAE3ISNXS, TLB Invalidate by VA, EL3, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.66
TLBI VAE3IS, TLBI VAE3ISNXS, TLB Invalidate by VA, EL3, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.67
TLBI VAE3OS, TLBI VAE3OSNXS, TLB Invalidate by VA, EL3, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.67
TLBI VAE3OS, TLBI VAE3OSNXS, TLB Invalidate by VA, EL3, Outer
Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.68
TLBI VALE1, TLBI VALE1NXS, TLB Invalidate by VA, Last level,
EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.68
TLBI VALE1, TLBI VALE1NXS, TLB Invalidate by VA, Last level,
EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.69
TLBI VALE1IS, TLBI VALE1ISNXS, TLB Invalidate by VA, Last level,
EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.69
TLBI VALE1IS, TLBI VALE1ISNXS, TLB Invalidate by VA, Last level,
EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.70
TLBI VALE1OS, TLBI VALE1OSNXS, TLB Invalidate by VA, Last level,
EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.70
TLBI VALE1OS, TLBI VALE1OSNXS, TLB Invalidate by VA, Last level,
EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.71
TLBI VALE2, TLBI VALE2NXS, TLB Invalidate by VA, Last level,
EL2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.71
TLBI VALE2, TLBI VALE2NXS, TLB Invalidate by VA, Last level,
EL2

# topic.topics[].topics[].topics[].topics[].label
​C5.5.72
TLBI VALE2IS, TLBI VALE2ISNXS, TLB Invalidate by VA, Last level,
EL2, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.72
TLBI VALE2IS, TLBI VALE2ISNXS, TLB Invalidate by VA, Last level,
EL2, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.73
TLBI VALE2OS, TLBI VALE2OSNXS, TLB Invalidate by VA, Last level,
EL2, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.73
TLBI VALE2OS, TLBI VALE2OSNXS, TLB Invalidate by VA, Last level,
EL2, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.74
TLBI VALE3, TLBI VALE3NXS, TLB Invalidate by VA, Last level,
EL3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.74
TLBI VALE3, TLBI VALE3NXS, TLB Invalidate by VA, Last level,
EL3

# topic.topics[].topics[].topics[].topics[].label
​C5.5.75
TLBI VALE3IS, TLBI VALE3ISNXS, TLB Invalidate by VA, Last level,
EL3, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.75
TLBI VALE3IS, TLBI VALE3ISNXS, TLB Invalidate by VA, Last level,
EL3, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.76
TLBI VALE3OS, TLBI VALE3OSNXS, TLB Invalidate by VA, Last level,
EL3, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.76
TLBI VALE3OS, TLBI VALE3OSNXS, TLB Invalidate by VA, Last level,
EL3, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.77
TLBI VMALLE1, TLBI VMALLE1NXS, TLB Invalidate by VMID, All at
stage 1, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.77
TLBI VMALLE1, TLBI VMALLE1NXS, TLB Invalidate by VMID, All at
stage 1, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.78
TLBI VMALLE1IS, TLBI VMALLE1ISNXS, TLB Invalidate by VMID, All at
stage 1, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.78
TLBI VMALLE1IS, TLBI VMALLE1ISNXS, TLB Invalidate by VMID, All at
stage 1, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.79
TLBI VMALLE1OS, TLBI VMALLE1OSNXS, TLB Invalidate by VMID, All at
stage 1, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.79
TLBI VMALLE1OS, TLBI VMALLE1OSNXS, TLB Invalidate by VMID, All at
stage 1, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.80
TLBI VMALLS12E1, TLBI VMALLS12E1NXS, TLB Invalidate by VMID, All
at Stage 1 and 2, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.80
TLBI VMALLS12E1, TLBI VMALLS12E1NXS, TLB Invalidate by VMID, All
at Stage 1 and 2, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.81 TLBI VMALLS12E1IS, TLBI
VMALLS12E1ISNXS, TLB Invalidate by VMID, All at Stage 1 and 2, EL1,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.81 TLBI VMALLS12E1IS, TLBI
VMALLS12E1ISNXS, TLB Invalidate by VMID, All at Stage 1 and 2, EL1,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.82 TLBI VMALLS12E1OS, TLBI
VMALLS12E1OSNXS, TLB Invalidate by VMID, All at Stage 1 and 2, EL1,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.82 TLBI VMALLS12E1OS, TLBI
VMALLS12E1OSNXS, TLB Invalidate by VMID, All at Stage 1 and 2, EL1,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.83
TLBI VMALLWS2E1, TLBI VMALLWS2E1NXS, TLB Invalidate stage 2 dirty
state by VMID, EL1&0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.83
TLBI VMALLWS2E1, TLBI VMALLWS2E1NXS, TLB Invalidate stage 2 dirty
state by VMID, EL1&0

# topic.topics[].topics[].topics[].topics[].label
​C5.5.84 TLBI VMALLWS2E1IS, TLBI
VMALLWS2E1ISNXS, TLB Invalidate stage 2 dirty state by VMID, EL1&0,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.84 TLBI VMALLWS2E1IS, TLBI
VMALLWS2E1ISNXS, TLB Invalidate stage 2 dirty state by VMID, EL1&0,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.85 TLBI VMALLWS2E1OS, TLBI
VMALLWS2E1OSNXS, TLB Invalidate stage 2 write permission by VMID,
EL1&0, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.85 TLBI VMALLWS2E1OS, TLBI
VMALLWS2E1OSNXS, TLB Invalidate stage 2 write permission by VMID,
EL1&0, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.86
TLBIP IPAS2E1, TLBIP IPAS2E1NXS, TLB Invalidate Pair by
Intermediate Physical Address, Stage 2, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.86
TLBIP IPAS2E1, TLBIP IPAS2E1NXS, TLB Invalidate Pair by
Intermediate Physical Address, Stage 2, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.87
TLBIP IPAS2E1IS, TLBIP IPAS2E1ISNXS, TLB Invalidate Pair by
Intermediate Physical Address, Stage 2, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.87
TLBIP IPAS2E1IS, TLBIP IPAS2E1ISNXS, TLB Invalidate Pair by
Intermediate Physical Address, Stage 2, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.88
TLBIP IPAS2E1OS, TLBIP IPAS2E1OSNXS, TLB Invalidate Pair by
Intermediate Physical Address, Stage 2, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.88
TLBIP IPAS2E1OS, TLBIP IPAS2E1OSNXS, TLB Invalidate Pair by
Intermediate Physical Address, Stage 2, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.89
TLBIP IPAS2LE1, TLBIP IPAS2LE1NXS, TLB Invalidate Pair by
Intermediate Physical Address, Stage 2, Last level, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.89
TLBIP IPAS2LE1, TLBIP IPAS2LE1NXS, TLB Invalidate Pair by
Intermediate Physical Address, Stage 2, Last level, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.90 TLBIP IPAS2LE1IS, TLBIP
IPAS2LE1ISNXS, TLB Invalidate Pair by Intermediate Physical Address,
Stage 2, Last level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.90 TLBIP IPAS2LE1IS, TLBIP
IPAS2LE1ISNXS, TLB Invalidate Pair by Intermediate Physical Address,
Stage 2, Last level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.91 TLBIP IPAS2LE1OS, TLBIP
IPAS2LE1OSNXS, TLB Invalidate Pair by Intermediate Physical Address,
Stage 2, Last level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.91 TLBIP IPAS2LE1OS, TLBIP
IPAS2LE1OSNXS, TLB Invalidate Pair by Intermediate Physical Address,
Stage 2, Last level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.92
TLBIP RIPAS2E1, TLBIP RIPAS2E1NXS, TLB Range Invalidate by
Intermediate Physical Address, Stage 2, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.92
TLBIP RIPAS2E1, TLBIP RIPAS2E1NXS, TLB Range Invalidate by
Intermediate Physical Address, Stage 2, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.93 TLBIP RIPAS2E1IS, TLBIP
RIPAS2E1ISNXS, TLB Range Invalidate by Intermediate Physical Address,
Stage 2, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.93 TLBIP RIPAS2E1IS, TLBIP
RIPAS2E1ISNXS, TLB Range Invalidate by Intermediate Physical Address,
Stage 2, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.94 TLBIP RIPAS2E1OS, TLBIP
RIPAS2E1OSNXS, TLB Range Invalidate by Intermediate Physical Address,
Stage 2, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.94 TLBIP RIPAS2E1OS, TLBIP
RIPAS2E1OSNXS, TLB Range Invalidate by Intermediate Physical Address,
Stage 2, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.95
TLBIP RIPAS2LE1, TLBIP RIPAS2LE1NXS, TLB Range Invalidate by
Intermediate Physical Address, Stage 2, Last level, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.95
TLBIP RIPAS2LE1, TLBIP RIPAS2LE1NXS, TLB Range Invalidate by
Intermediate Physical Address, Stage 2, Last level, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.96 TLBIP RIPAS2LE1IS, TLBIP
RIPAS2LE1ISNXS, TLB Range Invalidate by Intermediate Physical Address,
Stage 2, Last level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.96 TLBIP RIPAS2LE1IS, TLBIP
RIPAS2LE1ISNXS, TLB Range Invalidate by Intermediate Physical Address,
Stage 2, Last level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.97 TLBIP RIPAS2LE1OS, TLBIP
RIPAS2LE1OSNXS, TLB Range Invalidate by Intermediate Physical Address,
Stage 2, Last level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.97 TLBIP RIPAS2LE1OS, TLBIP
RIPAS2LE1OSNXS, TLB Range Invalidate by Intermediate Physical Address,
Stage 2, Last level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.98
TLBIP RVAAE1, TLBIP RVAAE1NXS, TLB Range Invalidate by VA, All
ASID, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.98
TLBIP RVAAE1, TLBIP RVAAE1NXS, TLB Range Invalidate by VA, All
ASID, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.99
TLBIP RVAAE1IS, TLBIP RVAAE1ISNXS, TLB Range Invalidate by VA,
All ASID, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.99
TLBIP RVAAE1IS, TLBIP RVAAE1ISNXS, TLB Range Invalidate by VA,
All ASID, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.100
TLBIP RVAAE1OS, TLBIP RVAAE1OSNXS, TLB Range Invalidate by VA,
All ASID, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.100
TLBIP RVAAE1OS, TLBIP RVAAE1OSNXS, TLB Range Invalidate by VA,
All ASID, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.101
TLBIP RVAALE1, TLBIP RVAALE1NXS, TLB Range Invalidate by VA, All
ASID, Last level, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.101
TLBIP RVAALE1, TLBIP RVAALE1NXS, TLB Range Invalidate by VA, All
ASID, Last level, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.102 TLBIP RVAALE1IS, TLBIP
RVAALE1ISNXS, TLB Range Invalidate by VA, All ASID, Last Level, EL1,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.102 TLBIP RVAALE1IS, TLBIP
RVAALE1ISNXS, TLB Range Invalidate by VA, All ASID, Last Level, EL1,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.103 TLBIP RVAALE1OS, TLBIP
RVAALE1OSNXS, TLB Range Invalidate by VA, All ASID, Last Level, EL1,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.103 TLBIP RVAALE1OS, TLBIP
RVAALE1OSNXS, TLB Range Invalidate by VA, All ASID, Last Level, EL1,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.104
TLBIP RVAE1, TLBIP RVAE1NXS, TLB Range Invalidate by VA,
EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.104
TLBIP RVAE1, TLBIP RVAE1NXS, TLB Range Invalidate by VA,
EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.105
TLBIP RVAE1IS, TLBIP RVAE1ISNXS, TLB Range Invalidate by VA, EL1,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.105
TLBIP RVAE1IS, TLBIP RVAE1ISNXS, TLB Range Invalidate by VA, EL1,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.106
TLBIP RVAE1OS, TLBIP RVAE1OSNXS, TLB Range Invalidate by VA, EL1,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.106
TLBIP RVAE1OS, TLBIP RVAE1OSNXS, TLB Range Invalidate by VA, EL1,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.107
TLBIP RVAE2, TLBIP RVAE2NXS, TLB Range Invalidate by VA,
EL2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.107
TLBIP RVAE2, TLBIP RVAE2NXS, TLB Range Invalidate by VA,
EL2

# topic.topics[].topics[].topics[].topics[].label
​C5.5.108
TLBIP RVAE2IS, TLBIP RVAE2ISNXS, TLB Range Invalidate by VA, EL2,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.108
TLBIP RVAE2IS, TLBIP RVAE2ISNXS, TLB Range Invalidate by VA, EL2,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.109
TLBIP RVAE2OS, TLBIP RVAE2OSNXS, TLB Range Invalidate by VA, EL2,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.109
TLBIP RVAE2OS, TLBIP RVAE2OSNXS, TLB Range Invalidate by VA, EL2,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.110
TLBIP RVAE3, TLBIP RVAE3NXS, TLB Range Invalidate by VA,
EL3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.110
TLBIP RVAE3, TLBIP RVAE3NXS, TLB Range Invalidate by VA,
EL3

# topic.topics[].topics[].topics[].topics[].label
​C5.5.111
TLBIP RVAE3IS, TLBIP RVAE3ISNXS, TLB Range Invalidate by VA, EL3,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.111
TLBIP RVAE3IS, TLBIP RVAE3ISNXS, TLB Range Invalidate by VA, EL3,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.112
TLBIP RVAE3OS, TLBIP RVAE3OSNXS, TLB Range Invalidate by VA, EL3,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.112
TLBIP RVAE3OS, TLBIP RVAE3OSNXS, TLB Range Invalidate by VA, EL3,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.113
TLBIP RVALE1, TLBIP RVALE1NXS, TLB Range Invalidate by VA, Last
level, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.113
TLBIP RVALE1, TLBIP RVALE1NXS, TLB Range Invalidate by VA, Last
level, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.114
TLBIP RVALE1IS, TLBIP RVALE1ISNXS, TLB Range Invalidate by VA,
Last level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.114
TLBIP RVALE1IS, TLBIP RVALE1ISNXS, TLB Range Invalidate by VA,
Last level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.115
TLBIP RVALE1OS, TLBIP RVALE1OSNXS, TLB Range Invalidate by VA,
Last level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.115
TLBIP RVALE1OS, TLBIP RVALE1OSNXS, TLB Range Invalidate by VA,
Last level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.116
TLBIP RVALE2, TLBIP RVALE2NXS, TLB Range Invalidate by VA, Last
level, EL2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.116
TLBIP RVALE2, TLBIP RVALE2NXS, TLB Range Invalidate by VA, Last
level, EL2

# topic.topics[].topics[].topics[].topics[].label
​C5.5.117
TLBIP RVALE2IS, TLBIP RVALE2ISNXS, TLB Range Invalidate by VA,
Last level, EL2, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.117
TLBIP RVALE2IS, TLBIP RVALE2ISNXS, TLB Range Invalidate by VA,
Last level, EL2, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.118
TLBIP RVALE2OS, TLBIP RVALE2OSNXS, TLB Range Invalidate by VA,
Last level, EL2, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.118
TLBIP RVALE2OS, TLBIP RVALE2OSNXS, TLB Range Invalidate by VA,
Last level, EL2, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.119
TLBIP RVALE3, TLBIP RVALE3NXS, TLB Range Invalidate by VA, Last
level, EL3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.119
TLBIP RVALE3, TLBIP RVALE3NXS, TLB Range Invalidate by VA, Last
level, EL3

# topic.topics[].topics[].topics[].topics[].label
​C5.5.120
TLBIP RVALE3IS, TLBIP RVALE3ISNXS, TLB Range Invalidate by VA,
Last level, EL3, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.120
TLBIP RVALE3IS, TLBIP RVALE3ISNXS, TLB Range Invalidate by VA,
Last level, EL3, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.121
TLBIP RVALE3OS, TLBIP RVALE3OSNXS, TLB Range Invalidate by VA,
Last level, EL3, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.121
TLBIP RVALE3OS, TLBIP RVALE3OSNXS, TLB Range Invalidate by VA,
Last level, EL3, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.122
TLBIP VAAE1, TLBIP VAAE1NXS, TLB Invalidate Pair by VA, All ASID,
EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.122
TLBIP VAAE1, TLBIP VAAE1NXS, TLB Invalidate Pair by VA, All ASID,
EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.123
TLBIP VAAE1IS, TLBIP VAAE1ISNXS, TLB Invalidate Pair by VA, All
ASID, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.123
TLBIP VAAE1IS, TLBIP VAAE1ISNXS, TLB Invalidate Pair by VA, All
ASID, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.124
TLBIP VAAE1OS, TLBIP VAAE1OSNXS, TLB Invalidate Pair by VA, All
ASID, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.124
TLBIP VAAE1OS, TLBIP VAAE1OSNXS, TLB Invalidate Pair by VA, All
ASID, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.125
TLBIP VAALE1, TLBIP VAALE1NXS, TLB Invalidate Pair by VA, All
ASID, Last level, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.125
TLBIP VAALE1, TLBIP VAALE1NXS, TLB Invalidate Pair by VA, All
ASID, Last level, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.126
TLBIP VAALE1IS, TLBIP VAALE1ISNXS, TLB Invalidate Pair by VA, All
ASID, Last Level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.126
TLBIP VAALE1IS, TLBIP VAALE1ISNXS, TLB Invalidate Pair by VA, All
ASID, Last Level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.127
TLBIP VAALE1OS, TLBIP VAALE1OSNXS, TLB Invalidate Pair by VA, All
ASID, Last Level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.127
TLBIP VAALE1OS, TLBIP VAALE1OSNXS, TLB Invalidate Pair by VA, All
ASID, Last Level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.128
TLBIP VAE1, TLBIP VAE1NXS, TLB Invalidate Pair by VA,
EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.128
TLBIP VAE1, TLBIP VAE1NXS, TLB Invalidate Pair by VA,
EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.129
TLBIP VAE1IS, TLBIP VAE1ISNXS, TLB Invalidate Pair by VA, EL1,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.129
TLBIP VAE1IS, TLBIP VAE1ISNXS, TLB Invalidate Pair by VA, EL1,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.130
TLBIP VAE1OS, TLBIP VAE1OSNXS, TLB Invalidate Pair by VA, EL1,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.130
TLBIP VAE1OS, TLBIP VAE1OSNXS, TLB Invalidate Pair by VA, EL1,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.131
TLBIP VAE2, TLBIP VAE2NXS, TLB Invalidate Pair by VA,
EL2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.131
TLBIP VAE2, TLBIP VAE2NXS, TLB Invalidate Pair by VA,
EL2

# topic.topics[].topics[].topics[].topics[].label
​C5.5.132
TLBIP VAE2IS, TLBIP VAE2ISNXS, TLB Invalidate Pair by VA, EL2,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.132
TLBIP VAE2IS, TLBIP VAE2ISNXS, TLB Invalidate Pair by VA, EL2,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.133
TLBIP VAE2OS, TLBIP VAE2OSNXS, TLB Invalidate Pair by VA, EL2,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.133
TLBIP VAE2OS, TLBIP VAE2OSNXS, TLB Invalidate Pair by VA, EL2,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.134
TLBIP VAE3, TLBIP VAE3NXS, TLB Invalidate Pair by VA,
EL3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.134
TLBIP VAE3, TLBIP VAE3NXS, TLB Invalidate Pair by VA,
EL3

# topic.topics[].topics[].topics[].topics[].label
​C5.5.135
TLBIP VAE3IS, TLBIP VAE3ISNXS, TLB Invalidate Pair by VA, EL3,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.135
TLBIP VAE3IS, TLBIP VAE3ISNXS, TLB Invalidate Pair by VA, EL3,
Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.136
TLBIP VAE3OS, TLBIP VAE3OSNXS, TLB Invalidate Pair by VA, EL3,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.136
TLBIP VAE3OS, TLBIP VAE3OSNXS, TLB Invalidate Pair by VA, EL3,
Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.137
TLBIP VALE1, TLBIP VALE1NXS, TLB Invalidate Pair by VA, Last
level, EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.137
TLBIP VALE1, TLBIP VALE1NXS, TLB Invalidate Pair by VA, Last
level, EL1

# topic.topics[].topics[].topics[].topics[].label
​C5.5.138
TLBIP VALE1IS, TLBIP VALE1ISNXS, TLB Invalidate Pair by VA, Last
level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.138
TLBIP VALE1IS, TLBIP VALE1ISNXS, TLB Invalidate Pair by VA, Last
level, EL1, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.139
TLBIP VALE1OS, TLBIP VALE1OSNXS, TLB Invalidate Pair by VA, Last
level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.139
TLBIP VALE1OS, TLBIP VALE1OSNXS, TLB Invalidate Pair by VA, Last
level, EL1, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.140
TLBIP VALE2, TLBIP VALE2NXS, TLB Invalidate Pair by VA, Last
level, EL2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.140
TLBIP VALE2, TLBIP VALE2NXS, TLB Invalidate Pair by VA, Last
level, EL2

# topic.topics[].topics[].topics[].topics[].label
​C5.5.141
TLBIP VALE2IS, TLBIP VALE2ISNXS, TLB Invalidate Pair by VA, Last
level, EL2, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.141
TLBIP VALE2IS, TLBIP VALE2ISNXS, TLB Invalidate Pair by VA, Last
level, EL2, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.142
TLBIP VALE2OS, TLBIP VALE2OSNXS, TLB Invalidate Pair by VA, Last
level, EL2, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.142
TLBIP VALE2OS, TLBIP VALE2OSNXS, TLB Invalidate Pair by VA, Last
level, EL2, Outer Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.143
TLBIP VALE3, TLBIP VALE3NXS, TLB Invalidate Pair by VA, Last
level, EL3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.143
TLBIP VALE3, TLBIP VALE3NXS, TLB Invalidate Pair by VA, Last
level, EL3

# topic.topics[].topics[].topics[].topics[].label
​C5.5.144
TLBIP VALE3IS, TLBIP VALE3ISNXS, TLB Invalidate Pair by VA, Last
level, EL3, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.144
TLBIP VALE3IS, TLBIP VALE3ISNXS, TLB Invalidate Pair by VA, Last
level, EL3, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​C5.5.145
TLBIP VALE3OS, TLBIP VALE3OSNXS, TLB Invalidate Pair by VA, Last
level, EL3, Outer Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.5.145
TLBIP VALE3OS, TLBIP VALE3OSNXS, TLB Invalidate Pair by VA, Last
level, EL3, Outer Shareable

# topic.topics[].topics[].topics[].anchors[].title
​C5.5 A64 System instructions for TLB
maintenance

# topic.topics[].topics[].topics[].label
​C5.6 A64 System instructions for prediction
restriction

# topic.topics[].topics[].topics[].topics[].label
​C5.6.1
CFP RCTX, Control Flow Prediction Restriction by Context

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.6.1
CFP RCTX, Control Flow Prediction Restriction by Context

# topic.topics[].topics[].topics[].topics[].label
​C5.6.2
COSP RCTX, Clear Other Speculative Prediction Restriction by
Context

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.6.2
COSP RCTX, Clear Other Speculative Prediction Restriction by
Context

# topic.topics[].topics[].topics[].topics[].label
​C5.6.3
CPP RCTX, Cache Prefetch Prediction Restriction by
Context

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.6.3
CPP RCTX, Cache Prefetch Prediction Restriction by
Context

# topic.topics[].topics[].topics[].topics[].label
​C5.6.4
DVP RCTX, Data Value Prediction Restriction by Context

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.6.4
DVP RCTX, Data Value Prediction Restriction by Context

# topic.topics[].topics[].topics[].anchors[].title
​C5.6 A64 System instructions for prediction
restriction

# topic.topics[].topics[].topics[].label
​C5.7 A64 System instructions for the Branch
Record Buffer Extension

# topic.topics[].topics[].topics[].topics[].label
​C5.7.1
BRB IALL, Invalidate the Branch Record Buffer

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.7.1
BRB IALL, Invalidate the Branch Record Buffer

# topic.topics[].topics[].topics[].topics[].label
​C5.7.2
BRB INJ, Branch Record Injection into the Branch Record
Buffer

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.7.2
BRB INJ, Branch Record Injection into the Branch Record
Buffer

# topic.topics[].topics[].topics[].anchors[].title
​C5.7 A64 System instructions for the Branch
Record Buffer Extension

# topic.topics[].topics[].topics[].label
​C5.8 A64 System instructions for the Trace
Extension

# topic.topics[].topics[].topics[].anchors[].title
​C5.8 A64 System instructions for the Trace
Extension

# topic.topics[].topics[].topics[].label
​C5.9
A64 System instructions for the Guarded Control Stack

# topic.topics[].topics[].topics[].topics[].label
​C5.9.1
GCSPOPCX, Guarded Control Stack Pop and Compare exception return
record

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.9.1
GCSPOPCX, Guarded Control Stack Pop and Compare exception return
record

# topic.topics[].topics[].topics[].topics[].label
​C5.9.2
GCSPOPM, Guarded Control Stack Pop

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.9.2
GCSPOPM, Guarded Control Stack Pop

# topic.topics[].topics[].topics[].topics[].label
​C5.9.3
GCSPOPX, Guarded Control Stack Pop exception return
record

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.9.3
GCSPOPX, Guarded Control Stack Pop exception return
record

# topic.topics[].topics[].topics[].topics[].label
​C5.9.4
GCSPUSHM, Guarded Control Stack Push

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.9.4
GCSPUSHM, Guarded Control Stack Push

# topic.topics[].topics[].topics[].topics[].label
​C5.9.5
GCSPUSHX, Guarded Control Stack Push exception return
record

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.9.5
GCSPUSHX, Guarded Control Stack Push exception return
record

# topic.topics[].topics[].topics[].topics[].label
​C5.9.6
GCSSS1, Guarded Control Stack Switch Stack 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.9.6
GCSSS1, Guarded Control Stack Switch Stack 1

# topic.topics[].topics[].topics[].topics[].label
​C5.9.7
GCSSS2, Guarded Control Stack Switch Stack 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.9.7
GCSSS2, Guarded Control Stack Switch Stack 2

# topic.topics[].topics[].topics[].anchors[].title
​C5.9
A64 System instructions for the Guarded Control Stack

# topic.topics[].topics[].topics[].label
​C5.10
A64 IMPLEMENTATION DEFINED System instructions

# topic.topics[].topics[].topics[].topics[].label
​C5.10.1 SYS|SYSL|SYSP
S1_<op1>_<Cn>_<Cm>_<op2>, IMPLEMENTATION DEFINED
System instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C5.10.1 SYS|SYSL|SYSP
S1_<op1>_<Cn>_<Cm>_<op2>, IMPLEMENTATION DEFINED
System instructions

# topic.topics[].topics[].topics[].anchors[].title
​C5.10
A64 IMPLEMENTATION DEFINED System instructions

# topic.topics[].topics[].anchors[].title
​Chapter C5 The A64 System Instruction
Class

# topic.topics[].topics[].label
​Chapter C6 A64 Base Instruction
Descriptions

# topic.topics[].topics[].topics[].topics[].label
​C6.1.4 Condition flags and related
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.1.4 Condition flags and related
instructions

# topic.topics[].topics[].topics[].label
​C6.2 Alphabetical list of A64 base
instructions

# topic.topics[].topics[].topics[].topics[].label
​C6.2.25 AUTIA, AUTIA1716, AUTIASP, AUTIAZ,
AUTIZA

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.25 AUTIA, AUTIA1716, AUTIASP, AUTIAZ,
AUTIZA

# topic.topics[].topics[].topics[].topics[].label
​C6.2.29 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ,
AUTIZB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.29 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ,
AUTIZB

# topic.topics[].topics[].topics[].topics[].label
​C6.2.179 LDADD, LDADDA, LDADDAL,
LDADDL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.179 LDADD, LDADDA, LDADDAL,
LDADDL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.180 LDADDB, LDADDAB, LDADDALB,
LDADDLB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.180 LDADDB, LDADDAB, LDADDALB,
LDADDLB

# topic.topics[].topics[].topics[].topics[].label
​C6.2.181 LDADDH, LDADDAH, LDADDALH,
LDADDLH

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.181 LDADDH, LDADDAH, LDADDALH,
LDADDLH

# topic.topics[].topics[].topics[].topics[].label
​C6.2.199 LDCLR, LDCLRA, LDCLRAL,
LDCLRL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.199 LDCLR, LDCLRA, LDCLRAL,
LDCLRL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.200 LDCLRB, LDCLRAB, LDCLRALB,
LDCLRLB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.200 LDCLRB, LDCLRAB, LDCLRALB,
LDCLRLB

# topic.topics[].topics[].topics[].topics[].label
​C6.2.201 LDCLRH, LDCLRAH, LDCLRALH,
LDCLRLH

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.201 LDCLRH, LDCLRAH, LDCLRALH,
LDCLRLH

# topic.topics[].topics[].topics[].topics[].label
​C6.2.202 LDCLRP, LDCLRPA, LDCLRPAL,
LDCLRPL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.202 LDCLRP, LDCLRPA, LDCLRPAL,
LDCLRPL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.203 LDEOR, LDEORA, LDEORAL,
LDEORL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.203 LDEOR, LDEORA, LDEORAL,
LDEORL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.204 LDEORB, LDEORAB, LDEORALB,
LDEORLB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.204 LDEORB, LDEORAB, LDEORALB,
LDEORLB

# topic.topics[].topics[].topics[].topics[].label
​C6.2.205 LDEORH, LDEORAH, LDEORALH,
LDEORLH

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.205 LDEORH, LDEORAH, LDEORALH,
LDEORLH

# topic.topics[].topics[].topics[].topics[].label
​C6.2.230 LDSET, LDSETA, LDSETAL,
LDSETL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.230 LDSET, LDSETA, LDSETAL,
LDSETL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.231 LDSETB, LDSETAB, LDSETALB,
LDSETLB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.231 LDSETB, LDSETAB, LDSETALB,
LDSETLB

# topic.topics[].topics[].topics[].topics[].label
​C6.2.232 LDSETH, LDSETAH, LDSETALH,
LDSETLH

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.232 LDSETH, LDSETAH, LDSETALH,
LDSETLH

# topic.topics[].topics[].topics[].topics[].label
​C6.2.233 LDSETP, LDSETPA, LDSETPAL,
LDSETPL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.233 LDSETP, LDSETPA, LDSETPAL,
LDSETPL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.234 LDSMAX, LDSMAXA, LDSMAXAL,
LDSMAXL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.234 LDSMAX, LDSMAXA, LDSMAXAL,
LDSMAXL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.235
LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.235
LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB

# topic.topics[].topics[].topics[].topics[].label
​C6.2.236
LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.236
LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH

# topic.topics[].topics[].topics[].topics[].label
​C6.2.237 LDSMIN, LDSMINA, LDSMINAL,
LDSMINL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.237 LDSMIN, LDSMINA, LDSMINAL,
LDSMINL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.238
LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.238
LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB

# topic.topics[].topics[].topics[].topics[].label
​C6.2.239
LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.239
LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH

# topic.topics[].topics[].topics[].topics[].label
​C6.2.240 LDTADD, LDTADDA, LDTADDAL,
LDTADDL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.240 LDTADD, LDTADDA, LDTADDAL,
LDTADDL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.241 LDTCLR, LDTCLRA, LDTCLRAL,
LDTCLRL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.241 LDTCLR, LDTCLRA, LDTCLRAL,
LDTCLRL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.250 LDTSET, LDTSETA, LDTSETAL,
LDTSETL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.250 LDTSET, LDTSETA, LDTSETAL,
LDTSETL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.252 LDUMAX, LDUMAXA, LDUMAXAL,
LDUMAXL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.252 LDUMAX, LDUMAXA, LDUMAXAL,
LDUMAXL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.253
LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.253
LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB

# topic.topics[].topics[].topics[].topics[].label
​C6.2.254
LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.254
LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH

# topic.topics[].topics[].topics[].topics[].label
​C6.2.255 LDUMIN, LDUMINA, LDUMINAL,
LDUMINL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.255 LDUMIN, LDUMINA, LDUMINAL,
LDUMINL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.256
LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.256
LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB

# topic.topics[].topics[].topics[].topics[].label
​C6.2.257
LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.257
LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH

# topic.topics[].topics[].topics[].topics[].label
​C6.2.305 PACIA, PACIA1716, PACIASP, PACIAZ,
PACIZA

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.305 PACIA, PACIA1716, PACIASP, PACIAZ,
PACIZA

# topic.topics[].topics[].topics[].topics[].label
​C6.2.308 PACIB, PACIB1716, PACIBSP, PACIBZ,
PACIZB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.308 PACIB, PACIB1716, PACIBSP, PACIBZ,
PACIZB

# topic.topics[].topics[].topics[].topics[].label
​C6.2.321 RCWCAS, RCWCASA, RCWCASAL,
RCWCASL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.321 RCWCAS, RCWCASA, RCWCASAL,
RCWCASL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.322
RCWCASP, RCWCASPA, RCWCASPAL, RCWCASPL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.322
RCWCASP, RCWCASPA, RCWCASPAL, RCWCASPL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.323 RCWCLR, RCWCLRA, RCWCLRAL,
RCWCLRL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.323 RCWCLR, RCWCLRA, RCWCLRAL,
RCWCLRL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.324
RCWCLRP, RCWCLRPA, RCWCLRPAL, RCWCLRPL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.324
RCWCLRP, RCWCLRPA, RCWCLRPAL, RCWCLRPL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.325
RCWSCAS, RCWSCASA, RCWSCASAL, RCWSCASL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.325
RCWSCAS, RCWSCASA, RCWSCASAL, RCWSCASL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.327
RCWSCLR, RCWSCLRA, RCWSCLRAL, RCWSCLRL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.327
RCWSCLR, RCWSCLRA, RCWSCLRAL, RCWSCLRL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.329 RCWSET, RCWSETA, RCWSETAL,
RCWSETL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.329 RCWSET, RCWSETA, RCWSETAL,
RCWSETL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.330
RCWSETP, RCWSETPA, RCWSETPAL, RCWSETPL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.330
RCWSETP, RCWSETPA, RCWSETPAL, RCWSETPL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.331
RCWSSET, RCWSSETA, RCWSSETAL, RCWSSETL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.331
RCWSSET, RCWSSETA, RCWSSETAL, RCWSSETL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.333
RCWSSWP, RCWSSWPA, RCWSSWPAL, RCWSSWPL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.333
RCWSSWP, RCWSSWPA, RCWSSWPAL, RCWSSWPL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.335 RCWSWP, RCWSWPA, RCWSWPAL,
RCWSWPL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.335 RCWSWP, RCWSWPA, RCWSWPAL,
RCWSWPL

# topic.topics[].topics[].topics[].topics[].label
​C6.2.336
RCWSWPP, RCWSWPPA, RCWSWPPAL, RCWSWPPL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C6.2.336
RCWSWPP, RCWSWPPA, RCWSWPPAL, RCWSWPPL

# topic.topics[].topics[].topics[].anchors[].title
​C6.2 Alphabetical list of A64 base
instructions

# topic.topics[].topics[].anchors[].title
​Chapter C6 A64 Base Instruction
Descriptions

# topic.topics[].topics[].label
​Chapter C7 A64 Advanced SIMD and
Floating-point Instruction Descriptions

# topic.topics[].topics[].topics[].label
​C7.1
About the A64 Advanced SIMD and floating-point instructions

# topic.topics[].topics[].topics[].topics[].label
​C7.1.4 Condition flags and related
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.1.4 Condition flags and related
instructions

# topic.topics[].topics[].topics[].anchors[].title
​C7.1
About the A64 Advanced SIMD and floating-point instructions

# topic.topics[].topics[].topics[].label
​C7.2 Alphabetical list of A64 Advanced SIMD
and floating-point instructions

# topic.topics[].topics[].topics[].topics[].label
​C7.2.13
BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.13
BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2

# topic.topics[].topics[].topics[].topics[].label
​C7.2.87
FCVTN, FCVTN2 (double to single-precision, single to
half-precision)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.87
FCVTN, FCVTN2 (double to single-precision, single to
half-precision)

# topic.topics[].topics[].topics[].topics[].label
​C7.2.88
FCVTN (half-precision to 8-bit floating-point)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.88
FCVTN (half-precision to 8-bit floating-point)

# topic.topics[].topics[].topics[].topics[].label
​C7.2.89
FCVTN, FCVTN2 (single-precision to 8-bit floating-point)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.89
FCVTN, FCVTN2 (single-precision to 8-bit floating-point)

# topic.topics[].topics[].topics[].topics[].label
​C7.2.115
FDOT (8-bit floating-point to half-precision, by
element)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.115
FDOT (8-bit floating-point to half-precision, by
element)

# topic.topics[].topics[].topics[].topics[].label
​C7.2.116
FDOT (8-bit floating-point to half-precision, vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.116
FDOT (8-bit floating-point to half-precision, vector)

# topic.topics[].topics[].topics[].topics[].label
​C7.2.117
FDOT (8-bit floating-point to single-precision, by
element)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.117
FDOT (8-bit floating-point to single-precision, by
element)

# topic.topics[].topics[].topics[].topics[].label
​C7.2.118
FDOT (8-bit floating-point to single-precision, vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.118
FDOT (8-bit floating-point to single-precision, vector)

# topic.topics[].topics[].topics[].topics[].label
​C7.2.147
FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.147
FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element)

# topic.topics[].topics[].topics[].topics[].label
​C7.2.148
FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.148
FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector)

# topic.topics[].topics[].topics[].topics[].label
​C7.2.153
FMMLA (widening, 8-bit floating-point to half-precision)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.153
FMMLA (widening, 8-bit floating-point to half-precision)

# topic.topics[].topics[].topics[].topics[].label
​C7.2.154
FMMLA (widening, 8-bit floating-point to
single-precision)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.154
FMMLA (widening, 8-bit floating-point to
single-precision)

# topic.topics[].topics[].topics[].topics[].label
​C7.2.218
LDBFADD, LDBFADDA, LDBFADDAL, LDBFADDL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.218
LDBFADD, LDBFADDA, LDBFADDAL, LDBFADDL

# topic.topics[].topics[].topics[].topics[].label
​C7.2.219
LDBFMAX, LDBFMAXA, LDBFMAXAL, LDBFMAXL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.219
LDBFMAX, LDBFMAXA, LDBFMAXAL, LDBFMAXL

# topic.topics[].topics[].topics[].topics[].label
​C7.2.221
LDBFMIN, LDBFMINA, LDBFMINAL, LDBFMINL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.221
LDBFMIN, LDBFMINA, LDBFMINAL, LDBFMINL

# topic.topics[].topics[].topics[].topics[].label
​C7.2.223 LDFADD, LDFADDA, LDFADDAL,
LDFADDL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.223 LDFADD, LDFADDA, LDFADDAL,
LDFADDL

# topic.topics[].topics[].topics[].topics[].label
​C7.2.224 LDFMAX, LDFMAXA, LDFMAXAL,
LDFMAXL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.224 LDFMAX, LDFMAXA, LDFMAXAL,
LDFMAXL

# topic.topics[].topics[].topics[].topics[].label
​C7.2.226 LDFMIN, LDFMINA, LDFMINAL,
LDFMINL

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.226 LDFMIN, LDFMINA, LDFMINAL,
LDFMINL

# topic.topics[].topics[].topics[].topics[].label
​C7.2.328
SQDMLAL, SQDMLAL2 (by element)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.328
SQDMLAL, SQDMLAL2 (by element)

# topic.topics[].topics[].topics[].topics[].label
​C7.2.330
SQDMLSL, SQDMLSL2 (by element)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.330
SQDMLSL, SQDMLSL2 (by element)

# topic.topics[].topics[].topics[].topics[].label
​C7.2.334
SQDMULL, SQDMULL2 (by element)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C7.2.334
SQDMULL, SQDMULL2 (by element)

# topic.topics[].topics[].topics[].anchors[].title
​C7.2 Alphabetical list of A64 Advanced SIMD
and floating-point instructions

# topic.topics[].topics[].anchors[].title
​Chapter C7 A64 Advanced SIMD and
Floating-point Instruction Descriptions

# topic.topics[].topics[].label
​Chapter C8
SVE Instruction Descriptions

# topic.topics[].topics[].topics[].label
​C8.2
Alphabetical list of SVE instructions

# topic.topics[].topics[].topics[].topics[].label
​C8.2.32 ASR
(wide elements, predicated)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.32 ASR
(wide elements, predicated)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.35 ASR
(wide elements, unpredicated)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.35 ASR
(wide elements, unpredicated)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.124 DECB,
DECD, DECH, DECW (scalar)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.124 DECB,
DECD, DECH, DECW (scalar)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.280 INCB,
INCD, INCH, INCW (scalar)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.280 INCB,
INCD, INCH, INCW (scalar)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.295
LD1B (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.295
LD1B (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.296
LD1B (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.296
LD1B (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.298
LD1B (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.298
LD1B (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.299
LD1B (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.299
LD1B (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.301
LD1D (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.301
LD1D (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.302
LD1D (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.302
LD1D (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.304
LD1D (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.304
LD1D (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.305
LD1D (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.305
LD1D (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.307
LD1H (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.307
LD1H (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.308
LD1H (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.308
LD1H (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.310
LD1H (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.310
LD1H (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.311
LD1H (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.311
LD1H (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.317
LD1ROB (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.317
LD1ROB (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.319
LD1ROD (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.319
LD1ROD (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.321
LD1ROH (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.321
LD1ROH (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.323
LD1ROW (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.323
LD1ROW (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.325
LD1RQB (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.325
LD1RQB (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.327
LD1RQD (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.327
LD1RQD (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.329
LD1RQH (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.329
LD1RQH (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.331
LD1RQW (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.331
LD1RQW (scalar plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.349
LD1W (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.349
LD1W (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.350
LD1W (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.350
LD1W (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.352
LD1W (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.352
LD1W (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.353
LD1W (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.353
LD1W (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.385
LDFF1B (vector plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.385
LDFF1B (vector plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.388
LDFF1D (vector plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.388
LDFF1D (vector plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.391
LDFF1H (vector plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.391
LDFF1H (vector plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.394
LDFF1SB (vector plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.394
LDFF1SB (vector plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.397
LDFF1SH (vector plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.397
LDFF1SH (vector plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.400
LDFF1SW (vector plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.400
LDFF1SW (vector plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.403
LDFF1W (vector plus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.403
LDFF1W (vector plus immediate)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.413
LDNT1B (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.413
LDNT1B (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.414
LDNT1B (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.414
LDNT1B (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.416
LDNT1B (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.416
LDNT1B (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.417
LDNT1B (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.417
LDNT1B (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.418
LDNT1D (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.418
LDNT1D (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.419
LDNT1D (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.419
LDNT1D (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.421
LDNT1D (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.421
LDNT1D (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.422
LDNT1D (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.422
LDNT1D (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.423
LDNT1H (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.423
LDNT1H (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.424
LDNT1H (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.424
LDNT1H (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.426
LDNT1H (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.426
LDNT1H (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.427
LDNT1H (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.427
LDNT1H (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.431
LDNT1W (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.431
LDNT1W (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.432
LDNT1W (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.432
LDNT1W (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.434
LDNT1W (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.434
LDNT1W (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.435
LDNT1W (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.435
LDNT1W (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.439 LSL
(wide elements, predicated)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.439 LSL
(wide elements, predicated)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.442 LSL
(wide elements, unpredicated)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.442 LSL
(wide elements, unpredicated)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.445 LSR
(wide elements, predicated)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.445 LSR
(wide elements, predicated)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.448 LSR
(wide elements, unpredicated)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.448 LSR
(wide elements, unpredicated)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.464
MOV (SIMD&FP scalar, predicated)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.464
MOV (SIMD&FP scalar, predicated)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.467
MOV (SIMD&FP scalar, unpredicated)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.467
MOV (SIMD&FP scalar, unpredicated)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.701
ST1B (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.701
ST1B (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.702
ST1B (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.702
ST1B (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.704
ST1B (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.704
ST1B (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.705
ST1B (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.705
ST1B (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.707
ST1D (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.707
ST1D (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.708
ST1D (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.708
ST1D (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.710
ST1D (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.710
ST1D (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.711
ST1D (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.711
ST1D (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.713
ST1H (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.713
ST1H (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.714
ST1H (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.714
ST1H (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.716
ST1H (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.716
ST1H (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.717
ST1H (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.717
ST1H (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.720
ST1W (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.720
ST1W (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.721
ST1W (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.721
ST1W (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.723
ST1W (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.723
ST1W (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.724
ST1W (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.724
ST1W (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.756
STNT1B (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.756
STNT1B (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.757
STNT1B (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.757
STNT1B (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.759
STNT1B (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.759
STNT1B (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.760
STNT1B (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.760
STNT1B (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.761
STNT1D (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.761
STNT1D (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.762
STNT1D (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.762
STNT1D (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.764
STNT1D (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.764
STNT1D (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.765
STNT1D (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.765
STNT1D (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.766
STNT1H (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.766
STNT1H (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.767
STNT1H (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.767
STNT1H (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.769
STNT1H (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.769
STNT1H (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.770
STNT1H (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.770
STNT1H (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.771
STNT1W (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.771
STNT1W (scalar plus immediate, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.772
STNT1W (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.772
STNT1W (scalar plus scalar, consecutive registers)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.774
STNT1W (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.774
STNT1W (scalar plus immediate, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.775
STNT1W (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.775
STNT1W (scalar plus scalar, single register)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.908
WHILEGE (predicate as counter)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.908
WHILEGE (predicate as counter)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.911
WHILEGT (predicate as counter)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.911
WHILEGT (predicate as counter)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.914
WHILEHI (predicate as counter)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.914
WHILEHI (predicate as counter)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.917
WHILEHS (predicate as counter)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.917
WHILEHS (predicate as counter)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.920
WHILELE (predicate as counter)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.920
WHILELE (predicate as counter)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.923
WHILELO (predicate as counter)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.923
WHILELO (predicate as counter)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.926
WHILELS (predicate as counter)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.926
WHILELS (predicate as counter)

# topic.topics[].topics[].topics[].topics[].label
​C8.2.929
WHILELT (predicate as counter)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C8.2.929
WHILELT (predicate as counter)

# topic.topics[].topics[].topics[].anchors[].title
​C8.2
Alphabetical list of SVE instructions

# topic.topics[].topics[].anchors[].title
​Chapter C8
SVE Instruction Descriptions

# topic.topics[].topics[].label
​Chapter C9
SME Instruction Descriptions

# topic.topics[].topics[].topics[].label
​C9.2
Alphabetical list of SME instructions

# topic.topics[].topics[].topics[].topics[].label
​C9.2.1 ADD
(to vector, multiple vectors)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.1 ADD
(to vector, multiple vectors)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.2 ADD (to
array, array and multiple vectors)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.2 ADD (to
array, array and multiple vectors)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.3 ADD
(to array, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.3 ADD
(to array, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.4 ADD
(to array, multiple vectors)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.4 ADD
(to array, multiple vectors)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.13
BFCVT (BFloat16 to 8-bit floating-point)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.13
BFCVT (BFloat16 to 8-bit floating-point)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.14
BFCVT (single-precision to BFloat16)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.14
BFCVT (single-precision to BFloat16)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.16
BFDOT (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.16
BFDOT (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.17
BFDOT (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.17
BFDOT (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.19
BFMAX (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.19
BFMAX (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.21
BFMAXNM (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.21
BFMAXNM (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.23
BFMIN (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.23
BFMIN (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.25
BFMINNM (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.25
BFMINNM (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.27
BFMLA (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.27
BFMLA (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.28
BFMLA (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.28
BFMLA (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.30
BFMLAL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.30
BFMLAL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.31
BFMLAL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.31
BFMLAL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.33
BFMLS (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.33
BFMLS (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.34
BFMLS (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.34
BFMLS (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.36
BFMLSL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.36
BFMLSL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.37
BFMLSL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.37
BFMLSL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.47
BFMUL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.47
BFMUL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.49
BFSCALE (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.49
BFSCALE (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.72
FDOT (4-way, multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.72
FDOT (4-way, multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.73
FDOT (4-way, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.73
FDOT (4-way, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.75
FDOT (2-way, multiple and indexed vector, FP8 to FP16)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.75
FDOT (2-way, multiple and indexed vector, FP8 to FP16)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.76
FDOT (2-way, multiple and single vector, FP8 to FP16)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.76
FDOT (2-way, multiple and single vector, FP8 to FP16)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.77
FDOT (2-way, multiple vectors, FP8 to FP16)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.77
FDOT (2-way, multiple vectors, FP8 to FP16)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.78 FDOT
(2-way, multiple and indexed vector, FP16 to FP32)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.78 FDOT
(2-way, multiple and indexed vector, FP16 to FP32)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.79 FDOT
(2-way, multiple and single vector, FP16 to FP32)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.79 FDOT
(2-way, multiple and single vector, FP16 to FP32)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.80 FDOT
(2-way, multiple vectors, FP16 to FP32)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.80 FDOT
(2-way, multiple vectors, FP16 to FP32)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.81 FMAX
(multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.81 FMAX
(multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.83
FMAXNM (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.83
FMAXNM (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.85 FMIN
(multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.85 FMIN
(multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.87
FMINNM (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.87
FMINNM (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.89 FMLA
(multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.89 FMLA
(multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.90 FMLA
(multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.90 FMLA
(multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.92
FMLAL (multiple and indexed vector, FP8 to FP16)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.92
FMLAL (multiple and indexed vector, FP8 to FP16)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.93
FMLAL (multiple and single vector, FP8 to FP16)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.93
FMLAL (multiple and single vector, FP8 to FP16)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.94
FMLAL (multiple vectors, FP8 to FP16)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.94
FMLAL (multiple vectors, FP8 to FP16)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.95
FMLAL (multiple and indexed vector, FP16 to FP32)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.95
FMLAL (multiple and indexed vector, FP16 to FP32)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.96
FMLAL (multiple and single vector, FP16 to FP32)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.96
FMLAL (multiple and single vector, FP16 to FP32)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.97
FMLAL (multiple vectors, FP16 to FP32)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.97
FMLAL (multiple vectors, FP16 to FP32)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.98
FMLALL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.98
FMLALL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.99
FMLALL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.99
FMLALL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.101
FMLS (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.101
FMLS (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.102
FMLS (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.102
FMLS (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.104
FMLSL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.104
FMLSL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.105
FMLSL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.105
FMLSL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.119
FMUL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.119
FMUL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.125
FSCALE (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.125
FSCALE (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.136
LD1B (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.136
LD1B (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.137
LD1B (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.137
LD1B (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.138
LD1B (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.138
LD1B (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.139
LD1D (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.139
LD1D (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.140
LD1D (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.140
LD1D (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.141
LD1D (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.141
LD1D (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.142
LD1H (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.142
LD1H (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.143
LD1H (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.143
LD1H (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.144
LD1H (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.144
LD1H (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.146
LD1W (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.146
LD1W (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.147
LD1W (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.147
LD1W (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.148
LD1W (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.148
LD1W (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.149
LDNT1B (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.149
LDNT1B (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.150
LDNT1B (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.150
LDNT1B (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.151
LDNT1D (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.151
LDNT1D (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.152
LDNT1D (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.152
LDNT1D (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.153
LDNT1H (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.153
LDNT1H (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.154
LDNT1H (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.154
LDNT1H (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.155
LDNT1W (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.155
LDNT1W (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.156
LDNT1W (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.156
LDNT1W (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.164
LUTI4 (four registers, 16-bit and 32-bit)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.164
LUTI4 (four registers, 16-bit and 32-bit)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.166
MOV (tile to vector, two registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.166
MOV (tile to vector, two registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.167
MOV (tile to vector, four registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.167
MOV (tile to vector, four registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.168
MOV (array to vector, two registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.168
MOV (array to vector, two registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.169
MOV (array to vector, four registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.169
MOV (array to vector, four registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.171
MOV (vector to tile, two registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.171
MOV (vector to tile, two registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.172
MOV (vector to tile, four registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.172
MOV (vector to tile, four registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.173
MOV (vector to array, two registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.173
MOV (vector to array, two registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.174
MOV (vector to array, four registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.174
MOV (vector to array, four registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.176
MOVA (tile to vector, two registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.176
MOVA (tile to vector, two registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.177
MOVA (tile to vector, four registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.177
MOVA (tile to vector, four registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.178
MOVA (array to vector, two registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.178
MOVA (array to vector, two registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.179
MOVA (array to vector, four registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.179
MOVA (array to vector, four registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.181 MOVA
(vector to tile, two registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.181 MOVA
(vector to tile, two registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.182 MOVA
(vector to tile, four registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.182 MOVA
(vector to tile, four registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.183
MOVA (vector to array, two registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.183
MOVA (vector to array, two registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.184
MOVA (vector to array, four registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.184
MOVA (vector to array, four registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.186
MOVAZ (tile to vector, two registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.186
MOVAZ (tile to vector, two registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.187
MOVAZ (tile to vector, four registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.187
MOVAZ (tile to vector, four registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.188
MOVAZ (array to vector, two registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.188
MOVAZ (array to vector, two registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.189
MOVAZ (array to vector, four registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.189
MOVAZ (array to vector, four registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.190
MOVAZ (tile to vector, single)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.190
MOVAZ (tile to vector, single)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.197
SDOT (2-way, multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.197
SDOT (2-way, multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.198
SDOT (2-way, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.198
SDOT (2-way, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.199
SDOT (2-way, multiple vectors)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.199
SDOT (2-way, multiple vectors)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.200
SDOT (4-way, multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.200
SDOT (4-way, multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.201
SDOT (4-way, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.201
SDOT (4-way, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.202
SDOT (4-way, multiple vectors)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.202
SDOT (4-way, multiple vectors)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.204
SMAX (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.204
SMAX (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.206
SMIN (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.206
SMIN (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.208
SMLAL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.208
SMLAL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.209
SMLAL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.209
SMLAL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.211
SMLALL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.211
SMLALL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.212
SMLALL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.212
SMLALL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.214
SMLSL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.214
SMLSL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.215
SMLSL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.215
SMLSL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.217
SMLSLL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.217
SMLSLL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.218
SMLSLL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.218
SMLSLL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.234
SQDMULH (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.234
SQDMULH (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.242
SRSHL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.242
SRSHL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.244
ST1B (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.244
ST1B (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.245
ST1B (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.245
ST1B (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.246
ST1B (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.246
ST1B (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.247
ST1D (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.247
ST1D (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.248
ST1D (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.248
ST1D (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.249
ST1D (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.249
ST1D (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.250
ST1H (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.250
ST1H (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.251
ST1H (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.251
ST1H (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.252
ST1H (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.252
ST1H (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.254
ST1W (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.254
ST1W (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.255
ST1W (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.255
ST1W (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.256
ST1W (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.256
ST1W (scalar plus scalar, tile slice)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.259
STNT1B (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.259
STNT1B (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.260
STNT1B (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.260
STNT1B (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.261
STNT1D (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.261
STNT1D (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.262
STNT1D (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.262
STNT1D (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.263
STNT1H (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.263
STNT1H (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.264
STNT1H (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.264
STNT1H (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.265
STNT1W (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.265
STNT1W (scalar plus immediate, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.266
STNT1W (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.266
STNT1W (scalar plus scalar, strided registers)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.269 SUB
(to array, array and multiple vectors)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.269 SUB
(to array, array and multiple vectors)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.270 SUB
(to array, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.270 SUB
(to array, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.271 SUB
(to array, multiple vectors)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.271 SUB
(to array, multiple vectors)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.272
SUDOT (4-way, multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.272
SUDOT (4-way, multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.273
SUDOT (4-way, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.273
SUDOT (4-way, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.274
SUMLALL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.274
SUMLALL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.275
SUMLALL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.275
SUMLALL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.287
UDOT (2-way, multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.287
UDOT (2-way, multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.288
UDOT (2-way, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.288
UDOT (2-way, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.289
UDOT (2-way, multiple vectors)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.289
UDOT (2-way, multiple vectors)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.290
UDOT (4-way, multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.290
UDOT (4-way, multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.291
UDOT (4-way, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.291
UDOT (4-way, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.292
UDOT (4-way, multiple vectors)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.292
UDOT (4-way, multiple vectors)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.293
UMAX (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.293
UMAX (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.295
UMIN (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.295
UMIN (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.297
UMLAL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.297
UMLAL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.298
UMLAL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.298
UMLAL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.300
UMLALL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.300
UMLALL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.301
UMLALL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.301
UMLALL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.303
UMLSL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.303
UMLSL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.304
UMLSL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.304
UMLSL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.306
UMLSLL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.306
UMLSLL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.307
UMLSLL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.307
UMLSLL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.323
URSHL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.323
URSHL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.325
USDOT (4-way, multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.325
USDOT (4-way, multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.326
USDOT (4-way, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.326
USDOT (4-way, multiple and single vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.327
USDOT (4-way, multiple vectors)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.327
USDOT (4-way, multiple vectors)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.328
USMLALL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.328
USMLALL (multiple and indexed vector)

# topic.topics[].topics[].topics[].topics[].label
​C9.2.329
USMLALL (multiple and single vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​C9.2.329
USMLALL (multiple and single vector)

# topic.topics[].topics[].topics[].anchors[].title
​C9.2
Alphabetical list of SME instructions

# topic.topics[].topics[].anchors[].title
​Chapter C9
SME Instruction Descriptions

# topic.topics[].label
​Part D The AArch64 System Level
Architecture

# topic.topics[].topics[].label
​Chapter D1 The AArch64 System Level
Programmers’ Model

# topic.topics[].topics[].topics[].topics[].label
​D1.1.3 Effect of not implementing an
Exception level

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D1.1.3 Effect of not implementing an
Exception level

# topic.topics[].topics[].topics[].label
​D1.2 Registers for instruction processing
and exception handling

# topic.topics[].topics[].topics[].topics[].label
​D1.2.3 The SIMD and floating-point
registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D1.2.3 The SIMD and floating-point
registers

# topic.topics[].topics[].topics[].anchors[].title
​D1.2 Registers for instruction processing
and exception handling

# topic.topics[].topics[].topics[].topics[].label
​D1.3.2 EL12 alias names for mask
registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D1.3.2 EL12 alias names for mask
registers

# topic.topics[].topics[].topics[].topics[].label
​D1.4.10 Program Counter and stack pointer
alignment

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D1.4.10 Program Counter and stack pointer
alignment

# topic.topics[].topics[].topics[].topics[].label
​D1.5.1 PSTATE fields that are meaningful in
AArch64 state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D1.5.1 PSTATE fields that are meaningful in
AArch64 state

# topic.topics[].topics[].topics[].label
​D1.7 Mechanisms for entering a low-power
state

# topic.topics[].topics[].topics[].topics[].label
​D1.7.4 Using WFI to indicate an idle state
on bus interfaces

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D1.7.4 Using WFI to indicate an idle state
on bus interfaces

# topic.topics[].topics[].topics[].anchors[].title
​D1.7 Mechanisms for entering a low-power
state

# topic.topics[].topics[].topics[].topics[].label
​D1.9.1 The Performance Monitors
Extension

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D1.9.1 The Performance Monitors
Extension

# topic.topics[].topics[].topics[].topics[].label
​D1.10.1 Register mappings between AArch32
state and AArch64 state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D1.10.1 Register mappings between AArch32
state and AArch64 state

# topic.topics[].topics[].anchors[].title
​Chapter D1 The AArch64 System Level
Programmers’ Model

# topic.topics[].topics[].topics[].topics[].label
​D2.1.1 Definition of a debugger in the
context of self-hosted debug

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.1.1 Definition of a debugger in the
context of self-hosted debug

# topic.topics[].topics[].topics[].topics[].label
​D2.2.1 Pseudocode description of routing
debug exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.2.1 Pseudocode description of routing
debug exceptions

# topic.topics[].topics[].topics[].label
​D2.3 The debug exception enable
controls

# topic.topics[].topics[].topics[].topics[].label
​D2.3.1 Enabling debug exceptions from the
current Exception level and Security state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.3.1 Enabling debug exceptions from the
current Exception level and Security state

# topic.topics[].topics[].topics[].topics[].label
​D2.3.2 Pseudocode description of enabling
debug exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.3.2 Pseudocode description of enabling
debug exceptions

# topic.topics[].topics[].topics[].anchors[].title
​D2.3 The debug exception enable
controls

# topic.topics[].topics[].topics[].label
​D2.4 The effect of powerdown on debug
exceptions

# topic.topics[].topics[].topics[].anchors[].title
​D2.4 The effect of powerdown on debug
exceptions

# topic.topics[].topics[].topics[].label
​D2.5 Summary of the routing and enabling of
debug exceptions

# topic.topics[].topics[].topics[].anchors[].title
​D2.5 Summary of the routing and enabling of
debug exceptions

# topic.topics[].topics[].topics[].label
​D2.6 Pseudocode description of debug
exceptions

# topic.topics[].topics[].topics[].anchors[].title
​D2.6 Pseudocode description of debug
exceptions

# topic.topics[].topics[].topics[].topics[].label
​D2.7.1 About Breakpoint Instruction
exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.7.1 About Breakpoint Instruction
exceptions

# topic.topics[].topics[].topics[].topics[].label
​D2.7.3 Exception syndrome information and
preferred return address

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.7.3 Exception syndrome information and
preferred return address

# topic.topics[].topics[].topics[].topics[].label
​D2.7.4 Pseudocode description of Breakpoint
Instruction exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.7.4 Pseudocode description of Breakpoint
Instruction exceptions

# topic.topics[].topics[].topics[].topics[].label
​D2.8.2 Accessing breakpoint System
registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.8.2 Accessing breakpoint System
registers

# topic.topics[].topics[].topics[].topics[].label
​D2.8.3 Breakpoint types and linking of
breakpoints

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.8.3 Breakpoint types and linking of
breakpoints

# topic.topics[].topics[].topics[].topics[].label
​D2.8.4 Execution conditions for which a
breakpoint generates Breakpoint exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.8.4 Execution conditions for which a
breakpoint generates Breakpoint exceptions

# topic.topics[].topics[].topics[].topics[].label
​D2.8.9 Pseudocode description of Breakpoint
exceptions taken from an AArch64 stage 1 translation regime

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.8.9 Pseudocode description of Breakpoint
exceptions taken from an AArch64 stage 1 translation regime

# topic.topics[].topics[].topics[].topics[].label
​D2.9.2 Accessing watchpoint System
registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.9.2 Accessing watchpoint System
registers

# topic.topics[].topics[].topics[].topics[].label
​D2.9.3 Watchpoint types and linking of
watchpoints

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.9.3 Watchpoint types and linking of
watchpoints

# topic.topics[].topics[].topics[].topics[].label
​D2.9.4 Execution conditions for which a
watchpoint generates Watchpoint exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.9.4 Execution conditions for which a
watchpoint generates Watchpoint exceptions

# topic.topics[].topics[].topics[].topics[].label
​D2.9.5 Watchpoint data address
comparisons

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.9.5 Watchpoint data address
comparisons

# topic.topics[].topics[].topics[].topics[].label
​D2.9.6 Watchpoint behavior for certain
instruction classes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.9.6 Watchpoint behavior for certain
instruction classes

# topic.topics[].topics[].topics[].topics[].label
​D2.9.8 Exception syndrome information,
fault address information, and preferred return address

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.9.8 Exception syndrome information,
fault address information, and preferred return address

# topic.topics[].topics[].topics[].topics[].label
​D2.9.9 Pseudocode description of Watchpoint
exceptions taken from AArch64 state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.9.9 Pseudocode description of Watchpoint
exceptions taken from AArch64 state

# topic.topics[].topics[].topics[].topics[].label
​D2.11.2 Rules for setting MDSCR_EL1.SS to
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.11.2 Rules for setting MDSCR_EL1.SS to
1

# topic.topics[].topics[].topics[].topics[].label
​D2.11.3 The software step state
machine

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.11.3 The software step state
machine

# topic.topics[].topics[].topics[].topics[].label
​D2.11.4 Entering the active-not-pending
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.11.4 Entering the active-not-pending
state

# topic.topics[].topics[].topics[].topics[].label
​D2.11.5 Behavior in the active-not-pending
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.11.5 Behavior in the active-not-pending
state

# topic.topics[].topics[].topics[].topics[].label
​D2.11.6 Entering the active-pending
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.11.6 Entering the active-pending
state

# topic.topics[].topics[].topics[].topics[].label
​D2.11.7 Behavior in the active-pending
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.11.7 Behavior in the active-pending
state

# topic.topics[].topics[].topics[].topics[].label
​D2.11.9 Exception syndrome information and
preferred return address

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.11.9 Exception syndrome information and
preferred return address

# topic.topics[].topics[].topics[].topics[].label
​D2.11.11 Pseudocode description of Software
Step exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D2.11.11 Pseudocode description of Software
Step exceptions

# topic.topics[].topics[].topics[].label
​D2.12 Synchronization and debug
exceptions

# topic.topics[].topics[].topics[].anchors[].title
​D2.12 Synchronization and debug
exceptions

# topic.topics[].topics[].topics[].topics[].label
​D3.1.2 Register controls to enable
self-hosted trace

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D3.1.2 Register controls to enable
self-hosted trace

# topic.topics[].topics[].topics[].label
​D3.2 Prohibited regions in self-hosted
trace

# topic.topics[].topics[].topics[].topics[].label
​D3.2.1 Controls to prohibit trace at
Exception levels

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D3.2.1 Controls to prohibit trace at
Exception levels

# topic.topics[].topics[].topics[].topics[].label
​D3.2.2 Self-hosted trace and visibility of
virtual data

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D3.2.2 Self-hosted trace and visibility of
virtual data

# topic.topics[].topics[].topics[].anchors[].title
​D3.2 Prohibited regions in self-hosted
trace

# topic.topics[].topics[].topics[].label
​D3.4 Synchronization in self-hosted
trace

# topic.topics[].topics[].topics[].anchors[].title
​D3.4 Synchronization in self-hosted
trace

# topic.topics[].topics[].label
​Chapter D4
The Embedded Trace Extension

# topic.topics[].topics[].topics[].label
​D4.1 About
the Embedded Trace Extension

# topic.topics[].topics[].topics[].anchors[].title
​D4.1 About
the Embedded Trace Extension

# topic.topics[].topics[].topics[].topics[].label
​D4.2.2 Synchronization of register
updates

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D4.2.2 Synchronization of register
updates

# topic.topics[].topics[].topics[].topics[].label
​D4.3.3 Speculation in the trace element
stream

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D4.3.3 Speculation in the trace element
stream

# topic.topics[].topics[].topics[].label
​D4.4 Instruction and exception
classification

# topic.topics[].topics[].topics[].topics[].label
​D4.4.4 Exceptions to Exception element
encoding

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D4.4.4 Exceptions to Exception element
encoding

# topic.topics[].topics[].topics[].anchors[].title
​D4.4 Instruction and exception
classification

# topic.topics[].topics[].topics[].topics[].label
​D4.5.3
Trace unit behavior while the PE is in Debug state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D4.5.3
Trace unit behavior while the PE is in Debug state

# topic.topics[].topics[].topics[].topics[].label
​D4.5.4 Trace unit behavior on a trace unit
buffer overflow

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D4.5.4 Trace unit behavior on a trace unit
buffer overflow

# topic.topics[].topics[].topics[].topics[].label
​D4.6.1 Behavior of the resources while in
the Running state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D4.6.1 Behavior of the resources while in
the Running state

# topic.topics[].topics[].topics[].topics[].label
​D4.6.2
Behavior of the resources while in the Pausing state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D4.6.2
Behavior of the resources while in the Pausing state

# topic.topics[].topics[].topics[].topics[].label
​D4.6.3
Behavior of the resources while in the Paused state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D4.6.3
Behavior of the resources while in the Paused state

# topic.topics[].topics[].topics[].topics[].label
​D4.6.4 Behavior of resources on a Trace
synchronization event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D4.6.4 Behavior of resources on a Trace
synchronization event

# topic.topics[].topics[].topics[].topics[].label
​D4.6.8 Virtual Context Identifier
Comparators

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D4.6.8 Virtual Context Identifier
Comparators

# topic.topics[].topics[].anchors[].title
​Chapter D4
The Embedded Trace Extension

# topic.topics[].topics[].topics[].topics[].label
​D5.3.12 Cycle Count Format 1_0 unknown
count Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.12 Cycle Count Format 1_0 unknown
count Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.13 Cycle Count Format 1_0 with count
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.13 Cycle Count Format 1_0 with count
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.14 Cycle Count Format 1_1 unknown
count Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.14 Cycle Count Format 1_1 unknown
count Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.15 Cycle Count Format 1_1 with count
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.15 Cycle Count Format 1_1 with count
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.16 Cycle Count Format 2_0 large commit
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.16 Cycle Count Format 2_0 large commit
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.20 Cycle Count Format 2_0 small commit
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.20 Cycle Count Format 2_0 small commit
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.26 Exception 32-bit Address IS0
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.26 Exception 32-bit Address IS0
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.27 Exception 32-bit Address IS0 with
Context Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.27 Exception 32-bit Address IS0 with
Context Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.28 Exception 32-bit Address IS1
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.28 Exception 32-bit Address IS1
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.29 Exception 32-bit Address IS1 with
Context Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.29 Exception 32-bit Address IS1 with
Context Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.30 Exception 64-bit Address IS0
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.30 Exception 64-bit Address IS0
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.31 Exception 64-bit Address IS0 with
Context Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.31 Exception 64-bit Address IS0 with
Context Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.32 Exception 64-bit Address IS1
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.32 Exception 64-bit Address IS1
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.33 Exception 64-bit Address IS1 with
Context Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.33 Exception 64-bit Address IS1 with
Context Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.34 Exception Exact Match Address
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.34 Exception Exact Match Address
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.35 Exception Short Address IS0
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.35 Exception Short Address IS0
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.36 Exception Short Address IS1
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.36 Exception Short Address IS1
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.48 Q with Exact match address
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.48 Q with Exact match address
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.49 Source Address 32-bit IS0
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.49 Source Address 32-bit IS0
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.50 Source Address 32-bit IS1
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.50 Source Address 32-bit IS1
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.51 Source Address 64-bit IS0
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.51 Source Address 64-bit IS0
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.52 Source Address 64-bit IS1
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.52 Source Address 64-bit IS1
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.53 Source Address Exact Match
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.53 Source Address Exact Match
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.54 Source Address Short IS0
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.54 Source Address Short IS0
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.55 Source Address Short IS1
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.55 Source Address Short IS1
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.58 Target Address 32-bit IS0
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.58 Target Address 32-bit IS0
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.59 Target Address 32-bit IS1
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.59 Target Address 32-bit IS1
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.60 Target Address 64-bit IS0
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.60 Target Address 64-bit IS0
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.61 Target Address 64-bit IS1
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.61 Target Address 64-bit IS1
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.62 Target Address Exact Match
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.62 Target Address Exact Match
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.63 Target Address Short IS0
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.63 Target Address Short IS0
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.64 Target Address Short IS1
Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.64 Target Address Short IS1
Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.65 Target Address with Context 32-bit
IS0 Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.65 Target Address with Context 32-bit
IS0 Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.66 Target Address with Context 32-bit
IS1 Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.66 Target Address with Context 32-bit
IS1 Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.67 Target Address with Context 64-bit
IS0 Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.67 Target Address with Context 64-bit
IS0 Packet

# topic.topics[].topics[].topics[].topics[].label
​D5.3.68 Target Address with Context 64-bit
IS1 Packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D5.3.68 Target Address with Context 64-bit
IS1 Packet

# topic.topics[].topics[].topics[].topics[].label
​D6.2.2
Restrictions on programming the Trace Buffer Unit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D6.2.2
Restrictions on programming the Trace Buffer Unit

# topic.topics[].topics[].topics[].topics[].label
​D6.2.3 Effect on the exclusive monitors and
transactions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D6.2.3 Effect on the exclusive monitors and
transactions

# topic.topics[].topics[].topics[].topics[].label
​D6.3.1 Behavior when address translation is
enabled

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D6.3.1 Behavior when address translation is
enabled

# topic.topics[].topics[].topics[].topics[].label
​D6.3.2 Behavior when address translation is
disabled

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D6.3.2 Behavior when address translation is
disabled

# topic.topics[].topics[].topics[].topics[].label
​D6.4.1 The external Trace Buffer debug
component

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D6.4.1 The external Trace Buffer debug
component

# topic.topics[].topics[].topics[].topics[].label
​D6.4.3 External mode and the Realm
Management Extension

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D6.4.3 External mode and the Realm
Management Extension

# topic.topics[].topics[].topics[].topics[].label
​D6.5.1 Prioritization of a trace buffer
management event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D6.5.1 Prioritization of a trace buffer
management event

# topic.topics[].topics[].topics[].topics[].label
​D6.5.2 Buffer full and buffer wrap
events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D6.5.2 Buffer full and buffer wrap
events

# topic.topics[].topics[].topics[].topics[].label
​D6.5.6
IMPLEMENTATION DEFINED management events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D6.5.6
IMPLEMENTATION DEFINED management events

# topic.topics[].topics[].topics[].label
​D6.6
Synchronization and the Trace Buffer Unit

# topic.topics[].topics[].topics[].topics[].label
​D6.6.2 Trace synchronization and the Trace
Unit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D6.6.2 Trace synchronization and the Trace
Unit

# topic.topics[].topics[].topics[].topics[].label
​D6.6.3 Self-hosted trace extension
synchronization rules

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D6.6.3 Self-hosted trace extension
synchronization rules

# topic.topics[].topics[].topics[].anchors[].title
​D6.6
Synchronization and the Trace Buffer Unit

# topic.topics[].topics[].topics[].label
​D6.7 Trace synchronization and memory
barriers

# topic.topics[].topics[].topics[].anchors[].title
​D6.7 Trace synchronization and memory
barriers

# topic.topics[].topics[].label
​Chapter D7 The AArch64 System Level Memory
Model

# topic.topics[].topics[].topics[].label
​D7.1 About the memory system
architecture

# topic.topics[].topics[].topics[].topics[].label
​D7.1.1 Form of the memory system
architecture

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D7.1.1 Form of the memory system
architecture

# topic.topics[].topics[].topics[].anchors[].title
​D7.1 About the memory system
architecture

# topic.topics[].topics[].topics[].topics[].label
​D7.4.3 Restrictions on the effects of
speculation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D7.4.3 Restrictions on the effects of
speculation

# topic.topics[].topics[].topics[].topics[].label
​D7.5.3 Cacheability, cache allocation
hints, and cache transient hints

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D7.5.3 Cacheability, cache allocation
hints, and cache transient hints

# topic.topics[].topics[].topics[].topics[].label
​D7.5.5 Enabling and disabling the caching
of memory accesses

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D7.5.5 Enabling and disabling the caching
of memory accesses

# topic.topics[].topics[].topics[].topics[].label
​D7.5.7 Non-cacheable accesses and
instruction caches

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D7.5.7 Non-cacheable accesses and
instruction caches

# topic.topics[].topics[].topics[].topics[].label
​D7.5.8 About cache maintenance in AArch64
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D7.5.8 About cache maintenance in AArch64
state

# topic.topics[].topics[].topics[].topics[].label
​D7.5.9 A64 Cache maintenance
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D7.5.9 A64 Cache maintenance
instructions

# topic.topics[].topics[].topics[].topics[].label
​D7.6.1 Provision for the classification of
External aborts

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D7.6.1 Provision for the classification of
External aborts

# topic.topics[].topics[].topics[].topics[].label
​D7.6.2 Parity or ECC error reporting, RAS
Extension not implemented

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D7.6.2 Parity or ECC error reporting, RAS
Extension not implemented

# topic.topics[].topics[].topics[].topics[].label
​D7.7.1 EL2 control of the shareability of
data barrier instructions executed at EL0 or EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D7.7.1 EL2 control of the shareability of
data barrier instructions executed at EL0 or EL1

# topic.topics[].topics[].topics[].label
​D7.8 Pseudocode description of general
memory System instructions

# topic.topics[].topics[].topics[].anchors[].title
​D7.8 Pseudocode description of general
memory System instructions

# topic.topics[].topics[].anchors[].title
​Chapter D7 The AArch64 System Level Memory
Model

# topic.topics[].topics[].label
​Chapter D8 The AArch64 Virtual Memory
System Architecture

# topic.topics[].topics[].topics[].topics[].label
​D8.1.3 Relationship between translation
regimes and implemented Exception levels

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.1.3 Relationship between translation
regimes and implemented Exception levels

# topic.topics[].topics[].topics[].topics[].label
​D8.1.4 The system registers relevant to MMU
operation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.1.4 The system registers relevant to MMU
operation

# topic.topics[].topics[].topics[].topics[].label
​D8.1.6 Implemented physical address
size

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.1.6 Implemented physical address
size

# topic.topics[].topics[].topics[].topics[].label
​D8.1.7 Output address size
configuration

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.1.7 Output address size
configuration

# topic.topics[].topics[].topics[].topics[].label
​D8.1.8 Supported virtual address
ranges

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.1.8 Supported virtual address
ranges

# topic.topics[].topics[].topics[].topics[].label
​D8.1.9 Input address size
configuration

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.1.9 Input address size
configuration

# topic.topics[].topics[].topics[].topics[].label
​D8.1.10 Intermediate physical address size
configuration

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.1.10 Intermediate physical address size
configuration

# topic.topics[].topics[].topics[].topics[].label
​D8.2.3 Translation table base address
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.2.3 Translation table base address
register

# topic.topics[].topics[].topics[].topics[].label
​D8.2.4 Selection between TTBR0_ELx and
TTBR1_ELx when two VA ranges are supported

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.2.4 Selection between TTBR0_ELx and
TTBR1_ELx when two VA ranges are supported

# topic.topics[].topics[].topics[].topics[].label
​D8.2.5 Translation table and translation
table lookup properties

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.2.5 Translation table and translation
table lookup properties

# topic.topics[].topics[].topics[].topics[].label
​D8.2.6 Translation table walk
properties

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.2.6 Translation table walk
properties

# topic.topics[].topics[].topics[].topics[].label
​D8.2.8 VMSAv8-64 translation using the 4KB
granule

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.2.8 VMSAv8-64 translation using the 4KB
granule

# topic.topics[].topics[].topics[].topics[].label
​D8.2.9 VMSAv8-64 translation using the 16KB
granule

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.2.9 VMSAv8-64 translation using the 16KB
granule

# topic.topics[].topics[].topics[].topics[].label
​D8.2.10 VMSAv8-64 translation using the
64KB granule

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.2.10 VMSAv8-64 translation using the
64KB granule

# topic.topics[].topics[].topics[].topics[].label
​D8.2.11 Translation using the VMSAv9-128
translation system

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.2.11 Translation using the VMSAv9-128
translation system

# topic.topics[].topics[].topics[].topics[].label
​D8.2.12 The effects of disabling an address
translation stage

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.2.12 The effects of disabling an address
translation stage

# topic.topics[].topics[].topics[].label
​D8.3 Translation table descriptor
formats

# topic.topics[].topics[].topics[].anchors[].title
​D8.3 Translation table descriptor
formats

# topic.topics[].topics[].topics[].topics[].label
​D8.4.3 Effect of both stage 1 and stage 2
on data access permissions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.4.3 Effect of both stage 1 and stage 2
on data access permissions

# topic.topics[].topics[].topics[].topics[].label
​D8.4.4 Effects on instruction execution
permissions and restrictions on instruction fetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.4.4 Effects on instruction execution
permissions and restrictions on instruction fetch

# topic.topics[].topics[].topics[].topics[].label
​D8.4.5 Effect of PSTATE on access
permission

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.4.5 Effect of PSTATE on access
permission

# topic.topics[].topics[].topics[].topics[].label
​D8.4.6 Controlling memory access Security
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.4.6 Controlling memory access Security
state

# topic.topics[].topics[].topics[].label
​D8.5 Hardware updates to the translation
tables

# topic.topics[].topics[].topics[].topics[].label
​D8.5.3 Ordering of hardware updates to the
translation tables

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.5.3 Ordering of hardware updates to the
translation tables

# topic.topics[].topics[].topics[].topics[].label
​D8.5.4 Restriction on memory types for
hardware updates to translation tables

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.5.4 Restriction on memory types for
hardware updates to translation tables

# topic.topics[].topics[].topics[].topics[].label
​D8.5.5 Use of the Contiguous bit with
hardware updates to the translation tables

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.5.5 Use of the Contiguous bit with
hardware updates to the translation tables

# topic.topics[].topics[].topics[].anchors[].title
​D8.5 Hardware updates to the translation
tables

# topic.topics[].topics[].topics[].topics[].label
​D8.6.1 Stage 1 memory type and Cacheability
attributes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.6.1 Stage 1 memory type and Cacheability
attributes

# topic.topics[].topics[].topics[].topics[].label
​D8.6.3 Stage 2 memory type and Cacheability
attributes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.6.3 Stage 2 memory type and Cacheability
attributes

# topic.topics[].topics[].topics[].topics[].label
​D8.6.4 Stage 2 Memory Tagging
attributes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.6.4 Stage 2 Memory Tagging
attributes

# topic.topics[].topics[].topics[].topics[].label
​D8.6.5 Stage 2 memory type and Cacheability
attributes when FWB is disabled

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.6.5 Stage 2 memory type and Cacheability
attributes when FWB is disabled

# topic.topics[].topics[].topics[].topics[].label
​D8.6.6 Stage 2 memory type and Cacheability
attributes when FWB is enabled

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.6.6 Stage 2 memory type and Cacheability
attributes when FWB is enabled

# topic.topics[].topics[].topics[].topics[].label
​D8.8.2 Effect of address tagging on the
PC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.8.2 Effect of address tagging on the
PC

# topic.topics[].topics[].topics[].topics[].label
​D8.10.2 PAC generation and verification
keys

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.10.2 PAC generation and verification
keys

# topic.topics[].topics[].topics[].topics[].label
​D8.10.5 Faulting on pointer
authentication

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.10.5 Faulting on pointer
authentication

# topic.topics[].topics[].topics[].label
​D8.12
Memory Encryption Contexts extension

# topic.topics[].topics[].topics[].anchors[].title
​D8.12
Memory Encryption Contexts extension

# topic.topics[].topics[].topics[].topics[].label
​D8.13.2 System and Special-purpose register
redirection

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.13.2 System and Special-purpose register
redirection

# topic.topics[].topics[].topics[].topics[].label
​D8.13.3 System and Special-purpose register
aliasing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.13.3 System and Special-purpose register
aliasing

# topic.topics[].topics[].topics[].topics[].label
​D8.14.2 Additional behavior when HCR_EL2.NV
is 1 and HCR_EL2.NV1 is 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.14.2 Additional behavior when HCR_EL2.NV
is 1 and HCR_EL2.NV1 is 0

# topic.topics[].topics[].topics[].topics[].label
​D8.14.3 Additional behavior when HCR_EL2.NV
is 1 and HCR_EL2.NV1 is 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.14.3 Additional behavior when HCR_EL2.NV
is 1 and HCR_EL2.NV1 is 1

# topic.topics[].topics[].topics[].topics[].label
​D8.14.4 Behavior when HCR_EL2.NV is 0 and
HCR_EL2.NV1 is 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.14.4 Behavior when HCR_EL2.NV is 0 and
HCR_EL2.NV1 is 1

# topic.topics[].topics[].topics[].topics[].label
​D8.14.6 Enhanced support for nested
virtualization

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.14.6 Enhanced support for nested
virtualization

# topic.topics[].topics[].topics[].topics[].label
​D8.15.2 MMU faults generated by address
translation instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.15.2 MMU faults generated by address
translation instructions

# topic.topics[].topics[].topics[].topics[].label
​D8.15.3 MMU faults generated by cache
maintenance operations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.15.3 MMU faults generated by cache
maintenance operations

# topic.topics[].topics[].topics[].topics[].label
​D8.15.5 MMU fault prioritization from a
single address translation stage

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.15.5 MMU fault prioritization from a
single address translation stage

# topic.topics[].topics[].topics[].topics[].label
​D8.16.3 Use of ASIDs and VMIDs to reduce
TLB maintenance requirements

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.16.3 Use of ASIDs and VMIDs to reduce
TLB maintenance requirements

# topic.topics[].topics[].topics[].topics[].label
​D8.17.1 Using break-before-make when
updating translation table entries

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.17.1 Using break-before-make when
updating translation table entries

# topic.topics[].topics[].topics[].topics[].label
​D8.17.2 Support levels for changing table
or block size

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.17.2 Support levels for changing table
or block size

# topic.topics[].topics[].topics[].topics[].label
​D8.17.3 TLB maintenance due to TLB
conflict

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.17.3 TLB maintenance due to TLB
conflict

# topic.topics[].topics[].topics[].topics[].label
​D8.17.4 The interaction of TLB lockdown
with TLB maintenance instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.17.4 The interaction of TLB lockdown
with TLB maintenance instructions

# topic.topics[].topics[].topics[].topics[].label
​D8.17.6 Operation of the TLB maintenance
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.17.6 Operation of the TLB maintenance
instructions

# topic.topics[].topics[].topics[].topics[].label
​D8.17.8 Ordering and completion of TLB
maintenance instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.17.8 Ordering and completion of TLB
maintenance instructions

# topic.topics[].topics[].topics[].topics[].label
​D8.18.3 Cache maintenance requirements due
to changing memory region attributes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D8.18.3 Cache maintenance requirements due
to changing memory region attributes

# topic.topics[].topics[].topics[].label
​D8.19 Pseudocode description of VMSA
address translation

# topic.topics[].topics[].topics[].anchors[].title
​D8.19 Pseudocode description of VMSA
address translation

# topic.topics[].topics[].anchors[].title
​Chapter D8 The AArch64 Virtual Memory
System Architecture

# topic.topics[].topics[].label
​Chapter D9 The Granule Protection Check
Mechanism

# topic.topics[].topics[].topics[].topics[].label
​D9.6.5 GPI field encoding in GPT
descriptors

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D9.6.5 GPI field encoding in GPT
descriptors

# topic.topics[].topics[].topics[].topics[].label
​D9.7.1 Ordering of memory accesses from GPT
walks

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D9.7.1 Ordering of memory accesses from GPT
walks

# topic.topics[].topics[].anchors[].title
​Chapter D9 The Granule Protection Check
Mechanism

# topic.topics[].topics[].label
​Chapter D10 The Memory Tagging
Extension

# topic.topics[].topics[].topics[].topics[].label
​D10.3.1 Interactions with Device
memory

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D10.3.1 Interactions with Device
memory

# topic.topics[].topics[].anchors[].title
​Chapter D10 The Memory Tagging
Extension

# topic.topics[].topics[].topics[].topics[].label
​D11.1.1 Protection for return
addresses

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D11.1.1 Protection for return
addresses

# topic.topics[].topics[].topics[].topics[].label
​D11.2.1 Enabling the Guarded Control
Stack

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D11.2.1 Enabling the Guarded Control
Stack

# topic.topics[].topics[].topics[].topics[].label
​D11.3.1 Procedure call and return
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D11.3.1 Procedure call and return
instructions

# topic.topics[].topics[].topics[].topics[].label
​D11.3.2 Management of procedure return
records

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D11.3.2 Management of procedure return
records

# topic.topics[].topics[].topics[].topics[].label
​D11.4.1 Pushing and popping exception
return state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D11.4.1 Pushing and popping exception
return state

# topic.topics[].topics[].topics[].topics[].label
​D11.4.2 Using the exception return
protection features

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D11.4.2 Using the exception return
protection features

# topic.topics[].topics[].topics[].label
​D11.9 Guarded Control Stack data
accesses

# topic.topics[].topics[].topics[].topics[].label
​D11.9.1 Guarded Control Stack data access
behaviors

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D11.9.1 Guarded Control Stack data access
behaviors

# topic.topics[].topics[].topics[].anchors[].title
​D11.9 Guarded Control Stack data
accesses

# topic.topics[].topics[].topics[].label
​D11.10
Detecting when FEAT_GCS is enabled

# topic.topics[].topics[].topics[].anchors[].title
​D11.10
Detecting when FEAT_GCS is enabled

# topic.topics[].topics[].label
​Chapter D12 The Generic Timer in AArch64
state

# topic.topics[].topics[].topics[].topics[].label
​D12.1.1 The full set of Generic Timer
components

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D12.1.1 The full set of Generic Timer
components

# topic.topics[].topics[].topics[].label
​D12.2 The AArch64 view of the Generic
Timer

# topic.topics[].topics[].topics[].anchors[].title
​D12.2 The AArch64 view of the Generic
Timer

# topic.topics[].topics[].anchors[].title
​Chapter D12 The Generic Timer in AArch64
state

# topic.topics[].topics[].label
​Chapter D13 The Performance Monitors
Extension

# topic.topics[].topics[].topics[].label
​D13.2 Accuracy of the Performance
Monitors

# topic.topics[].topics[].topics[].topics[].label
​D13.2.2 A reasonable degree of
inaccuracy

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D13.2.2 A reasonable degree of
inaccuracy

# topic.topics[].topics[].topics[].anchors[].title
​D13.2 Accuracy of the Performance
Monitors

# topic.topics[].topics[].topics[].topics[].label
​D13.3.1 Generating overflow interrupt
requests

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D13.3.1 Generating overflow interrupt
requests

# topic.topics[].topics[].topics[].topics[].label
​D13.7.1 Filtering by Exception level and
Security state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D13.7.1 Filtering by Exception level and
Security state

# topic.topics[].topics[].topics[].topics[].label
​D13.7.2 Filtering by SVE Streaming
mode

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D13.7.2 Filtering by SVE Streaming
mode

# topic.topics[].topics[].topics[].topics[].label
​D13.7.4 Pseudocode description of event
filtering

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D13.7.4 Pseudocode description of event
filtering

# topic.topics[].topics[].topics[].label
​D13.8 Event threshold and edge
counting

# topic.topics[].topics[].topics[].anchors[].title
​D13.8 Event threshold and edge
counting

# topic.topics[].topics[].topics[].label
​D13.10 Performance Monitors and Debug
state

# topic.topics[].topics[].topics[].anchors[].title
​D13.10 Performance Monitors and Debug
state

# topic.topics[].topics[].topics[].topics[].label
​D13.11.2 Cycle and instruction
counters

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D13.11.2 Cycle and instruction
counters

# topic.topics[].topics[].topics[].label
​D13.12 Performance Monitors Extension
registers

# topic.topics[].topics[].topics[].anchors[].title
​D13.12 Performance Monitors Extension
registers

# topic.topics[].topics[].anchors[].title
​Chapter D13 The Performance Monitors
Extension

# topic.topics[].topics[].topics[].topics[].label
​D14.1.3 Counting events from shared
components

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D14.1.3 Counting events from shared
components

# topic.topics[].topics[].topics[].topics[].label
​D14.1.4 Tracking the Guarded Control Stack
data accesses

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D14.1.4 Tracking the Guarded Control Stack
data accesses

# topic.topics[].topics[].topics[].topics[].label
​D14.1.5 Counting exceptions taken locally
or not taken locally

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D14.1.5 Counting exceptions taken locally
or not taken locally

# topic.topics[].topics[].topics[].label
​D14.2 The PMU event number space and common
events

# topic.topics[].topics[].topics[].anchors[].title
​D14.2 The PMU event number space and common
events

# topic.topics[].topics[].topics[].topics[].label
​0x0000, SW_INCR, Instruction
architecturally executed, Condition code check pass, software
increment

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0000, SW_INCR, Instruction
architecturally executed, Condition code check pass, software
increment

# topic.topics[].topics[].topics[].topics[].label
​0x0006, LD_RETIRED, Instruction
architecturally executed, Condition code check pass, load

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0006, LD_RETIRED, Instruction
architecturally executed, Condition code check pass, load

# topic.topics[].topics[].topics[].topics[].label
​0x0007, ST_RETIRED, Instruction
architecturally executed, Condition code check pass, store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0007, ST_RETIRED, Instruction
architecturally executed, Condition code check pass, store

# topic.topics[].topics[].topics[].topics[].label
​0x000A, EXC_RETURN, Instruction
architecturally executed, Condition code check pass, exception
return

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x000A, EXC_RETURN, Instruction
architecturally executed, Condition code check pass, exception
return

# topic.topics[].topics[].topics[].topics[].label
​0x000B, CID_WRITE_RETIRED,
Instruction architecturally executed, Condition code check pass, write
to CONTEXTIDR

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x000B, CID_WRITE_RETIRED,
Instruction architecturally executed, Condition code check pass, write
to CONTEXTIDR

# topic.topics[].topics[].topics[].topics[].label
​0x000C, PC_WRITE_RETIRED,
Instruction architecturally executed, Condition code check pass,
Software change of the PC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x000C, PC_WRITE_RETIRED,
Instruction architecturally executed, Condition code check pass,
Software change of the PC

# topic.topics[].topics[].topics[].topics[].label
​0x000E, BR_RETURN_RETIRED,
Branch instruction architecturally executed, procedure return,
taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x000E, BR_RETURN_RETIRED,
Branch instruction architecturally executed, procedure return,
taken

# topic.topics[].topics[].topics[].topics[].label
​0x000F,
UNALIGNED_LDST_RETIRED, Instruction architecturally executed, Condition
code check pass, unaligned load or store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x000F,
UNALIGNED_LDST_RETIRED, Instruction architecturally executed, Condition
code check pass, unaligned load or store

# topic.topics[].topics[].topics[].topics[].label
​0x001C,
TTBR_WRITE_RETIRED, Instruction architecturally executed, Condition code
check pass, write to TTBR

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x001C,
TTBR_WRITE_RETIRED, Instruction architecturally executed, Condition code
check pass, write to TTBR

# topic.topics[].topics[].topics[].topics[].label
​0x001E, CHAIN, Chain a pair of event
counters

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x001E, CHAIN, Chain a pair of event
counters

# topic.topics[].topics[].topics[].topics[].label
​0x0081, EXC_UNDEF, Exception
taken, other synchronous

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0081, EXC_UNDEF, Exception
taken, other synchronous

# topic.topics[].topics[].topics[].topics[].label
​0x0082, EXC_SVC, Exception taken,
Supervisor Call

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0082, EXC_SVC, Exception taken,
Supervisor Call

# topic.topics[].topics[].topics[].topics[].label
​0x0083, EXC_PABORT, Exception
taken, Instruction Abort

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0083, EXC_PABORT, Exception
taken, Instruction Abort

# topic.topics[].topics[].topics[].topics[].label
​0x0084, EXC_DABORT, Exception
taken, Data Abort or SError

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0084, EXC_DABORT, Exception
taken, Data Abort or SError

# topic.topics[].topics[].topics[].topics[].label
​0x0088, EXC_SMC, Exception taken,
Secure Monitor Call

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0088, EXC_SMC, Exception taken,
Secure Monitor Call

# topic.topics[].topics[].topics[].topics[].label
​0x008A, EXC_HVC, Exception taken,
Hypervisor Call

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x008A, EXC_HVC, Exception taken,
Hypervisor Call

# topic.topics[].topics[].topics[].topics[].label
​0x008B, EXC_TRAP_PABORT,
Exception taken, Instruction Abort not Taken locally

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x008B, EXC_TRAP_PABORT,
Exception taken, Instruction Abort not Taken locally

# topic.topics[].topics[].topics[].topics[].label
​0x008C, EXC_TRAP_DABORT,
Exception taken, Data Abort or SError not Taken locally

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x008C, EXC_TRAP_DABORT,
Exception taken, Data Abort or SError not Taken locally

# topic.topics[].topics[].topics[].topics[].label
​0x008D, EXC_TRAP_OTHER,
Exception taken, other traps not Taken locally

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x008D, EXC_TRAP_OTHER,
Exception taken, other traps not Taken locally

# topic.topics[].topics[].topics[].topics[].label
​0x008E, EXC_TRAP_IRQ, Exception
taken, IRQ not Taken locally

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x008E, EXC_TRAP_IRQ, Exception
taken, IRQ not Taken locally

# topic.topics[].topics[].topics[].topics[].label
​0x008F, EXC_TRAP_FIQ, Exception
taken, FIQ not Taken locally

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x008F, EXC_TRAP_FIQ, Exception
taken, FIQ not Taken locally

# topic.topics[].topics[].topics[].topics[].label
​0x400C, TRB_WRAP, Trace buffer
current write pointer wrapped

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x400C, TRB_WRAP, Trace buffer
current write pointer wrapped

# topic.topics[].topics[].topics[].topics[].label
​0x400D, PMU_OVFS, PMU overflow,
counters accessible to EL1 and EL0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x400D, PMU_OVFS, PMU overflow,
counters accessible to EL1 and EL0

# topic.topics[].topics[].topics[].topics[].label
​0x400E, TRB_TRIG, Trace buffer
Trigger Event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x400E, TRB_TRIG, Trace buffer
Trigger Event

# topic.topics[].topics[].topics[].topics[].label
​0x400F, PMU_HOVFS, PMU overflow,
counters reserved for use by EL2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x400F, PMU_HOVFS, PMU overflow,
counters reserved for use by EL2

# topic.topics[].topics[].topics[].topics[].label
​0x8003,
ASE_SVE_INST_RETIRED, Instruction architecturally executed, Advanced
SIMD or SVE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8003,
ASE_SVE_INST_RETIRED, Instruction architecturally executed, Advanced
SIMD or SVE

# topic.topics[].topics[].topics[].topics[].label
​0x8107, BR_SKIP_RETIRED,
Branch instruction architecturally executed, not taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8107, BR_SKIP_RETIRED,
Branch instruction architecturally executed, not taken

# topic.topics[].topics[].topics[].topics[].label
​0x810B,
BR_IND_SKIP_RETIRED, Branch instruction architecturally executed,
indirect, not taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x810B,
BR_IND_SKIP_RETIRED, Branch instruction architecturally executed,
indirect, not taken

# topic.topics[].topics[].topics[].topics[].label
​0x810C,
BR_INDNR_TAKEN_RETIRED, Branch instruction architecturally executed,
indirect excluding procedure return, taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x810C,
BR_INDNR_TAKEN_RETIRED, Branch instruction architecturally executed,
indirect excluding procedure return, taken

# topic.topics[].topics[].topics[].topics[].label
​0x810D,
BR_INDNR_SKIP_RETIRED, Branch instruction architecturally executed,
indirect excluding procedure return, not taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x810D,
BR_INDNR_SKIP_RETIRED, Branch instruction architecturally executed,
indirect excluding procedure return, not taken

# topic.topics[].topics[].topics[].topics[].label
​0x810F,
BR_RETURN_SKIP_RETIRED, Branch instruction architecturally executed,
procedure return, not taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x810F,
BR_RETURN_SKIP_RETIRED, Branch instruction architecturally executed,
procedure return, not taken

# topic.topics[].topics[].topics[].topics[].label
​0x811E, BR_INDNR_RETIRED,
Branch instruction architecturally executed, indirect excluding
procedure return

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x811E, BR_INDNR_RETIRED,
Branch instruction architecturally executed, indirect excluding
procedure return

# topic.topics[].topics[].topics[].topics[].label
​0x811F, BRB_FILTRATE, Branch
Record captured

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x811F, BRB_FILTRATE, Branch
Record captured

# topic.topics[].topics[].topics[].topics[].label
​0x8179,
BRNL_INDNR_TAKEN_RETIRED, Branch instruction architecturally executed,
indirect branch without link excluding procedure return, taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8179,
BRNL_INDNR_TAKEN_RETIRED, Branch instruction architecturally executed,
indirect branch without link excluding procedure return, taken

# topic.topics[].topics[].topics[].topics[].label
​0x817A, BL_TAKEN_RETIRED,
Branch instruction architecturally executed, branch with link,
taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x817A, BL_TAKEN_RETIRED,
Branch instruction architecturally executed, branch with link,
taken

# topic.topics[].topics[].topics[].topics[].label
​0x817B,
BRNL_TAKEN_RETIRED, Branch instruction architecturally executed, branch
without link, taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x817B,
BRNL_TAKEN_RETIRED, Branch instruction architecturally executed, branch
without link, taken

# topic.topics[].topics[].topics[].topics[].label
​0x817C,
BL_IND_TAKEN_RETIRED, Branch instruction architecturally executed,
indirect branch with link, taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x817C,
BL_IND_TAKEN_RETIRED, Branch instruction architecturally executed,
indirect branch with link, taken

# topic.topics[].topics[].topics[].topics[].label
​0x817D,
BRNL_IND_TAKEN_RETIRED, Branch instruction architecturally executed,
indirect branch without link, taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x817D,
BRNL_IND_TAKEN_RETIRED, Branch instruction architecturally executed,
indirect branch without link, taken

# topic.topics[].topics[].topics[].topics[].label
​0x817E,
BL_IMMED_TAKEN_RETIRED, Branch instruction architecturally executed,
direct branch with link, taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x817E,
BL_IMMED_TAKEN_RETIRED, Branch instruction architecturally executed,
direct branch with link, taken

# topic.topics[].topics[].topics[].topics[].label
​0x817F,
BRNL_IMMED_TAKEN_RETIRED, Branch instruction architecturally executed,
direct branch without link, taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x817F,
BRNL_IMMED_TAKEN_RETIRED, Branch instruction architecturally executed,
direct branch without link, taken

# topic.topics[].topics[].topics[].topics[].label
​0x82A4, ASE_SVE_RETIRED,
Instruction architecturally executed, Advanced SIMD data processing or
SVE data processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82A4, ASE_SVE_RETIRED,
Instruction architecturally executed, Advanced SIMD data processing or
SVE data processing

# topic.topics[].topics[].topics[].topics[].label
​0x82AA, LDST_ANY_RETIRED,
Instruction architecturally executed, load or store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82AA, LDST_ANY_RETIRED,
Instruction architecturally executed, load or store

# topic.topics[].topics[].topics[].topics[].label
​0x82AB, DP_RETIRED, Instruction
architecturally executed, integer data processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82AB, DP_RETIRED, Instruction
architecturally executed, integer data processing

# topic.topics[].topics[].topics[].topics[].label
​0x82AC, ASE_RETIRED, Instruction
architecturally executed, Advanced SIMD data processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82AC, ASE_RETIRED, Instruction
architecturally executed, Advanced SIMD data processing

# topic.topics[].topics[].topics[].topics[].label
​0x82AE, SVE_RETIRED, Instruction
architecturally executed, SVE data processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82AE, SVE_RETIRED, Instruction
architecturally executed, SVE data processing

# topic.topics[].topics[].topics[].topics[].label
​0x8358, SME_RETIRED, Instruction
architecturally executed, SME data processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8358, SME_RETIRED, Instruction
architecturally executed, SME data processing

# topic.topics[].topics[].topics[].topics[].label
​0x8359, SE_RETIRED, Instruction
architecturally executed, Advanced SIMD, SVE, or SME data
processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8359, SE_RETIRED, Instruction
architecturally executed, Advanced SIMD, SVE, or SME data
processing

# topic.topics[].topics[].topics[].topics[].label
​0x835B, SE_INST_RETIRED,
Instruction architecturally executed, Advanced SIMD, SVE, or
SME

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x835B, SE_INST_RETIRED,
Instruction architecturally executed, Advanced SIMD, SVE, or
SME

# topic.topics[].topics[].topics[].topics[].label
​0x0001, L1I_CACHE_REFILL,
Level 1 instruction cache refill

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0001, L1I_CACHE_REFILL,
Level 1 instruction cache refill

# topic.topics[].topics[].topics[].topics[].label
​0x0002, L1I_TLB_REFILL, Level
1 instruction TLB refill

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0002, L1I_TLB_REFILL, Level
1 instruction TLB refill

# topic.topics[].topics[].topics[].topics[].label
​0x0003, L1D_CACHE_REFILL,
Level 1 data cache refill

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0003, L1D_CACHE_REFILL,
Level 1 data cache refill

# topic.topics[].topics[].topics[].topics[].label
​0x0004, L1D_CACHE, Level 1 data
cache access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0004, L1D_CACHE, Level 1 data
cache access

# topic.topics[].topics[].topics[].topics[].label
​0x0005, L1D_TLB_REFILL, Level
1 data TLB refill

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0005, L1D_TLB_REFILL, Level
1 data TLB refill

# topic.topics[].topics[].topics[].topics[].label
​0x0010, BR_MIS_PRED, Branch
instruction speculatively executed, mispredicted or not
predicted

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0010, BR_MIS_PRED, Branch
instruction speculatively executed, mispredicted or not
predicted

# topic.topics[].topics[].topics[].topics[].label
​0x0012, BR_PRED, Predictable branch
instruction speculatively executed

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0012, BR_PRED, Predictable branch
instruction speculatively executed

# topic.topics[].topics[].topics[].topics[].label
​0x0014, L1I_CACHE, Level 1
instruction cache access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0014, L1I_CACHE, Level 1
instruction cache access

# topic.topics[].topics[].topics[].topics[].label
​0x0015, L1D_CACHE_WB, Level 1
data cache write-back

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0015, L1D_CACHE_WB, Level 1
data cache write-back

# topic.topics[].topics[].topics[].topics[].label
​0x0016, L2D_CACHE, Level 2 data
cache access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0016, L2D_CACHE, Level 2 data
cache access

# topic.topics[].topics[].topics[].topics[].label
​0x0017, L2D_CACHE_REFILL,
Level 2 data cache refill

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0017, L2D_CACHE_REFILL,
Level 2 data cache refill

# topic.topics[].topics[].topics[].topics[].label
​0x0018, L2D_CACHE_WB, Level 2
data cache write-back

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0018, L2D_CACHE_WB, Level 2
data cache write-back

# topic.topics[].topics[].topics[].topics[].label
​0x001A, MEMORY_ERROR, Local
memory error

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x001A, MEMORY_ERROR, Local
memory error

# topic.topics[].topics[].topics[].topics[].label
​0x001F,
L1D_CACHE_ALLOCATE, Level 1 data cache allocation without
refill

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x001F,
L1D_CACHE_ALLOCATE, Level 1 data cache allocation without
refill

# topic.topics[].topics[].topics[].topics[].label
​0x0020,
L2D_CACHE_ALLOCATE, Level 2 data cache allocation without
refill

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0020,
L2D_CACHE_ALLOCATE, Level 2 data cache allocation without
refill

# topic.topics[].topics[].topics[].topics[].label
​0x0023, STALL_FRONTEND, No
operation sent for execution due to the frontend

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0023, STALL_FRONTEND, No
operation sent for execution due to the frontend

# topic.topics[].topics[].topics[].topics[].label
​0x0024, STALL_BACKEND, No
operation sent for execution due to the backend

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0024, STALL_BACKEND, No
operation sent for execution due to the backend

# topic.topics[].topics[].topics[].topics[].label
​0x0025, L1D_TLB, Level 1 data TLB
access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0025, L1D_TLB, Level 1 data TLB
access

# topic.topics[].topics[].topics[].topics[].label
​0x0026, L1I_TLB, Level 1 instruction
TLB access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0026, L1I_TLB, Level 1 instruction
TLB access

# topic.topics[].topics[].topics[].topics[].label
​0x0027, L2I_CACHE, Level 2
instruction cache access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0027, L2I_CACHE, Level 2
instruction cache access

# topic.topics[].topics[].topics[].topics[].label
​0x0028, L2I_CACHE_REFILL,
Level 2 instruction cache refill

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0028, L2I_CACHE_REFILL,
Level 2 instruction cache refill

# topic.topics[].topics[].topics[].topics[].label
​0x0029,
L3D_CACHE_ALLOCATE, Level 3 data cache allocation without
refill

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0029,
L3D_CACHE_ALLOCATE, Level 3 data cache allocation without
refill

# topic.topics[].topics[].topics[].topics[].label
​0x002A, L3D_CACHE_REFILL,
Level 3 data cache refill

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x002A, L3D_CACHE_REFILL,
Level 3 data cache refill

# topic.topics[].topics[].topics[].topics[].label
​0x002B, L3D_CACHE, Level 3 data
cache access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x002B, L3D_CACHE, Level 3 data
cache access

# topic.topics[].topics[].topics[].topics[].label
​0x002C, L3D_CACHE_WB, Level 3
data cache write-back

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x002C, L3D_CACHE_WB, Level 3
data cache write-back

# topic.topics[].topics[].topics[].topics[].label
​0x002D, L2D_TLB_REFILL, Level
2 data TLB refill

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x002D, L2D_TLB_REFILL, Level
2 data TLB refill

# topic.topics[].topics[].topics[].topics[].label
​0x002E, L2I_TLB_REFILL, Level
2 instruction TLB refill

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x002E, L2I_TLB_REFILL, Level
2 instruction TLB refill

# topic.topics[].topics[].topics[].topics[].label
​0x002F, L2D_TLB, Level 2 data TLB
access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x002F, L2D_TLB, Level 2 data TLB
access

# topic.topics[].topics[].topics[].topics[].label
​0x0030, L2I_TLB, Level 2 instruction
TLB access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0030, L2I_TLB, Level 2 instruction
TLB access

# topic.topics[].topics[].topics[].topics[].label
​0x0031, REMOTE_ACCESS, Access
to a remote device

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0031, REMOTE_ACCESS, Access
to a remote device

# topic.topics[].topics[].topics[].topics[].label
​0x0032, LL_CACHE, Last level cache
access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0032, LL_CACHE, Last level cache
access

# topic.topics[].topics[].topics[].topics[].label
​0x0033, LL_CACHE_MISS, Last
level cache miss

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0033, LL_CACHE_MISS, Last
level cache miss

# topic.topics[].topics[].topics[].topics[].label
​0x0034, DTLB_WALK, Data TLB access
with at least one translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0034, DTLB_WALK, Data TLB access
with at least one translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x0035, ITLB_WALK, Instruction TLB
access with at least one translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0035, ITLB_WALK, Instruction TLB
access with at least one translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x0036, LL_CACHE_RD, Last level
cache access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0036, LL_CACHE_RD, Last level
cache access, read

# topic.topics[].topics[].topics[].topics[].label
​0x0037, LL_CACHE_MISS_RD,
Last level cache miss, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0037, LL_CACHE_MISS_RD,
Last level cache miss, read

# topic.topics[].topics[].topics[].topics[].label
​0x0038, REMOTE_ACCESS_RD,
Access to a remote device, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0038, REMOTE_ACCESS_RD,
Access to a remote device, read

# topic.topics[].topics[].topics[].topics[].label
​0x0039,
L1D_CACHE_LMISS_RD, Level 1 data cache long-latency read miss

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0039,
L1D_CACHE_LMISS_RD, Level 1 data cache long-latency read miss

# topic.topics[].topics[].topics[].topics[].label
​0x003C, STALL, No operation sent for
execution

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x003C, STALL, No operation sent for
execution

# topic.topics[].topics[].topics[].topics[].label
​0x003D,
STALL_SLOT_BACKEND, No operation sent for execution on a Slot due to the
backend

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x003D,
STALL_SLOT_BACKEND, No operation sent for execution on a Slot due to the
backend

# topic.topics[].topics[].topics[].topics[].label
​0x003E,
STALL_SLOT_FRONTEND, No operation sent for execution on a Slot due to
the frontend

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x003E,
STALL_SLOT_FRONTEND, No operation sent for execution on a Slot due to
the frontend

# topic.topics[].topics[].topics[].topics[].label
​0x003F, STALL_SLOT, No operation
sent for execution on a Slot

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x003F, STALL_SLOT, No operation
sent for execution on a Slot

# topic.topics[].topics[].topics[].topics[].label
​0x0040, L1D_CACHE_RD, Level 1
data cache access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0040, L1D_CACHE_RD, Level 1
data cache access, read

# topic.topics[].topics[].topics[].topics[].label
​0x0041, L1D_CACHE_WR, Level 1
data cache access, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0041, L1D_CACHE_WR, Level 1
data cache access, write

# topic.topics[].topics[].topics[].topics[].label
​0x0042,
L1D_CACHE_REFILL_RD, Level 1 data cache refill, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0042,
L1D_CACHE_REFILL_RD, Level 1 data cache refill, read

# topic.topics[].topics[].topics[].topics[].label
​0x0043,
L1D_CACHE_REFILL_WR, Level 1 data cache refill, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0043,
L1D_CACHE_REFILL_WR, Level 1 data cache refill, write

# topic.topics[].topics[].topics[].topics[].label
​0x0044,
L1D_CACHE_REFILL_INNER, Level 1 data cache refill, inner

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0044,
L1D_CACHE_REFILL_INNER, Level 1 data cache refill, inner

# topic.topics[].topics[].topics[].topics[].label
​0x0045,
L1D_CACHE_REFILL_OUTER, Level 1 data cache refill, outer

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0045,
L1D_CACHE_REFILL_OUTER, Level 1 data cache refill, outer

# topic.topics[].topics[].topics[].topics[].label
​0x0046,
L1D_CACHE_WB_VICTIM, Level 1 data cache write-back, victim

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0046,
L1D_CACHE_WB_VICTIM, Level 1 data cache write-back, victim

# topic.topics[].topics[].topics[].topics[].label
​0x0047,
L1D_CACHE_WB_CLEAN, Level 1 data cache write-back, cleaning and
coherency

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0047,
L1D_CACHE_WB_CLEAN, Level 1 data cache write-back, cleaning and
coherency

# topic.topics[].topics[].topics[].topics[].label
​0x0048, L1D_CACHE_INVAL,
Level 1 data cache invalidate

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0048, L1D_CACHE_INVAL,
Level 1 data cache invalidate

# topic.topics[].topics[].topics[].topics[].label
​0x004C, L1D_TLB_REFILL_RD,
Level 1 data TLB refill, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x004C, L1D_TLB_REFILL_RD,
Level 1 data TLB refill, read

# topic.topics[].topics[].topics[].topics[].label
​0x004D, L1D_TLB_REFILL_WR,
Level 1 data TLB refill, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x004D, L1D_TLB_REFILL_WR,
Level 1 data TLB refill, write

# topic.topics[].topics[].topics[].topics[].label
​0x004E, L1D_TLB_RD, Level 1 data
TLB access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x004E, L1D_TLB_RD, Level 1 data
TLB access, read

# topic.topics[].topics[].topics[].topics[].label
​0x004F, L1D_TLB_WR, Level 1 data
TLB access, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x004F, L1D_TLB_WR, Level 1 data
TLB access, write

# topic.topics[].topics[].topics[].topics[].label
​0x0050, L2D_CACHE_RD, Level 2
data cache access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0050, L2D_CACHE_RD, Level 2
data cache access, read

# topic.topics[].topics[].topics[].topics[].label
​0x0051, L2D_CACHE_WR, Level 2
data cache access, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0051, L2D_CACHE_WR, Level 2
data cache access, write

# topic.topics[].topics[].topics[].topics[].label
​0x0052,
L2D_CACHE_REFILL_RD, Level 2 data cache refill, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0052,
L2D_CACHE_REFILL_RD, Level 2 data cache refill, read

# topic.topics[].topics[].topics[].topics[].label
​0x0053,
L2D_CACHE_REFILL_WR, Level 2 data cache refill, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0053,
L2D_CACHE_REFILL_WR, Level 2 data cache refill, write

# topic.topics[].topics[].topics[].topics[].label
​0x0056,
L2D_CACHE_WB_VICTIM, Level 2 data cache write-back, victim

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0056,
L2D_CACHE_WB_VICTIM, Level 2 data cache write-back, victim

# topic.topics[].topics[].topics[].topics[].label
​0x0057,
L2D_CACHE_WB_CLEAN, Level 2 data cache write-back, cleaning and
coherency

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0057,
L2D_CACHE_WB_CLEAN, Level 2 data cache write-back, cleaning and
coherency

# topic.topics[].topics[].topics[].topics[].label
​0x0058, L2D_CACHE_INVAL,
Level 2 data cache invalidate

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0058, L2D_CACHE_INVAL,
Level 2 data cache invalidate

# topic.topics[].topics[].topics[].topics[].label
​0x005C, L2D_TLB_REFILL_RD,
Level 2 data TLB refill, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x005C, L2D_TLB_REFILL_RD,
Level 2 data TLB refill, read

# topic.topics[].topics[].topics[].topics[].label
​0x005D, L2D_TLB_REFILL_WR,
Level 2 data TLB refill, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x005D, L2D_TLB_REFILL_WR,
Level 2 data TLB refill, write

# topic.topics[].topics[].topics[].topics[].label
​0x005E, L2D_TLB_RD, Level 2 data
TLB access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x005E, L2D_TLB_RD, Level 2 data
TLB access, read

# topic.topics[].topics[].topics[].topics[].label
​0x005F, L2D_TLB_WR, Level 2 data
TLB access, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x005F, L2D_TLB_WR, Level 2 data
TLB access, write

# topic.topics[].topics[].topics[].topics[].label
​0x0060, BUS_ACCESS_RD, Bus
access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0060, BUS_ACCESS_RD, Bus
access, read

# topic.topics[].topics[].topics[].topics[].label
​0x0061, BUS_ACCESS_WR, Bus
access, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0061, BUS_ACCESS_WR, Bus
access, write

# topic.topics[].topics[].topics[].topics[].label
​0x0062, BUS_ACCESS_SHARED,
Bus access, Normal, Cacheable, Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0062, BUS_ACCESS_SHARED,
Bus access, Normal, Cacheable, Shareable

# topic.topics[].topics[].topics[].topics[].label
​0x0063,
BUS_ACCESS_NOT_SHARED, Bus access, not Normal, Cacheable,
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0063,
BUS_ACCESS_NOT_SHARED, Bus access, not Normal, Cacheable,
Shareable

# topic.topics[].topics[].topics[].topics[].label
​0x0064, BUS_ACCESS_NORMAL,
Bus access, normal

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0064, BUS_ACCESS_NORMAL,
Bus access, normal

# topic.topics[].topics[].topics[].topics[].label
​0x0066, MEM_ACCESS_RD, Data
memory access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0066, MEM_ACCESS_RD, Data
memory access, read

# topic.topics[].topics[].topics[].topics[].label
​0x0067, MEM_ACCESS_WR, Data
memory access, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0067, MEM_ACCESS_WR, Data
memory access, write

# topic.topics[].topics[].topics[].topics[].label
​0x0070, LD_SPEC, Operation
speculatively executed, load

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0070, LD_SPEC, Operation
speculatively executed, load

# topic.topics[].topics[].topics[].topics[].label
​0x0071, ST_SPEC, Operation
speculatively executed, store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0071, ST_SPEC, Operation
speculatively executed, store

# topic.topics[].topics[].topics[].topics[].label
​0x0072, LDST_SPEC, Operation
speculatively executed, load or store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0072, LDST_SPEC, Operation
speculatively executed, load or store

# topic.topics[].topics[].topics[].topics[].label
​0x0073, DP_SPEC, Operation
speculatively executed, integer data processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0073, DP_SPEC, Operation
speculatively executed, integer data processing

# topic.topics[].topics[].topics[].topics[].label
​0x0074, ASE_SPEC, Operation
speculatively executed, Advanced SIMD data processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0074, ASE_SPEC, Operation
speculatively executed, Advanced SIMD data processing

# topic.topics[].topics[].topics[].topics[].label
​0x0075, VFP_SPEC, Operation
speculatively executed, scalar floating-point data processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0075, VFP_SPEC, Operation
speculatively executed, scalar floating-point data processing

# topic.topics[].topics[].topics[].topics[].label
​0x0076, PC_WRITE_SPEC,
Operation speculatively executed, Software change of the PC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0076, PC_WRITE_SPEC,
Operation speculatively executed, Software change of the PC

# topic.topics[].topics[].topics[].topics[].label
​0x0078, BR_IMMED_SPEC, Branch
speculatively executed, immediate branch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0078, BR_IMMED_SPEC, Branch
speculatively executed, immediate branch

# topic.topics[].topics[].topics[].topics[].label
​0x0079, BR_RETURN_SPEC,
Branch speculatively executed, procedure return

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0079, BR_RETURN_SPEC,
Branch speculatively executed, procedure return

# topic.topics[].topics[].topics[].topics[].label
​0x007C, ISB_SPEC, Barrier
speculatively executed, ISB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x007C, ISB_SPEC, Barrier
speculatively executed, ISB

# topic.topics[].topics[].topics[].topics[].label
​0x007D, DSB_SPEC, Barrier
speculatively executed, DSB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x007D, DSB_SPEC, Barrier
speculatively executed, DSB

# topic.topics[].topics[].topics[].topics[].label
​0x007E, DMB_SPEC, Barrier
speculatively executed, DMB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x007E, DMB_SPEC, Barrier
speculatively executed, DMB

# topic.topics[].topics[].topics[].topics[].label
​0x007F, CSDB_SPEC, Barrier
speculatively executed, CSDB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x007F, CSDB_SPEC, Barrier
speculatively executed, CSDB

# topic.topics[].topics[].topics[].topics[].label
​0x0092,
L3D_CACHE_HIT_WR_FEXT_PROP, Level 3 data cache demand access first hit,
write, fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x0092,
L3D_CACHE_HIT_WR_FEXT_PROP, Level 3 data cache demand access first hit,
write, fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].label
​0x00A0, L3D_CACHE_RD, Level 3
data cache access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00A0, L3D_CACHE_RD, Level 3
data cache access, read

# topic.topics[].topics[].topics[].topics[].label
​0x00A1, L3D_CACHE_WR, Level 3
data cache access, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00A1, L3D_CACHE_WR, Level 3
data cache access, write

# topic.topics[].topics[].topics[].topics[].label
​0x00A2,
L3D_CACHE_REFILL_RD, Level 3 data cache refill, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00A2,
L3D_CACHE_REFILL_RD, Level 3 data cache refill, read

# topic.topics[].topics[].topics[].topics[].label
​0x00A3,
L3D_CACHE_REFILL_WR, Level 3 data cache refill, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00A3,
L3D_CACHE_REFILL_WR, Level 3 data cache refill, write

# topic.topics[].topics[].topics[].topics[].label
​0x00A6,
L3D_CACHE_WB_VICTIM, Level 3 data cache write-back, victim

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00A6,
L3D_CACHE_WB_VICTIM, Level 3 data cache write-back, victim

# topic.topics[].topics[].topics[].topics[].label
​0x00A7,
L3D_CACHE_WB_CLEAN, Level 3 data cache write-back, cleaning and
coherency

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00A7,
L3D_CACHE_WB_CLEAN, Level 3 data cache write-back, cleaning and
coherency

# topic.topics[].topics[].topics[].topics[].label
​0x00A8, L3D_CACHE_INVAL,
Level 3 data cache invalidate

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00A8, L3D_CACHE_INVAL,
Level 3 data cache invalidate

# topic.topics[].topics[].topics[].topics[].label
​0x00A9,
L2D_CACHE_HIT_RD_FEXT_PROP, Level 2 data cache demand access first hit,
read, fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00A9,
L2D_CACHE_HIT_RD_FEXT_PROP, Level 2 data cache demand access first hit,
read, fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].label
​0x00AA,
L2D_CACHE_HIT_WR_FEXT_PROP, Level 2 data cache demand access first hit,
write, fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00AA,
L2D_CACHE_HIT_WR_FEXT_PROP, Level 2 data cache demand access first hit,
write, fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].label
​0x00AB,
L2D_CACHE_HIT_RW_FEXT_PROP, Level 2 data cache demand access first hit,
fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00AB,
L2D_CACHE_HIT_RW_FEXT_PROP, Level 2 data cache demand access first hit,
fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].label
​0x00AC,
L3D_CACHE_EXT_PROP, Level 3 data cache allocation due to external
propagating transaction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00AC,
L3D_CACHE_EXT_PROP, Level 3 data cache allocation due to external
propagating transaction

# topic.topics[].topics[].topics[].topics[].label
​0x00AD,
L3D_CACHE_EXT_PROP_PRFM_IR, Level 3 data cache allocation due to
external propagating transaction after prefetch with intent to
read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00AD,
L3D_CACHE_EXT_PROP_PRFM_IR, Level 3 data cache allocation due to
external propagating transaction after prefetch with intent to
read

# topic.topics[].topics[].topics[].topics[].label
​0x00AE,
L3D_CACHE_HIT_RW_FEXT_PROP, Level 3 data cache demand access first hit,
fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00AE,
L3D_CACHE_HIT_RW_FEXT_PROP, Level 3 data cache demand access first hit,
fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].label
​0x00AF,
L3D_CACHE_HIT_RD_FEXT_PROP, Level 3 data cache demand access first hit,
read, fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00AF,
L3D_CACHE_HIT_RD_FEXT_PROP, Level 3 data cache demand access first hit,
read, fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].label
​0x00B0, STSHH_SPEC, Store shared
hint instruction speculatively executed

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00B0, STSHH_SPEC, Store shared
hint instruction speculatively executed

# topic.topics[].topics[].topics[].topics[].label
​0x00B1, STSHH_KEEP_SPEC,
Store shared hint instruction speculatively executed with KEEP
policy

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00B1, STSHH_KEEP_SPEC,
Store shared hint instruction speculatively executed with KEEP
policy

# topic.topics[].topics[].topics[].topics[].label
​0x00B2, STSHH_STRM_SPEC,
Store shared hint instruction speculatively executed with STRM
policy

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00B2, STSHH_STRM_SPEC,
Store shared hint instruction speculatively executed with STRM
policy

# topic.topics[].topics[].topics[].topics[].label
​0x00B3, PRFM_IR_SPEC, Prefetch
with intent to read instruction speculatively executed

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00B3, PRFM_IR_SPEC, Prefetch
with intent to read instruction speculatively executed

# topic.topics[].topics[].topics[].topics[].label
​0x00B4,
MEM_ACCESS_WR_STSHH, Memory write with store shared hint

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00B4,
MEM_ACCESS_WR_STSHH, Memory write with store shared hint

# topic.topics[].topics[].topics[].topics[].label
​0x00B5,
MEM_ACCESS_WR_STSHH_KEEP, Memory write with store shared hint with keep
policy

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00B5,
MEM_ACCESS_WR_STSHH_KEEP, Memory write with store shared hint with keep
policy

# topic.topics[].topics[].topics[].topics[].label
​0x00B6,
MEM_ACCESS_WR_STSHH_STRM, Memory write with store shared hint with
stream policy

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00B6,
MEM_ACCESS_WR_STSHH_STRM, Memory write with store shared hint with
stream policy

# topic.topics[].topics[].topics[].topics[].label
​0x00B7,
MEM_ACCESS_WR_STSHH_KEEP_NEAR, Memory write with store shared hint with
keep policy performed near

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00B7,
MEM_ACCESS_WR_STSHH_KEEP_NEAR, Memory write with store shared hint with
keep policy performed near

# topic.topics[].topics[].topics[].topics[].label
​0x00B8,
MEM_ACCESS_WR_STSHH_KEEP_FAR, Memory write with store shared hint with
keep policy performed far

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00B8,
MEM_ACCESS_WR_STSHH_KEEP_FAR, Memory write with store shared hint with
keep policy performed far

# topic.topics[].topics[].topics[].topics[].label
​0x00B9,
L1D_CACHE_EXT_PROP, Level 1 data cache allocation due to external
propagating transaction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00B9,
L1D_CACHE_EXT_PROP, Level 1 data cache allocation due to external
propagating transaction

# topic.topics[].topics[].topics[].topics[].label
​0x00BA,
L1D_CACHE_EXT_PROP_PRFM_IR, Level 1 data cache allocation due to
external propagating transaction after prefetch with intent to
read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00BA,
L1D_CACHE_EXT_PROP_PRFM_IR, Level 1 data cache allocation due to
external propagating transaction after prefetch with intent to
read

# topic.topics[].topics[].topics[].topics[].label
​0x00BB,
L1D_CACHE_HIT_RD_FEXT_PROP, Level 1 data cache demand access first hit,
read, fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00BB,
L1D_CACHE_HIT_RD_FEXT_PROP, Level 1 data cache demand access first hit,
read, fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].label
​0x00BC,
L1D_CACHE_HIT_WR_FEXT_PROP, Level 1 data cache demand access first hit,
write, fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00BC,
L1D_CACHE_HIT_WR_FEXT_PROP, Level 1 data cache demand access first hit,
write, fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].label
​0x00BD,
L1D_CACHE_HIT_RW_FEXT_PROP, Level 1 data cache demand access first hit,
fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00BD,
L1D_CACHE_HIT_RW_FEXT_PROP, Level 1 data cache demand access first hit,
fetched by external propagating transaction

# topic.topics[].topics[].topics[].topics[].label
​0x00BE,
L2D_CACHE_EXT_PROP, Level 2 data cache allocation due to external
propagating transaction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00BE,
L2D_CACHE_EXT_PROP, Level 2 data cache allocation due to external
propagating transaction

# topic.topics[].topics[].topics[].topics[].label
​0x00BF,
L2D_CACHE_EXT_PROP_PRFM_IR, Level 2 data cache allocation due to
external propagating transaction after prefetch with intent to
read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x00BF,
L2D_CACHE_EXT_PROP_PRFM_IR, Level 2 data cache allocation due to
external propagating transaction after prefetch with intent to
read

# topic.topics[].topics[].topics[].topics[].label
​0x4000, SAMPLE_POP, Statistical
Profiling sample population

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4000, SAMPLE_POP, Statistical
Profiling sample population

# topic.topics[].topics[].topics[].topics[].label
​0x4001, SAMPLE_FEED, Statistical
Profiling sample taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4001, SAMPLE_FEED, Statistical
Profiling sample taken

# topic.topics[].topics[].topics[].topics[].label
​0x4002, SAMPLE_FILTRATE,
Statistical Profiling sample taken and not removed by filtering

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4002, SAMPLE_FILTRATE,
Statistical Profiling sample taken and not removed by filtering

# topic.topics[].topics[].topics[].topics[].label
​0x4003, SAMPLE_COLLISION,
Statistical Profiling sample collided with previous sample

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4003, SAMPLE_COLLISION,
Statistical Profiling sample collided with previous sample

# topic.topics[].topics[].topics[].topics[].label
​0x4004, CNT_CYCLES, Constant
frequency cycles

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4004, CNT_CYCLES, Constant
frequency cycles

# topic.topics[].topics[].topics[].topics[].label
​0x4005, STALL_BACKEND_MEM,
Memory stall cycles

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4005, STALL_BACKEND_MEM,
Memory stall cycles

# topic.topics[].topics[].topics[].topics[].label
​0x4006, L1I_CACHE_LMISS,
Level 1 instruction cache long-latency miss

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4006, L1I_CACHE_LMISS,
Level 1 instruction cache long-latency miss

# topic.topics[].topics[].topics[].topics[].label
​0x4009,
L2D_CACHE_LMISS_RD, Level 2 data cache long-latency read miss

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4009,
L2D_CACHE_LMISS_RD, Level 2 data cache long-latency read miss

# topic.topics[].topics[].topics[].topics[].label
​0x400A, L2I_CACHE_LMISS,
Level 2 instruction cache long-latency miss

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x400A, L2I_CACHE_LMISS,
Level 2 instruction cache long-latency miss

# topic.topics[].topics[].topics[].topics[].label
​0x400B,
L3D_CACHE_LMISS_RD, Level 3 data cache long-latency read miss

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x400B,
L3D_CACHE_LMISS_RD, Level 3 data cache long-latency read miss

# topic.topics[].topics[].topics[].topics[].label
​0x4010, TRCEXTOUT0, Trace unit
external output 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4010, TRCEXTOUT0, Trace unit
external output 0

# topic.topics[].topics[].topics[].topics[].label
​0x4011, TRCEXTOUT1, Trace unit
external output 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4011, TRCEXTOUT1, Trace unit
external output 1

# topic.topics[].topics[].topics[].topics[].label
​0x4012, TRCEXTOUT2, Trace unit
external output 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4012, TRCEXTOUT2, Trace unit
external output 2

# topic.topics[].topics[].topics[].topics[].label
​0x4013, TRCEXTOUT3, Trace unit
external output 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4013, TRCEXTOUT3, Trace unit
external output 3

# topic.topics[].topics[].topics[].topics[].label
​0x4018, CTI_TRIGOUT4,
Cross-trigger Interface output trigger 4

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4018, CTI_TRIGOUT4,
Cross-trigger Interface output trigger 4

# topic.topics[].topics[].topics[].topics[].label
​0x4019, CTI_TRIGOUT5,
Cross-trigger Interface output trigger 5

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4019, CTI_TRIGOUT5,
Cross-trigger Interface output trigger 5

# topic.topics[].topics[].topics[].topics[].label
​0x401A, CTI_TRIGOUT6,
Cross-trigger Interface output trigger 6

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x401A, CTI_TRIGOUT6,
Cross-trigger Interface output trigger 6

# topic.topics[].topics[].topics[].topics[].label
​0x401B, CTI_TRIGOUT7,
Cross-trigger Interface output trigger 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x401B, CTI_TRIGOUT7,
Cross-trigger Interface output trigger 7

# topic.topics[].topics[].topics[].topics[].label
​0x4020, LDST_ALIGN_LAT,
Access with additional latency from alignment

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4020, LDST_ALIGN_LAT,
Access with additional latency from alignment

# topic.topics[].topics[].topics[].topics[].label
​0x4021, LD_ALIGN_LAT, Load with
additional latency from alignment

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4021, LD_ALIGN_LAT, Load with
additional latency from alignment

# topic.topics[].topics[].topics[].topics[].label
​0x4022, ST_ALIGN_LAT, Store
with additional latency from alignment

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4022, ST_ALIGN_LAT, Store
with additional latency from alignment

# topic.topics[].topics[].topics[].topics[].label
​0x4024,
MEM_ACCESS_CHECKED, Checked data memory access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4024,
MEM_ACCESS_CHECKED, Checked data memory access

# topic.topics[].topics[].topics[].topics[].label
​0x4025,
MEM_ACCESS_CHECKED_RD, Checked data memory access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4025,
MEM_ACCESS_CHECKED_RD, Checked data memory access, read

# topic.topics[].topics[].topics[].topics[].label
​0x4026,
MEM_ACCESS_CHECKED_WR, Checked data memory access, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x4026,
MEM_ACCESS_CHECKED_WR, Checked data memory access, write

# topic.topics[].topics[].topics[].topics[].label
​0x8005, ASE_INST_SPEC,
Operation speculatively executed, Advanced SIMD

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8005, ASE_INST_SPEC,
Operation speculatively executed, Advanced SIMD

# topic.topics[].topics[].topics[].topics[].label
​0x8007, ASE_SVE_INST_SPEC,
Operation speculatively executed, Advanced SIMD or SVE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8007, ASE_SVE_INST_SPEC,
Operation speculatively executed, Advanced SIMD or SVE

# topic.topics[].topics[].topics[].topics[].label
​0x800B, ASE_SVE_UOP_SPEC,
Microarchitectural operation speculatively executed, Advanced SIMD or
SVE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x800B, ASE_SVE_UOP_SPEC,
Microarchitectural operation speculatively executed, Advanced SIMD or
SVE

# topic.topics[].topics[].topics[].topics[].label
​0x800E, SVE_MATH_SPEC,
Operation speculatively executed, SVE math accelerator

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x800E, SVE_MATH_SPEC,
Operation speculatively executed, SVE math accelerator

# topic.topics[].topics[].topics[].topics[].label
​0x8010, FP_SPEC, Floating-point
operation speculatively executed, including SIMD

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8010, FP_SPEC, Floating-point
operation speculatively executed, including SIMD

# topic.topics[].topics[].topics[].topics[].label
​0x8011, ASE_FP_SPEC,
Floating-point operation speculatively executed, Advanced SIMD

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8011, ASE_FP_SPEC,
Floating-point operation speculatively executed, Advanced SIMD

# topic.topics[].topics[].topics[].topics[].label
​0x8013, ASE_SVE_FP_SPEC,
Floating-point operation speculatively executed, Advanced SIMD or
SVE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8013, ASE_SVE_FP_SPEC,
Floating-point operation speculatively executed, Advanced SIMD or
SVE

# topic.topics[].topics[].topics[].topics[].label
​0x8017,
ASE_SVE_FP_HP_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE half-precision

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8017,
ASE_SVE_FP_HP_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE half-precision

# topic.topics[].topics[].topics[].topics[].label
​0x801B,
ASE_SVE_FP_SP_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE single-precision, data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x801B,
ASE_SVE_FP_SP_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE single-precision, data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x801F,
ASE_SVE_FP_DP_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE double-precision, data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x801F,
ASE_SVE_FP_DP_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE double-precision, data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x8021, ASE_FP_DIV_SPEC,
Floating-point operation speculatively executed, Advanced SIMD
divide

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8021, ASE_FP_DIV_SPEC,
Floating-point operation speculatively executed, Advanced SIMD
divide

# topic.topics[].topics[].topics[].topics[].label
​0x8023,
ASE_SVE_FP_DIV_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE divide

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8023,
ASE_SVE_FP_DIV_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE divide

# topic.topics[].topics[].topics[].topics[].label
​0x8024, FP_SQRT_SPEC,
Floating-point operation speculatively executed, square root

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8024, FP_SQRT_SPEC,
Floating-point operation speculatively executed, square root

# topic.topics[].topics[].topics[].topics[].label
​0x8025, ASE_FP_SQRT_SPEC,
Floating-point operation speculatively executed, Advanced SIMD square
root

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8025, ASE_FP_SQRT_SPEC,
Floating-point operation speculatively executed, Advanced SIMD square
root

# topic.topics[].topics[].topics[].topics[].label
​0x8026, SVE_FP_SQRT_SPEC,
Floating-point operation speculatively executed, SVE square
root

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8026, SVE_FP_SQRT_SPEC,
Floating-point operation speculatively executed, SVE square
root

# topic.topics[].topics[].topics[].topics[].label
​0x8027,
ASE_SVE_FP_SQRT_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE square-root

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8027,
ASE_SVE_FP_SQRT_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE square-root

# topic.topics[].topics[].topics[].topics[].label
​0x8029, ASE_FP_FMA_SPEC,
Floating-point operation speculatively executed, Advanced SIMD
FMA

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8029, ASE_FP_FMA_SPEC,
Floating-point operation speculatively executed, Advanced SIMD
FMA

# topic.topics[].topics[].topics[].topics[].label
​0x802A, SVE_FP_FMA_SPEC,
Floating-point operation speculatively executed, SVE FMA

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x802A, SVE_FP_FMA_SPEC,
Floating-point operation speculatively executed, SVE FMA

# topic.topics[].topics[].topics[].topics[].label
​0x802B,
ASE_SVE_FP_FMA_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE FMA

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x802B,
ASE_SVE_FP_FMA_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE FMA

# topic.topics[].topics[].topics[].topics[].label
​0x802F,
ASE_SVE_FP_MUL_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE multiply

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x802F,
ASE_SVE_FP_MUL_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE multiply

# topic.topics[].topics[].topics[].topics[].label
​0x8030, FP_ADDSUB_SPEC,
Floating-point operation speculatively executed, add or
subtract

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8030, FP_ADDSUB_SPEC,
Floating-point operation speculatively executed, add or
subtract

# topic.topics[].topics[].topics[].topics[].label
​0x8031,
ASE_FP_ADDSUB_SPEC, Floating-point operation speculatively executed,
Advanced SIMD add or subtract

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8031,
ASE_FP_ADDSUB_SPEC, Floating-point operation speculatively executed,
Advanced SIMD add or subtract

# topic.topics[].topics[].topics[].topics[].label
​0x8032,
SVE_FP_ADDSUB_SPEC, Floating-point operation speculatively executed, SVE
add or subtract

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8032,
SVE_FP_ADDSUB_SPEC, Floating-point operation speculatively executed, SVE
add or subtract

# topic.topics[].topics[].topics[].topics[].label
​0x8033,
ASE_SVE_FP_ADDSUB_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE add or subtract

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8033,
ASE_SVE_FP_ADDSUB_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE add or subtract

# topic.topics[].topics[].topics[].topics[].label
​0x8037,
ASE_SVE_FP_RECPE_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE reciprocal estimate

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8037,
ASE_SVE_FP_RECPE_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE reciprocal estimate

# topic.topics[].topics[].topics[].topics[].label
​0x8039, ASE_FP_CVT_SPEC,
Floating-point operation speculatively executed, Advanced SIMD
convert

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8039, ASE_FP_CVT_SPEC,
Floating-point operation speculatively executed, Advanced SIMD
convert

# topic.topics[].topics[].topics[].topics[].label
​0x803B,
ASE_SVE_FP_CVT_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE convert

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x803B,
ASE_SVE_FP_CVT_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE convert

# topic.topics[].topics[].topics[].topics[].label
​0x803D,
ASE_FP_PREDUCE_SPEC, Floating-point operation speculatively executed,
Advanced SIMD pairwise add step or pairwise reduce step

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x803D,
ASE_FP_PREDUCE_SPEC, Floating-point operation speculatively executed,
Advanced SIMD pairwise add step or pairwise reduce step

# topic.topics[].topics[].topics[].topics[].label
​0x803E,
SVE_FP_VREDUCE_SPEC, Floating-point operation speculatively executed,
SVE pairwise or reduction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x803E,
SVE_FP_VREDUCE_SPEC, Floating-point operation speculatively executed,
SVE pairwise or reduction

# topic.topics[].topics[].topics[].topics[].label
​0x803F,
ASE_SVE_FP_VREDUCE_SPEC, Floating-point operation speculatively
executed, Advanced SIMD or SVE vector reduction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x803F,
ASE_SVE_FP_VREDUCE_SPEC, Floating-point operation speculatively
executed, Advanced SIMD or SVE vector reduction

# topic.topics[].topics[].topics[].topics[].label
​0x8040, INT_SPEC, Integer operation
speculatively executed

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8040, INT_SPEC, Integer operation
speculatively executed

# topic.topics[].topics[].topics[].topics[].label
​0x8041, ASE_INT_SPEC, Integer
operation speculatively executed, Advanced SIMD

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8041, ASE_INT_SPEC, Integer
operation speculatively executed, Advanced SIMD

# topic.topics[].topics[].topics[].topics[].label
​0x8042, SVE_INT_SPEC, Integer
operation speculatively executed, SVE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8042, SVE_INT_SPEC, Integer
operation speculatively executed, SVE

# topic.topics[].topics[].topics[].topics[].label
​0x8043, ASE_SVE_INT_SPEC,
Integer operation speculatively executed, Advanced SIMD or SVE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8043, ASE_SVE_INT_SPEC,
Integer operation speculatively executed, Advanced SIMD or SVE

# topic.topics[].topics[].topics[].topics[].label
​0x8044, INT_DIV_SPEC, Integer
operation speculatively executed, divide

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8044, INT_DIV_SPEC, Integer
operation speculatively executed, divide

# topic.topics[].topics[].topics[].topics[].label
​0x8045, INT_DIV64_SPEC,
Integer operation speculatively executed, 64-bit divide

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8045, INT_DIV64_SPEC,
Integer operation speculatively executed, 64-bit divide

# topic.topics[].topics[].topics[].topics[].label
​0x8046, SVE_INT_DIV_SPEC,
Integer operation speculatively executed, SVE divide

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8046, SVE_INT_DIV_SPEC,
Integer operation speculatively executed, SVE divide

# topic.topics[].topics[].topics[].topics[].label
​0x8047,
SVE_INT_DIV64_SPEC, Integer operation speculatively executed, SVE 64-bit
divide

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8047,
SVE_INT_DIV64_SPEC, Integer operation speculatively executed, SVE 64-bit
divide

# topic.topics[].topics[].topics[].topics[].label
​0x8049, ASE_INT_MUL_SPEC,
Integer operation speculatively executed, Advanced SIMD
multiply

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8049, ASE_INT_MUL_SPEC,
Integer operation speculatively executed, Advanced SIMD
multiply

# topic.topics[].topics[].topics[].topics[].label
​0x804A, SVE_INT_MUL_SPEC,
Integer operation speculatively executed, SVE multiply

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x804A, SVE_INT_MUL_SPEC,
Integer operation speculatively executed, SVE multiply

# topic.topics[].topics[].topics[].topics[].label
​0x804B,
ASE_SVE_INT_MUL_SPEC, Integer operation speculatively executed, Advanced
SIMD or SVE multiply

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x804B,
ASE_SVE_INT_MUL_SPEC, Integer operation speculatively executed, Advanced
SIMD or SVE multiply

# topic.topics[].topics[].topics[].topics[].label
​0x804C, INT_MUL64_SPEC,
Integer operation speculatively executed, 64×64 multiply

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x804C, INT_MUL64_SPEC,
Integer operation speculatively executed, 64×64 multiply

# topic.topics[].topics[].topics[].topics[].label
​0x804D,
SVE_INT_MUL64_SPEC, Integer operation speculatively executed, SVE 64×64
multiply

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x804D,
SVE_INT_MUL64_SPEC, Integer operation speculatively executed, SVE 64×64
multiply

# topic.topics[].topics[].topics[].topics[].label
​0x804E, INT_MULH64_SPEC,
Integer operation speculatively executed, 64×64 multiply returning high
part

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x804E, INT_MULH64_SPEC,
Integer operation speculatively executed, 64×64 multiply returning high
part

# topic.topics[].topics[].topics[].topics[].label
​0x804F,
SVE_INT_MULH64_SPEC, Integer operation speculatively executed, SVE 64×64
multiply high part

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x804F,
SVE_INT_MULH64_SPEC, Integer operation speculatively executed, SVE 64×64
multiply high part

# topic.topics[].topics[].topics[].topics[].label
​0x8053,
ASE_SVE_FP_BF16_SPEC, Floating-point operation speculatively executed,
SVE or Advanced SIMD BFloat16, data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8053,
ASE_SVE_FP_BF16_SPEC, Floating-point operation speculatively executed,
SVE or Advanced SIMD BFloat16, data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x8056, SVE_SPEC, Operation
speculatively executed, SVE data processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8056, SVE_SPEC, Operation
speculatively executed, SVE data processing

# topic.topics[].topics[].topics[].topics[].label
​0x8057, ASE_SVE_SPEC, Operation
speculatively executed, Advanced SIMD data processing or SVE data
processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8057, ASE_SVE_SPEC, Operation
speculatively executed, Advanced SIMD data processing or SVE data
processing

# topic.topics[].topics[].topics[].topics[].label
​0x805B,
ASE_SVE_NONFP_SPEC, Non-floating-point operation speculatively executed,
Advanced SIMD or SVE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x805B,
ASE_SVE_NONFP_SPEC, Non-floating-point operation speculatively executed,
Advanced SIMD or SVE

# topic.topics[].topics[].topics[].topics[].label
​0x805D,
ASE_INT_VREDUCE_SPEC, Integer operation speculatively executed, Advanced
SIMD reduction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x805D,
ASE_INT_VREDUCE_SPEC, Integer operation speculatively executed, Advanced
SIMD reduction

# topic.topics[].topics[].topics[].topics[].label
​0x805F,
ASE_SVE_INT_VREDUCE_SPEC, Integer operation speculatively executed,
Advanced SIMD or SVE reduction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x805F,
ASE_SVE_INT_VREDUCE_SPEC, Integer operation speculatively executed,
Advanced SIMD or SVE reduction

# topic.topics[].topics[].topics[].topics[].label
​0x8060, SVE_PERM_SPEC,
Operation speculatively executed, SVE permute

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8060, SVE_PERM_SPEC,
Operation speculatively executed, SVE permute

# topic.topics[].topics[].topics[].topics[].label
​0x8065,
SVE_XPIPE_Z2R_SPEC, Operation speculatively executed, SVE vector to
scalar cross-pipe

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8065,
SVE_XPIPE_Z2R_SPEC, Operation speculatively executed, SVE vector to
scalar cross-pipe

# topic.topics[].topics[].topics[].topics[].label
​0x8066,
SVE_XPIPE_R2Z_SPEC, Operation speculatively executed, SVE scalar to
vector cross-pipe

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8066,
SVE_XPIPE_R2Z_SPEC, Operation speculatively executed, SVE scalar to
vector cross-pipe

# topic.topics[].topics[].topics[].topics[].label
​0x8068, SVE_PGEN_SPEC,
Operation speculatively executed, SVE predicate generating

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8068, SVE_PGEN_SPEC,
Operation speculatively executed, SVE predicate generating

# topic.topics[].topics[].topics[].topics[].label
​0x8069, SVE_PGEN_FLG_SPEC,
Operation speculatively executed, SVE predicate flag setting

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8069, SVE_PGEN_FLG_SPEC,
Operation speculatively executed, SVE predicate flag setting

# topic.topics[].topics[].topics[].topics[].label
​0x806A, SVE_PGEN_CMP_SPEC,
Operation speculatively executed, SVE vector compare

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x806A, SVE_PGEN_CMP_SPEC,
Operation speculatively executed, SVE vector compare

# topic.topics[].topics[].topics[].topics[].label
​0x806B, SVE_PGEN_FCM_SPEC,
Floating-point operation speculatively executed, SVE vector
compare

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x806B, SVE_PGEN_FCM_SPEC,
Floating-point operation speculatively executed, SVE vector
compare

# topic.topics[].topics[].topics[].topics[].label
​0x806D, SVE_PPERM_SPEC,
Operation speculatively executed, SVE predicate permute

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x806D, SVE_PPERM_SPEC,
Operation speculatively executed, SVE predicate permute

# topic.topics[].topics[].topics[].topics[].label
​0x806E, SVE_PSCAN_SPEC,
Operation speculatively executed, SVE predicate scan

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x806E, SVE_PSCAN_SPEC,
Operation speculatively executed, SVE predicate scan

# topic.topics[].topics[].topics[].topics[].label
​0x806F, SVE_PCNT_SPEC,
Operation speculatively executed, SVE predicate count

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x806F, SVE_PCNT_SPEC,
Operation speculatively executed, SVE predicate count

# topic.topics[].topics[].topics[].topics[].label
​0x8070,
SVE_PLOOP_WHILE_SPEC, Operation speculatively executed, SVE predicate
loop while

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8070,
SVE_PLOOP_WHILE_SPEC, Operation speculatively executed, SVE predicate
loop while

# topic.topics[].topics[].topics[].topics[].label
​0x8071,
SVE_PLOOP_TEST_SPEC, Operation speculatively executed, SVE predicate
loop test

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8071,
SVE_PLOOP_TEST_SPEC, Operation speculatively executed, SVE predicate
loop test

# topic.topics[].topics[].topics[].topics[].label
​0x8072,
SVE_PLOOP_ELTS_SPEC, Operation speculatively executed, SVE predicate
loop elements

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8072,
SVE_PLOOP_ELTS_SPEC, Operation speculatively executed, SVE predicate
loop elements

# topic.topics[].topics[].topics[].topics[].label
​0x8073,
SVE_PLOOP_TERM_SPEC, Operation speculatively executed, SVE predicate
loop termination

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8073,
SVE_PLOOP_TERM_SPEC, Operation speculatively executed, SVE predicate
loop termination

# topic.topics[].topics[].topics[].topics[].label
​0x8075,
SVE_PRED_EMPTY_SPEC, Operation speculatively executed, SIMD predicated
with no active elements

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8075,
SVE_PRED_EMPTY_SPEC, Operation speculatively executed, SIMD predicated
with no active elements

# topic.topics[].topics[].topics[].topics[].label
​0x8076,
SVE_PRED_FULL_SPEC, Operation speculatively executed, SIMD predicated
with all active elements

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8076,
SVE_PRED_FULL_SPEC, Operation speculatively executed, SIMD predicated
with all active elements

# topic.topics[].topics[].topics[].topics[].label
​0x8077,
SVE_PRED_PARTIAL_SPEC, Operation speculatively executed, SIMD predicated
with partially active elements

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8077,
SVE_PRED_PARTIAL_SPEC, Operation speculatively executed, SIMD predicated
with partially active elements

# topic.topics[].topics[].topics[].topics[].label
​0x8079,
SVE_PRED_NOT_FULL_SPEC, Operation speculatively executed, SVE predicated
with at least one inactive element

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8079,
SVE_PRED_NOT_FULL_SPEC, Operation speculatively executed, SVE predicated
with at least one inactive element

# topic.topics[].topics[].topics[].topics[].label
​0x807C, SVE_MOVPRFX_SPEC,
Operation speculatively executed, SVE MOVPRFX

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x807C, SVE_MOVPRFX_SPEC,
Operation speculatively executed, SVE MOVPRFX

# topic.topics[].topics[].topics[].topics[].label
​0x807D,
SVE_MOVPRFX_Z_SPEC, Operation speculatively executed, SVE MOVPRFX
zeroing predication

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x807D,
SVE_MOVPRFX_Z_SPEC, Operation speculatively executed, SVE MOVPRFX
zeroing predication

# topic.topics[].topics[].topics[].topics[].label
​0x807E,
SVE_MOVPRFX_M_SPEC, Operation speculatively executed, SVE MOVPRFX
merging predication

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x807E,
SVE_MOVPRFX_M_SPEC, Operation speculatively executed, SVE MOVPRFX
merging predication

# topic.topics[].topics[].topics[].topics[].label
​0x807F,
SVE_MOVPRFX_U_SPEC, Operation speculatively executed, SVE MOVPRFX
unfused

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x807F,
SVE_MOVPRFX_U_SPEC, Operation speculatively executed, SVE MOVPRFX
unfused

# topic.topics[].topics[].topics[].topics[].label
​0x8080, SVE_LDST_SPEC,
Operation speculatively executed, SVE load, store, or prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8080, SVE_LDST_SPEC,
Operation speculatively executed, SVE load, store, or prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8081, SVE_LD_SPEC, Operation
speculatively executed, SVE load

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8081, SVE_LD_SPEC, Operation
speculatively executed, SVE load

# topic.topics[].topics[].topics[].topics[].label
​0x8082, SVE_ST_SPEC, Operation
speculatively executed, SVE store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8082, SVE_ST_SPEC, Operation
speculatively executed, SVE store

# topic.topics[].topics[].topics[].topics[].label
​0x8083, SVE_PRF_SPEC, Operation
speculatively executed, SVE prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8083, SVE_PRF_SPEC, Operation
speculatively executed, SVE prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8084, ASE_SVE_LDST_SPEC,
Operation speculatively executed, Advanced SIMD or SVE load or
store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8084, ASE_SVE_LDST_SPEC,
Operation speculatively executed, Advanced SIMD or SVE load or
store

# topic.topics[].topics[].topics[].topics[].label
​0x8085, ASE_SVE_LD_SPEC,
Operation speculatively executed, Advanced SIMD or SVE load

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8085, ASE_SVE_LD_SPEC,
Operation speculatively executed, Advanced SIMD or SVE load

# topic.topics[].topics[].topics[].topics[].label
​0x8086, ASE_SVE_ST_SPEC,
Operation speculatively executed, Advanced SIMD or SVE store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8086, ASE_SVE_ST_SPEC,
Operation speculatively executed, Advanced SIMD or SVE store

# topic.topics[].topics[].topics[].topics[].label
​0x8088,
BASE_LDST_REG_SPEC, Operation speculatively executed, general-purpose
register load, store, or prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8088,
BASE_LDST_REG_SPEC, Operation speculatively executed, general-purpose
register load, store, or prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x808C,
FPASE_LDST_REG_SPEC, Operation speculatively executed, SIMD&FP
register load or store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x808C,
FPASE_LDST_REG_SPEC, Operation speculatively executed, SIMD&FP
register load or store

# topic.topics[].topics[].topics[].topics[].label
​0x808D, FPASE_LD_REG_SPEC,
Operation speculatively executed, SIMD&FP register load

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x808D, FPASE_LD_REG_SPEC,
Operation speculatively executed, SIMD&FP register load

# topic.topics[].topics[].topics[].topics[].label
​0x808E, FPASE_ST_REG_SPEC,
Operation speculatively executed, SIMD&FP register store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x808E, FPASE_ST_REG_SPEC,
Operation speculatively executed, SIMD&FP register store

# topic.topics[].topics[].topics[].topics[].label
​0x8090, SVE_LDST_REG_SPEC,
Operation speculatively executed, SVE unpredicated load or store
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8090, SVE_LDST_REG_SPEC,
Operation speculatively executed, SVE unpredicated load or store
register

# topic.topics[].topics[].topics[].topics[].label
​0x8091, SVE_LDR_REG_SPEC,
Operation speculatively executed, SVE unpredicated load
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8091, SVE_LDR_REG_SPEC,
Operation speculatively executed, SVE unpredicated load
register

# topic.topics[].topics[].topics[].topics[].label
​0x8092, SVE_STR_REG_SPEC,
Operation speculatively executed, SVE unpredicated store
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8092, SVE_STR_REG_SPEC,
Operation speculatively executed, SVE unpredicated store
register

# topic.topics[].topics[].topics[].topics[].label
​0x8094,
SVE_LDST_PREG_SPEC, Operation speculatively executed, SVE load or store
predicate register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8094,
SVE_LDST_PREG_SPEC, Operation speculatively executed, SVE load or store
predicate register

# topic.topics[].topics[].topics[].topics[].label
​0x8095, SVE_LDR_PREG_SPEC,
Operation speculatively executed, SVE load predicate register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8095, SVE_LDR_PREG_SPEC,
Operation speculatively executed, SVE load predicate register

# topic.topics[].topics[].topics[].topics[].label
​0x8096, SVE_STR_PREG_SPEC,
Operation speculatively executed, SVE store predicate register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8096, SVE_STR_PREG_SPEC,
Operation speculatively executed, SVE store predicate register

# topic.topics[].topics[].topics[].topics[].label
​0x8098,
SVE_LDST_ZREG_SPEC, Operation speculatively executed, SVE load or store
vector register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8098,
SVE_LDST_ZREG_SPEC, Operation speculatively executed, SVE load or store
vector register

# topic.topics[].topics[].topics[].topics[].label
​0x8099, SVE_LDR_ZREG_SPEC,
Operation speculatively executed, SVE load vector register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8099, SVE_LDR_ZREG_SPEC,
Operation speculatively executed, SVE load vector register

# topic.topics[].topics[].topics[].topics[].label
​0x809A, SVE_STR_ZREG_SPEC,
Operation speculatively executed, SVE store vector register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x809A, SVE_STR_ZREG_SPEC,
Operation speculatively executed, SVE store vector register

# topic.topics[].topics[].topics[].topics[].label
​0x809C,
SVE_LDST_CONTIG_SPEC, Operation speculatively executed, SVE contiguous
load, store, or prefetch element

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x809C,
SVE_LDST_CONTIG_SPEC, Operation speculatively executed, SVE contiguous
load, store, or prefetch element

# topic.topics[].topics[].topics[].topics[].label
​0x809D,
SVE_LD_CONTIG_SPEC, Operation speculatively executed, SVE single vector
contiguous load element

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x809D,
SVE_LD_CONTIG_SPEC, Operation speculatively executed, SVE single vector
contiguous load element

# topic.topics[].topics[].topics[].topics[].label
​0x809E,
SVE_ST_CONTIG_SPEC, Operation speculatively executed, SVE contiguous
store element

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x809E,
SVE_ST_CONTIG_SPEC, Operation speculatively executed, SVE contiguous
store element

# topic.topics[].topics[].topics[].topics[].label
​0x809F,
SVE_PRF_CONTIG_SPEC, Operation speculatively executed, SVE contiguous
prefetch element

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x809F,
SVE_PRF_CONTIG_SPEC, Operation speculatively executed, SVE contiguous
prefetch element

# topic.topics[].topics[].topics[].topics[].label
​0x80A0,
SVE_LDSTNT_CONTIG_SPEC, Operation speculatively executed, SVE
non-temporal contiguous load or store element

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80A0,
SVE_LDSTNT_CONTIG_SPEC, Operation speculatively executed, SVE
non-temporal contiguous load or store element

# topic.topics[].topics[].topics[].topics[].label
​0x80A1,
SVE_LDNT_CONTIG_SPEC, Operation speculatively executed, SVE non-temporal
contiguous load element

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80A1,
SVE_LDNT_CONTIG_SPEC, Operation speculatively executed, SVE non-temporal
contiguous load element

# topic.topics[].topics[].topics[].topics[].label
​0x80A2,
SVE_STNT_CONTIG_SPEC, Operation speculatively executed, SVE non-temporal
contiguous store element

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80A2,
SVE_STNT_CONTIG_SPEC, Operation speculatively executed, SVE non-temporal
contiguous store element

# topic.topics[].topics[].topics[].topics[].label
​0x80A4,
ASE_SVE_LDST_MULTI_SPEC, Operation speculatively executed, Advanced SIMD
or SVE contiguous load or store multiple vector

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80A4,
ASE_SVE_LDST_MULTI_SPEC, Operation speculatively executed, Advanced SIMD
or SVE contiguous load or store multiple vector

# topic.topics[].topics[].topics[].topics[].label
​0x80A5,
ASE_SVE_LD_MULTI_SPEC, Operation speculatively executed, Advanced SIMD
or SVE contiguous load multiple vector

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80A5,
ASE_SVE_LD_MULTI_SPEC, Operation speculatively executed, Advanced SIMD
or SVE contiguous load multiple vector

# topic.topics[].topics[].topics[].topics[].label
​0x80A6,
ASE_SVE_ST_MULTI_SPEC, Operation speculatively executed, Advanced SIMD
or SVE contiguous store multiple vector

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80A6,
ASE_SVE_ST_MULTI_SPEC, Operation speculatively executed, Advanced SIMD
or SVE contiguous store multiple vector

# topic.topics[].topics[].topics[].topics[].label
​0x80A8,
SVE_LDST_MULTI_SPEC, Operation speculatively executed, SVE contiguous
load or store multiple vector

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80A8,
SVE_LDST_MULTI_SPEC, Operation speculatively executed, SVE contiguous
load or store multiple vector

# topic.topics[].topics[].topics[].topics[].label
​0x80A9, SVE_LD_MULTI_SPEC,
Operation speculatively executed, SVE contiguous load multiple
vector

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80A9, SVE_LD_MULTI_SPEC,
Operation speculatively executed, SVE contiguous load multiple
vector

# topic.topics[].topics[].topics[].topics[].label
​0x80AA, SVE_ST_MULTI_SPEC,
Operation speculatively executed, SVE contiguous store multiple
vector

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80AA, SVE_ST_MULTI_SPEC,
Operation speculatively executed, SVE contiguous store multiple
vector

# topic.topics[].topics[].topics[].topics[].label
​0x80AC,
SVE_LDST_NONCONTIG_SPEC, Operation speculatively executed, SVE
non-contiguous load, store, or prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80AC,
SVE_LDST_NONCONTIG_SPEC, Operation speculatively executed, SVE
non-contiguous load, store, or prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x80B0,
SVE_LDST64_NONCONTIG_SPEC, Operation speculatively executed, SVE 64-bit
non-contiguous load, store, or prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80B0,
SVE_LDST64_NONCONTIG_SPEC, Operation speculatively executed, SVE 64-bit
non-contiguous load, store, or prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x80B4,
ASE_SVE_UNALIGNED_LDST_SPEC, Advanced SIMD or SVE unaligned
access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80B4,
ASE_SVE_UNALIGNED_LDST_SPEC, Advanced SIMD or SVE unaligned
access

# topic.topics[].topics[].topics[].topics[].label
​0x80B5,
ASE_SVE_UNALIGNED_LD_SPEC, Advanced SIMD or SVE unaligned read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80B5,
ASE_SVE_UNALIGNED_LD_SPEC, Advanced SIMD or SVE unaligned read

# topic.topics[].topics[].topics[].topics[].label
​0x80B6,
ASE_SVE_UNALIGNED_ST_SPEC, Advanced SIMD or SVE unaligned write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80B6,
ASE_SVE_UNALIGNED_ST_SPEC, Advanced SIMD or SVE unaligned write

# topic.topics[].topics[].topics[].topics[].label
​0x80B8,
ASE_SVE_UNALIGNED_CONTIG_LDST_SPEC, Advanced SIMD or SVE unaligned
contiguous access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80B8,
ASE_SVE_UNALIGNED_CONTIG_LDST_SPEC, Advanced SIMD or SVE unaligned
contiguous access

# topic.topics[].topics[].topics[].topics[].label
​0x80B9,
ASE_SVE_UNALIGNED_CONTIG_LD_SPEC, Advanced SIMD or SVE unaligned
contiguous read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80B9,
ASE_SVE_UNALIGNED_CONTIG_LD_SPEC, Advanced SIMD or SVE unaligned
contiguous read

# topic.topics[].topics[].topics[].topics[].label
​0x80BA,
ASE_SVE_UNALIGNED_CONTIG_ST_SPEC, Advanced SIMD or SVE unaligned
contiguous write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80BA,
ASE_SVE_UNALIGNED_CONTIG_ST_SPEC, Advanced SIMD or SVE unaligned
contiguous write

# topic.topics[].topics[].topics[].topics[].label
​0x80BC, SVE_LDFF_SPEC,
Operation speculatively executed, SVE first-fault load

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80BC, SVE_LDFF_SPEC,
Operation speculatively executed, SVE first-fault load

# topic.topics[].topics[].topics[].topics[].label
​0x80BD,
SVE_LDFF_FAULT_SPEC, Operation speculatively executed, SVE first-fault
load which set FFR bit to 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80BD,
SVE_LDFF_FAULT_SPEC, Operation speculatively executed, SVE first-fault
load which set FFR bit to 0

# topic.topics[].topics[].topics[].topics[].label
​0x80C2,
FP_HP_SCALE_OPS_SPEC, Scalable element arithmetic operations
speculatively executed, largest type is half-precision
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80C2,
FP_HP_SCALE_OPS_SPEC, Scalable element arithmetic operations
speculatively executed, largest type is half-precision
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x80C3,
FP_HP_FIXED_OPS_SPEC, Non-scalable element arithmetic operations
speculatively executed, largest type is half-precision
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80C3,
FP_HP_FIXED_OPS_SPEC, Non-scalable element arithmetic operations
speculatively executed, largest type is half-precision
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x80C4,
FP_SP_SCALE_OPS_SPEC, Scalable element arithmetic operations
speculatively executed, largest type is single-precision
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80C4,
FP_SP_SCALE_OPS_SPEC, Scalable element arithmetic operations
speculatively executed, largest type is single-precision
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x80C6,
FP_DP_SCALE_OPS_SPEC, Scalable element arithmetic operations
speculatively executed, largest type is double-precision
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80C6,
FP_DP_SCALE_OPS_SPEC, Scalable element arithmetic operations
speculatively executed, largest type is double-precision
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x80CA,
LDST_SCALE_OPS_SPEC, Scalable load or store element operations
speculatively executed

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80CA,
LDST_SCALE_OPS_SPEC, Scalable load or store element operations
speculatively executed

# topic.topics[].topics[].topics[].topics[].label
​0x80CB,
LDST_FIXED_OPS_SPEC, Non-scalable load or store element operations
speculatively executed

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80CB,
LDST_FIXED_OPS_SPEC, Non-scalable load or store element operations
speculatively executed

# topic.topics[].topics[].topics[].topics[].label
​0x80CC, LD_SCALE_OPS_SPEC,
Scalable load element operations speculatively executed

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80CC, LD_SCALE_OPS_SPEC,
Scalable load element operations speculatively executed

# topic.topics[].topics[].topics[].topics[].label
​0x80CE, ST_SCALE_OPS_SPEC,
Scalable store element operations speculatively executed

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80CE, ST_SCALE_OPS_SPEC,
Scalable store element operations speculatively executed

# topic.topics[].topics[].topics[].topics[].label
​0x80D2,
FP_HP_SCALE2_OPS_SPEC, Scalable tile arithmetic operations speculatively
executed, largest type is half-precision floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80D2,
FP_HP_SCALE2_OPS_SPEC, Scalable tile arithmetic operations speculatively
executed, largest type is half-precision floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x80D3,
FP_BF16_SCALE2_OPS_SPEC, Scalable tile arithmetic operations
speculatively executed, largest type is BFloat16 floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80D3,
FP_BF16_SCALE2_OPS_SPEC, Scalable tile arithmetic operations
speculatively executed, largest type is BFloat16 floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x80D4,
FP_SP_SCALE2_OPS_SPEC, Scalable tile arithmetic operations speculatively
executed, largest type is single-precision floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80D4,
FP_SP_SCALE2_OPS_SPEC, Scalable tile arithmetic operations speculatively
executed, largest type is single-precision floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x80D6,
FP_DP_SCALE2_OPS_SPEC, Scalable tile arithmetic operations speculatively
executed, largest type is double-precision floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80D6,
FP_DP_SCALE2_OPS_SPEC, Scalable tile arithmetic operations speculatively
executed, largest type is double-precision floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x80DA,
LDST_SCALE_BYTES_SPEC, Scalable load and store bytes speculatively
executed

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80DA,
LDST_SCALE_BYTES_SPEC, Scalable load and store bytes speculatively
executed

# topic.topics[].topics[].topics[].topics[].label
​0x80DB,
LDST_FIXED_BYTES_SPEC, Non-scalable load and store bytes speculatively
executed

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80DB,
LDST_FIXED_BYTES_SPEC, Non-scalable load and store bytes speculatively
executed

# topic.topics[].topics[].topics[].topics[].label
​0x80DC,
LD_SCALE_BYTES_SPEC, Scalable load bytes speculatively executed

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80DC,
LD_SCALE_BYTES_SPEC, Scalable load bytes speculatively executed

# topic.topics[].topics[].topics[].topics[].label
​0x80E1, ASE_INT8_SPEC, Integer
operation speculatively executed, Advanced SIMD 8-bit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80E1, ASE_INT8_SPEC, Integer
operation speculatively executed, Advanced SIMD 8-bit

# topic.topics[].topics[].topics[].topics[].label
​0x80E2, SVE_INT8_SPEC, Integer
operation speculatively executed, SVE 8-bit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80E2, SVE_INT8_SPEC, Integer
operation speculatively executed, SVE 8-bit

# topic.topics[].topics[].topics[].topics[].label
​0x80E3, ASE_SVE_INT8_SPEC,
Integer operation speculatively executed, Advanced SIMD or SVE
8-bit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80E3, ASE_SVE_INT8_SPEC,
Integer operation speculatively executed, Advanced SIMD or SVE
8-bit

# topic.topics[].topics[].topics[].topics[].label
​0x80E5, ASE_INT16_SPEC,
Integer operation speculatively executed, Advanced SIMD 16-bit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80E5, ASE_INT16_SPEC,
Integer operation speculatively executed, Advanced SIMD 16-bit

# topic.topics[].topics[].topics[].topics[].label
​0x80E6, SVE_INT16_SPEC,
Integer operation speculatively executed, SVE 16-bit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80E6, SVE_INT16_SPEC,
Integer operation speculatively executed, SVE 16-bit

# topic.topics[].topics[].topics[].topics[].label
​0x80E7,
ASE_SVE_INT16_SPEC, Integer operation speculatively executed, Advanced
SIMD or SVE 16-bit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80E7,
ASE_SVE_INT16_SPEC, Integer operation speculatively executed, Advanced
SIMD or SVE 16-bit

# topic.topics[].topics[].topics[].topics[].label
​0x80E8,
FP_BF16_SCALE_OPS_SPEC, Scalable element arithmetic operations
speculatively executed, largest type is BFloat16 floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80E8,
FP_BF16_SCALE_OPS_SPEC, Scalable element arithmetic operations
speculatively executed, largest type is BFloat16 floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x80E9, ASE_INT32_SPEC,
Integer operation speculatively executed, Advanced SIMD 32-bit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80E9, ASE_INT32_SPEC,
Integer operation speculatively executed, Advanced SIMD 32-bit

# topic.topics[].topics[].topics[].topics[].label
​0x80EA, SVE_INT32_SPEC,
Integer operation speculatively executed, SVE 32-bit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80EA, SVE_INT32_SPEC,
Integer operation speculatively executed, SVE 32-bit

# topic.topics[].topics[].topics[].topics[].label
​0x80EB,
ASE_SVE_INT32_SPEC, Integer operation speculatively executed, Advanced
SIMD or SVE 32-bit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80EB,
ASE_SVE_INT32_SPEC, Integer operation speculatively executed, Advanced
SIMD or SVE 32-bit

# topic.topics[].topics[].topics[].topics[].label
​0x80ED, ASE_INT64_SPEC,
Integer operation speculatively executed, Advanced SIMD 64-bit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80ED, ASE_INT64_SPEC,
Integer operation speculatively executed, Advanced SIMD 64-bit

# topic.topics[].topics[].topics[].topics[].label
​0x80EE, SVE_INT64_SPEC,
Integer operation speculatively executed, SVE 64-bit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80EE, SVE_INT64_SPEC,
Integer operation speculatively executed, SVE 64-bit

# topic.topics[].topics[].topics[].topics[].label
​0x80EF,
ASE_SVE_INT64_SPEC, Integer operation speculatively executed, Advanced
SIMD or SVE 64-bit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80EF,
ASE_SVE_INT64_SPEC, Integer operation speculatively executed, Advanced
SIMD or SVE 64-bit

# topic.topics[].topics[].topics[].topics[].label
​0x80F3,
ASE_SVE_FP_DOT_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE dot-product

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80F3,
ASE_SVE_FP_DOT_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE dot-product

# topic.topics[].topics[].topics[].topics[].label
​0x80F5, ASE_FP_MMLA_SPEC,
Floating-point operation speculatively executed, Advanced SIMD matrix
multiply

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80F5, ASE_FP_MMLA_SPEC,
Floating-point operation speculatively executed, Advanced SIMD matrix
multiply

# topic.topics[].topics[].topics[].topics[].label
​0x80F6, SVE_FP_MMLA_SPEC,
Floating-point operation speculatively executed, SVE matrix
multiply

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80F6, SVE_FP_MMLA_SPEC,
Floating-point operation speculatively executed, SVE matrix
multiply

# topic.topics[].topics[].topics[].topics[].label
​0x80F7,
ASE_SVE_FP_MMLA_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE matrix multiply

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80F7,
ASE_SVE_FP_MMLA_SPEC, Floating-point operation speculatively executed,
Advanced SIMD or SVE matrix multiply

# topic.topics[].topics[].topics[].topics[].label
​0x80F9, ASE_INT_DOT_SPEC,
Operation speculatively executed, Advanced SIMD integer
dot-product

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80F9, ASE_INT_DOT_SPEC,
Operation speculatively executed, Advanced SIMD integer
dot-product

# topic.topics[].topics[].topics[].topics[].label
​0x80FA, SVE_INT_DOT_SPEC,
Integer operation speculatively executed, SVE dot-product

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80FA, SVE_INT_DOT_SPEC,
Integer operation speculatively executed, SVE dot-product

# topic.topics[].topics[].topics[].topics[].label
​0x80FB,
ASE_SVE_INT_DOT_SPEC, Integer operation speculatively executed, Advanced
SIMD or SVE dot-product

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80FB,
ASE_SVE_INT_DOT_SPEC, Integer operation speculatively executed, Advanced
SIMD or SVE dot-product

# topic.topics[].topics[].topics[].topics[].label
​0x80FD, ASE_INT_MMLA_SPEC,
Integer operation speculatively executed, Advanced SIMD matrix
multiply

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80FD, ASE_INT_MMLA_SPEC,
Integer operation speculatively executed, Advanced SIMD matrix
multiply

# topic.topics[].topics[].topics[].topics[].label
​0x80FE, SVE_INT_MMLA_SPEC,
Integer operation speculatively executed, SVE matrix multiply

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80FE, SVE_INT_MMLA_SPEC,
Integer operation speculatively executed, SVE matrix multiply

# topic.topics[].topics[].topics[].topics[].label
​0x80FF,
ASE_SVE_INT_MMLA_SPEC, Integer operation speculatively executed,
Advanced SIMD or SVE matrix multiply

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x80FF,
ASE_SVE_INT_MMLA_SPEC, Integer operation speculatively executed,
Advanced SIMD or SVE matrix multiply

# topic.topics[].topics[].topics[].topics[].label
​0x811A,
BR_SKIP_PRED_RETIRED, Branch instruction architecturally executed,
predicted branch, not taken

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x811A,
BR_SKIP_PRED_RETIRED, Branch instruction architecturally executed,
predicted branch, not taken

# topic.topics[].topics[].topics[].topics[].label
​0x8120, INST_FETCH_PERCYC,
Instruction fetches in progress

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8120, INST_FETCH_PERCYC,
Instruction fetches in progress

# topic.topics[].topics[].topics[].topics[].label
​0x8121,
MEM_ACCESS_RD_PERCYC, Data memory reads in progress

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8121,
MEM_ACCESS_RD_PERCYC, Data memory reads in progress

# topic.topics[].topics[].topics[].topics[].label
​0x8122, SAMPLE_FEED_DS,
Statistical Profiling sample taken, selected Data Source

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8122, SAMPLE_FEED_DS,
Statistical Profiling sample taken, selected Data Source

# topic.topics[].topics[].topics[].topics[].label
​0x8124, INST_FETCH, Instruction
memory access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8124, INST_FETCH, Instruction
memory access

# topic.topics[].topics[].topics[].topics[].label
​0x8125, BUS_REQ_RD_PERCYC,
Bus read transactions in progress

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8125, BUS_REQ_RD_PERCYC,
Bus read transactions in progress

# topic.topics[].topics[].topics[].topics[].label
​0x8126, BUS_REQ_WR_PERCYC,
Bus write transactions in progress

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8126, BUS_REQ_WR_PERCYC,
Bus write transactions in progress

# topic.topics[].topics[].topics[].topics[].label
​0x8127, PMU_SNAPSHOT,
Successful PMU capture event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8127, PMU_SNAPSHOT,
Successful PMU capture event

# topic.topics[].topics[].topics[].topics[].label
​0x8128, DTLB_WALK_PERCYC,
Data translation table walks in progress

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8128, DTLB_WALK_PERCYC,
Data translation table walks in progress

# topic.topics[].topics[].topics[].topics[].label
​0x8129, ITLB_WALK_PERCYC,
Instruction translation table walks in progress

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8129, ITLB_WALK_PERCYC,
Instruction translation table walks in progress

# topic.topics[].topics[].topics[].topics[].label
​0x812A, SAMPLE_FEED_BR,
Statistical Profiling sample taken, branch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x812A, SAMPLE_FEED_BR,
Statistical Profiling sample taken, branch

# topic.topics[].topics[].topics[].topics[].label
​0x812B, SAMPLE_FEED_LD,
Statistical Profiling sample taken, load

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x812B, SAMPLE_FEED_LD,
Statistical Profiling sample taken, load

# topic.topics[].topics[].topics[].topics[].label
​0x812C, SAMPLE_FEED_ST,
Statistical Profiling sample taken, store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x812C, SAMPLE_FEED_ST,
Statistical Profiling sample taken, store

# topic.topics[].topics[].topics[].topics[].label
​0x812D, SAMPLE_FEED_OP,
Statistical Profiling sample taken, matching type

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x812D, SAMPLE_FEED_OP,
Statistical Profiling sample taken, matching type

# topic.topics[].topics[].topics[].topics[].label
​0x812E, SAMPLE_FEED_EVENT,
Statistical Profiling sample taken, matching events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x812E, SAMPLE_FEED_EVENT,
Statistical Profiling sample taken, matching events

# topic.topics[].topics[].topics[].topics[].label
​0x812F, SAMPLE_FEED_LAT,
Statistical Profiling sample taken, exceeding minimum latency

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x812F, SAMPLE_FEED_LAT,
Statistical Profiling sample taken, exceeding minimum latency

# topic.topics[].topics[].topics[].topics[].label
​0x8130, L1D_TLB_RW, Level 1 data
TLB access, demand access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8130, L1D_TLB_RW, Level 1 data
TLB access, demand access

# topic.topics[].topics[].topics[].topics[].label
​0x8131, L1I_TLB_RD, Level 1
instruction TLB access, demand access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8131, L1I_TLB_RD, Level 1
instruction TLB access, demand access

# topic.topics[].topics[].topics[].topics[].label
​0x8132, L1D_TLB_PRFM, Level 1
data TLB access, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8132, L1D_TLB_PRFM, Level 1
data TLB access, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8133, L1I_TLB_PRFM, Level 1
instruction TLB access, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8133, L1I_TLB_PRFM, Level 1
instruction TLB access, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8134, DTLB_HWUPD, Data TLB
hardware update of translation table

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8134, DTLB_HWUPD, Data TLB
hardware update of translation table

# topic.topics[].topics[].topics[].topics[].label
​0x8135, ITLB_HWUPD, Instruction
TLB hardware update of translation table

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8135, ITLB_HWUPD, Instruction
TLB hardware update of translation table

# topic.topics[].topics[].topics[].topics[].label
​0x8136, DTLB_STEP, Data TLB
translation table walk, step

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8136, DTLB_STEP, Data TLB
translation table walk, step

# topic.topics[].topics[].topics[].topics[].label
​0x8137, ITLB_STEP, Instruction TLB
translation table walk, step

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8137, ITLB_STEP, Instruction TLB
translation table walk, step

# topic.topics[].topics[].topics[].topics[].label
​0x8138, DTLB_WALK_LARGE,
Data TLB large page translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8138, DTLB_WALK_LARGE,
Data TLB large page translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x8139, ITLB_WALK_LARGE,
Instruction TLB large page translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8139, ITLB_WALK_LARGE,
Instruction TLB large page translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x813A, DTLB_WALK_SMALL,
Data TLB small page translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x813A, DTLB_WALK_SMALL,
Data TLB small page translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x813B, ITLB_WALK_SMALL,
Instruction TLB small page translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x813B, ITLB_WALK_SMALL,
Instruction TLB small page translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x813C, DTLB_WALK_RW, Data TLB
demand access, with at least one translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x813C, DTLB_WALK_RW, Data TLB
demand access, with at least one translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x813D, ITLB_WALK_RD,
Instruction TLB demand access, with at least one translation table
walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x813D, ITLB_WALK_RD,
Instruction TLB demand access, with at least one translation table
walk

# topic.topics[].topics[].topics[].topics[].label
​0x813E, DTLB_WALK_PRFM, Data
TLB software prefetch, with at least one translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x813E, DTLB_WALK_PRFM, Data
TLB software prefetch, with at least one translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x813F, ITLB_WALK_PRFM,
Instruction TLB software prefetch, with at least one translation table
walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x813F, ITLB_WALK_PRFM,
Instruction TLB software prefetch, with at least one translation table
walk

# topic.topics[].topics[].topics[].topics[].label
​0x8140, L1D_CACHE_RW, Level 1
data cache demand access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8140, L1D_CACHE_RW, Level 1
data cache demand access

# topic.topics[].topics[].topics[].topics[].label
​0x8141, L1I_CACHE_RD, Level 1
instruction cache demand fetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8141, L1I_CACHE_RD, Level 1
instruction cache demand fetch

# topic.topics[].topics[].topics[].topics[].label
​0x8142, L1D_CACHE_PRFM, Level
1 data cache software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8142, L1D_CACHE_PRFM, Level
1 data cache software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8143, L1I_CACHE_PRFM, Level
1 instruction cache software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8143, L1I_CACHE_PRFM, Level
1 instruction cache software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8144, L1D_CACHE_MISS, Level
1 data cache demand access miss

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8144, L1D_CACHE_MISS, Level
1 data cache demand access miss

# topic.topics[].topics[].topics[].topics[].label
​0x8145, L1I_CACHE_HWPRF,
Level 1 instruction cache hardware prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8145, L1I_CACHE_HWPRF,
Level 1 instruction cache hardware prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8146,
L1D_CACHE_REFILL_PRFM, Level 1 data cache refill, software
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8146,
L1D_CACHE_REFILL_PRFM, Level 1 data cache refill, software
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8147,
L1I_CACHE_REFILL_PRFM, Level 1 instruction cache refill, software
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8147,
L1I_CACHE_REFILL_PRFM, Level 1 instruction cache refill, software
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8148, L2D_CACHE_RW, Level 2
data cache demand access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8148, L2D_CACHE_RW, Level 2
data cache demand access

# topic.topics[].topics[].topics[].topics[].label
​0x8149, L2I_CACHE_RD, Level 2
instruction cache demand fetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8149, L2I_CACHE_RD, Level 2
instruction cache demand fetch

# topic.topics[].topics[].topics[].topics[].label
​0x814A, L2D_CACHE_PRFM, Level
2 data cache software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x814A, L2D_CACHE_PRFM, Level
2 data cache software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x814B, L2I_CACHE_PRFM, Level
2 instruction cache software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x814B, L2I_CACHE_PRFM, Level
2 instruction cache software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x814C, L2D_CACHE_MISS, Level
2 data cache demand access miss

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x814C, L2D_CACHE_MISS, Level
2 data cache demand access miss

# topic.topics[].topics[].topics[].topics[].label
​0x814D, L2I_CACHE_HWPRF,
Level 2 instruction cache hardware prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x814D, L2I_CACHE_HWPRF,
Level 2 instruction cache hardware prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x814E,
L2D_CACHE_REFILL_PRFM, Level 2 data cache refill, software
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x814E,
L2D_CACHE_REFILL_PRFM, Level 2 data cache refill, software
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x814F,
L2I_CACHE_REFILL_PRFM, Level 2 instruction cache refill, software
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x814F,
L2I_CACHE_REFILL_PRFM, Level 2 instruction cache refill, software
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8150, L3D_CACHE_RW, Level 3
data cache demand access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8150, L3D_CACHE_RW, Level 3
data cache demand access

# topic.topics[].topics[].topics[].topics[].label
​0x8151, L3D_CACHE_PRFM, Level
3 data cache software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8151, L3D_CACHE_PRFM, Level
3 data cache software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8152, L3D_CACHE_MISS, Level
3 data cache demand access miss

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8152, L3D_CACHE_MISS, Level
3 data cache demand access miss

# topic.topics[].topics[].topics[].topics[].label
​0x8153,
L3D_CACHE_REFILL_PRFM, Level 3 data cache refill, software
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8153,
L3D_CACHE_REFILL_PRFM, Level 3 data cache refill, software
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8154, L1D_CACHE_HWPRF,
Level 1 data cache hardware prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8154, L1D_CACHE_HWPRF,
Level 1 data cache hardware prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8155, L2D_CACHE_HWPRF,
Level 2 data cache hardware prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8155, L2D_CACHE_HWPRF,
Level 2 data cache hardware prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8156, L3D_CACHE_HWPRF,
Level 3 data cache hardware prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8156, L3D_CACHE_HWPRF,
Level 3 data cache hardware prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8157, LL_CACHE_HWPRF, Last
level cache hardware prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8157, LL_CACHE_HWPRF, Last
level cache hardware prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8158,
STALL_FRONTEND_MEMBOUND, Frontend stall cycles, memory bound

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8158,
STALL_FRONTEND_MEMBOUND, Frontend stall cycles, memory bound

# topic.topics[].topics[].topics[].topics[].label
​0x8159,
STALL_FRONTEND_L1I, Frontend stall cycles, level 1 instruction
cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8159,
STALL_FRONTEND_L1I, Frontend stall cycles, level 1 instruction
cache

# topic.topics[].topics[].topics[].topics[].label
​0x815A,
STALL_FRONTEND_L2I, Frontend stall cycles, level 2 instruction
cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x815A,
STALL_FRONTEND_L2I, Frontend stall cycles, level 2 instruction
cache

# topic.topics[].topics[].topics[].topics[].label
​0x815B,
STALL_FRONTEND_MEM, Frontend stall cycles, last level PE cache or
memory

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x815B,
STALL_FRONTEND_MEM, Frontend stall cycles, last level PE cache or
memory

# topic.topics[].topics[].topics[].topics[].label
​0x815C,
STALL_FRONTEND_TLB, Frontend stall cycles, TLB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x815C,
STALL_FRONTEND_TLB, Frontend stall cycles, TLB

# topic.topics[].topics[].topics[].topics[].label
​0x815D,
STALL_BACKEND_BUSY_SMCU, Backend stall cycles, SMCU busy

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x815D,
STALL_BACKEND_BUSY_SMCU, Backend stall cycles, SMCU busy

# topic.topics[].topics[].topics[].topics[].label
​0x8160,
STALL_FRONTEND_CPUBOUND, Frontend stall cycles, processor bound

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8160,
STALL_FRONTEND_CPUBOUND, Frontend stall cycles, processor bound

# topic.topics[].topics[].topics[].topics[].label
​0x8161,
STALL_FRONTEND_FLOW, Frontend stall cycles, flow control

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8161,
STALL_FRONTEND_FLOW, Frontend stall cycles, flow control

# topic.topics[].topics[].topics[].topics[].label
​0x8162,
STALL_FRONTEND_FLUSH, Frontend stall cycles, flush recovery

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8162,
STALL_FRONTEND_FLUSH, Frontend stall cycles, flush recovery

# topic.topics[].topics[].topics[].topics[].label
​0x8163,
STALL_FRONTEND_RENAME, Frontend stall cycles, rename full

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8163,
STALL_FRONTEND_RENAME, Frontend stall cycles, rename full

# topic.topics[].topics[].topics[].topics[].label
​0x8164,
STALL_BACKEND_MEMBOUND, Backend stall cycles, memory bound

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8164,
STALL_BACKEND_MEMBOUND, Backend stall cycles, memory bound

# topic.topics[].topics[].topics[].topics[].label
​0x8165, STALL_BACKEND_L1D,
Backend stall cycles, level 1 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8165, STALL_BACKEND_L1D,
Backend stall cycles, level 1 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x8166, STALL_BACKEND_L2D,
Backend stall cycles, level 2 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8166, STALL_BACKEND_L2D,
Backend stall cycles, level 2 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x8167, STALL_BACKEND_TLB,
Backend stall cycles, TLB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8167, STALL_BACKEND_TLB,
Backend stall cycles, TLB

# topic.topics[].topics[].topics[].topics[].label
​0x8168, STALL_BACKEND_ST,
Backend stall cycles, store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8168, STALL_BACKEND_ST,
Backend stall cycles, store

# topic.topics[].topics[].topics[].topics[].label
​0x816A,
STALL_BACKEND_CPUBOUND, Backend stall cycles, processor bound

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x816A,
STALL_BACKEND_CPUBOUND, Backend stall cycles, processor bound

# topic.topics[].topics[].topics[].topics[].label
​0x816B,
STALL_BACKEND_BUSY, Backend stall cycles, backend busy

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x816B,
STALL_BACKEND_BUSY, Backend stall cycles, backend busy

# topic.topics[].topics[].topics[].topics[].label
​0x816C,
STALL_BACKEND_ILOCK, Backend stall cycles, input dependency

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x816C,
STALL_BACKEND_ILOCK, Backend stall cycles, input dependency

# topic.topics[].topics[].topics[].topics[].label
​0x816D,
STALL_BACKEND_RENAME, Backend stall cycles, rename full

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x816D,
STALL_BACKEND_RENAME, Backend stall cycles, rename full

# topic.topics[].topics[].topics[].topics[].label
​0x816E,
STALL_BACKEND_ATOMIC, Backend stall cycles, atomic operation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x816E,
STALL_BACKEND_ATOMIC, Backend stall cycles, atomic operation

# topic.topics[].topics[].topics[].topics[].label
​0x816F,
STALL_BACKEND_MEMCPYSET, Backend stall cycles, Memory Copy or Set
operation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x816F,
STALL_BACKEND_MEMCPYSET, Backend stall cycles, Memory Copy or Set
operation

# topic.topics[].topics[].topics[].topics[].label
​0x8170, CAS_NEAR_FAIL, Atomic
memory Operation speculatively executed, Compare and Swap fail

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8170, CAS_NEAR_FAIL, Atomic
memory Operation speculatively executed, Compare and Swap fail

# topic.topics[].topics[].topics[].topics[].label
​0x8171, CAS_NEAR_PASS, Atomic
memory Operation speculatively executed, Compare and Swap pass

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8171, CAS_NEAR_PASS, Atomic
memory Operation speculatively executed, Compare and Swap pass

# topic.topics[].topics[].topics[].topics[].label
​0x8172, CAS_NEAR_SPEC, Atomic
memory Operation speculatively executed, Compare and Swap near

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8172, CAS_NEAR_SPEC, Atomic
memory Operation speculatively executed, Compare and Swap near

# topic.topics[].topics[].topics[].topics[].label
​0x8173, CAS_FAR_SPEC, Atomic
memory Operation speculatively executed, Compare and Swap far

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8173, CAS_FAR_SPEC, Atomic
memory Operation speculatively executed, Compare and Swap far

# topic.topics[].topics[].topics[].topics[].label
​0x8174, CAS_SPEC, Atomic memory
Operation speculatively executed, Compare and Swap

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8174, CAS_SPEC, Atomic memory
Operation speculatively executed, Compare and Swap

# topic.topics[].topics[].topics[].topics[].label
​0x8175, LSE_LD_SPEC, Atomic
memory Operation speculatively executed, load

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8175, LSE_LD_SPEC, Atomic
memory Operation speculatively executed, load

# topic.topics[].topics[].topics[].topics[].label
​0x8176, LSE_ST_SPEC, Atomic
memory Operation speculatively executed, store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8176, LSE_ST_SPEC, Atomic
memory Operation speculatively executed, store

# topic.topics[].topics[].topics[].topics[].label
​0x8177, LSE_LDST_SPEC, Atomic
memory Operation speculatively executed, load or store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8177, LSE_LDST_SPEC, Atomic
memory Operation speculatively executed, load or store

# topic.topics[].topics[].topics[].topics[].label
​0x8178, REMOTE_ACCESS_WR,
Access to a remote device, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8178, REMOTE_ACCESS_WR,
Access to a remote device, write

# topic.topics[].topics[].topics[].topics[].label
​0x8188, DTLB_WALK_BLOCK,
Data TLB block translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8188, DTLB_WALK_BLOCK,
Data TLB block translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x8189, ITLB_WALK_BLOCK,
Instruction TLB block translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8189, ITLB_WALK_BLOCK,
Instruction TLB block translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x818A, DTLB_WALK_PAGE, Data
TLB page translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x818A, DTLB_WALK_PAGE, Data
TLB page translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x818B, ITLB_WALK_PAGE,
Instruction TLB page translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x818B, ITLB_WALK_PAGE,
Instruction TLB page translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x8190, ISNP_HIT_RD, Snoop hit,
demand instruction fetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8190, ISNP_HIT_RD, Snoop hit,
demand instruction fetch

# topic.topics[].topics[].topics[].topics[].label
​0x8191, ISNP_HIT_NEAR_RD,
Snoop hit in near local cache, demand instruction fetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8191, ISNP_HIT_NEAR_RD,
Snoop hit in near local cache, demand instruction fetch

# topic.topics[].topics[].topics[].topics[].label
​0x8192, ISNP_HIT_FAR_RD,
Snoop hit in far local cache, demand instruction fetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8192, ISNP_HIT_FAR_RD,
Snoop hit in far local cache, demand instruction fetch

# topic.topics[].topics[].topics[].topics[].label
​0x8193,
ISNP_HIT_REMOTE_RD, Snoop hit in remote cache, demand instruction
fetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8193,
ISNP_HIT_REMOTE_RD, Snoop hit in remote cache, demand instruction
fetch

# topic.topics[].topics[].topics[].topics[].label
​0x8194, DSNP_HIT_RD, Snoop hit,
demand data read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8194, DSNP_HIT_RD, Snoop hit,
demand data read

# topic.topics[].topics[].topics[].topics[].label
​0x8195, DSNP_HIT_NEAR_RD,
Snoop hit in near local cache, demand data read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8195, DSNP_HIT_NEAR_RD,
Snoop hit in near local cache, demand data read

# topic.topics[].topics[].topics[].topics[].label
​0x8196, DSNP_HIT_FAR_RD,
Snoop hit in far local cache, demand data read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8196, DSNP_HIT_FAR_RD,
Snoop hit in far local cache, demand data read

# topic.topics[].topics[].topics[].topics[].label
​0x8197,
DSNP_HIT_REMOTE_RD, Snoop hit in remote cache, demand data read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8197,
DSNP_HIT_REMOTE_RD, Snoop hit in remote cache, demand data read

# topic.topics[].topics[].topics[].topics[].label
​0x8198, DSNP_HIT_WR, Snoop hit,
demand data write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8198, DSNP_HIT_WR, Snoop hit,
demand data write

# topic.topics[].topics[].topics[].topics[].label
​0x8199, DSNP_HIT_NEAR_WR,
Snoop hit in near local cache, demand data write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8199, DSNP_HIT_NEAR_WR,
Snoop hit in near local cache, demand data write

# topic.topics[].topics[].topics[].topics[].label
​0x819A, DSNP_HIT_FAR_WR,
Snoop hit in far local cache, demand data write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x819A, DSNP_HIT_FAR_WR,
Snoop hit in far local cache, demand data write

# topic.topics[].topics[].topics[].topics[].label
​0x819B,
DSNP_HIT_REMOTE_WR, Snoop hit in remote cache, demand data
write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x819B,
DSNP_HIT_REMOTE_WR, Snoop hit in remote cache, demand data
write

# topic.topics[].topics[].topics[].topics[].label
​0x819C, DSNP_HIT_RW, Snoop hit,
demand data access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x819C, DSNP_HIT_RW, Snoop hit,
demand data access

# topic.topics[].topics[].topics[].topics[].label
​0x819D, DSNP_HIT_NEAR_RW,
Snoop hit in near local cache, demand data access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x819D, DSNP_HIT_NEAR_RW,
Snoop hit in near local cache, demand data access

# topic.topics[].topics[].topics[].topics[].label
​0x819E, DSNP_HIT_FAR_RW,
Snoop hit in far local cache, demand data access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x819E, DSNP_HIT_FAR_RW,
Snoop hit in far local cache, demand data access

# topic.topics[].topics[].topics[].topics[].label
​0x819F,
DSNP_HIT_REMOTE_RW, Snoop hit in remote cache, demand data
access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x819F,
DSNP_HIT_REMOTE_RW, Snoop hit in remote cache, demand data
access

# topic.topics[].topics[].topics[].topics[].label
​0x81A0, DSNP_HIT_PRFM, Snoop
hit, software data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81A0, DSNP_HIT_PRFM, Snoop
hit, software data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81A1,
DSNP_HIT_NEAR_PRFM, Snoop hit in near local cache, software data
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81A1,
DSNP_HIT_NEAR_PRFM, Snoop hit in near local cache, software data
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81A2, DSNP_HIT_FAR_PRFM,
Snoop hit in far local cache, software data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81A2, DSNP_HIT_FAR_PRFM,
Snoop hit in far local cache, software data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81A3,
DSNP_HIT_REMOTE_PRFM, Snoop hit in remote cache, software data
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81A3,
DSNP_HIT_REMOTE_PRFM, Snoop hit in remote cache, software data
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81A4, DSNP_HIT_HWPRF, Snoop
hit, hardware data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81A4, DSNP_HIT_HWPRF, Snoop
hit, hardware data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81A5,
DSNP_HIT_NEAR_HWPRF, Snoop hit in near local cache, hardware data
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81A5,
DSNP_HIT_NEAR_HWPRF, Snoop hit in near local cache, hardware data
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81A6,
DSNP_HIT_FAR_HWPRF, Snoop hit in far local cache, hardware data
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81A6,
DSNP_HIT_FAR_HWPRF, Snoop hit in far local cache, hardware data
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81A7,
DSNP_HIT_REMOTE_HWPRF, Snoop hit in remote cache, hardware data
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81A7,
DSNP_HIT_REMOTE_HWPRF, Snoop hit in remote cache, hardware data
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81A8, ISNP_HIT_PRFM, Snoop
hit, software instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81A8, ISNP_HIT_PRFM, Snoop
hit, software instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81A9,
ISNP_HIT_NEAR_PRFM, Snoop hit in near local cache, software instruction
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81A9,
ISNP_HIT_NEAR_PRFM, Snoop hit in near local cache, software instruction
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81AA, ISNP_HIT_FAR_PRFM,
Snoop hit in far local cache, software instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81AA, ISNP_HIT_FAR_PRFM,
Snoop hit in far local cache, software instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81AB,
ISNP_HIT_REMOTE_PRFM, Snoop hit in remote cache, software instruction
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81AB,
ISNP_HIT_REMOTE_PRFM, Snoop hit in remote cache, software instruction
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81AC, ISNP_HIT_HWPRF, Snoop
hit, hardware instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81AC, ISNP_HIT_HWPRF, Snoop
hit, hardware instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81AD,
ISNP_HIT_NEAR_HWPRF, Snoop hit in near local cache, hardware instruction
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81AD,
ISNP_HIT_NEAR_HWPRF, Snoop hit in near local cache, hardware instruction
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81AE,
ISNP_HIT_FAR_HWPRF, Snoop hit in far local cache, hardware instruction
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81AE,
ISNP_HIT_FAR_HWPRF, Snoop hit in far local cache, hardware instruction
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81AF,
ISNP_HIT_REMOTE_HWPRF, Snoop hit in remote cache, hardware instruction
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81AF,
ISNP_HIT_REMOTE_HWPRF, Snoop hit in remote cache, hardware instruction
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81B0, ISNP_HIT, Snoop hit,
instruction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81B0, ISNP_HIT, Snoop hit,
instruction

# topic.topics[].topics[].topics[].topics[].label
​0x81B1, ISNP_HIT_NEAR, Snoop
hit in near local cache, instruction access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81B1, ISNP_HIT_NEAR, Snoop
hit in near local cache, instruction access

# topic.topics[].topics[].topics[].topics[].label
​0x81B2, ISNP_HIT_FAR, Snoop hit
in far local cache, instruction access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81B2, ISNP_HIT_FAR, Snoop hit
in far local cache, instruction access

# topic.topics[].topics[].topics[].topics[].label
​0x81B3, ISNP_HIT_REMOTE,
Snoop hit in remote cache, instruction access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81B3, ISNP_HIT_REMOTE,
Snoop hit in remote cache, instruction access

# topic.topics[].topics[].topics[].topics[].label
​0x81B5, DSNP_HIT_NEAR, Snoop
hit in near local cache, data access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81B5, DSNP_HIT_NEAR, Snoop
hit in near local cache, data access

# topic.topics[].topics[].topics[].topics[].label
​0x81B6, DSNP_HIT_FAR, Snoop hit
in far local cache, data access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81B6, DSNP_HIT_FAR, Snoop hit
in far local cache, data access

# topic.topics[].topics[].topics[].topics[].label
​0x81B7, DSNP_HIT_REMOTE,
Snoop hit in remote cache, data access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81B7, DSNP_HIT_REMOTE,
Snoop hit in remote cache, data access

# topic.topics[].topics[].topics[].topics[].label
​0x81B8,
L1I_CACHE_REFILL_HWPRF, Level 1 instruction cache refill, hardware
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81B8,
L1I_CACHE_REFILL_HWPRF, Level 1 instruction cache refill, hardware
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81B9,
L2I_CACHE_REFILL_HWPRF, Level 2 instruction cache refill, hardware
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81B9,
L2I_CACHE_REFILL_HWPRF, Level 2 instruction cache refill, hardware
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81BC,
L1D_CACHE_REFILL_HWPRF, Level 1 data cache refill, hardware
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81BC,
L1D_CACHE_REFILL_HWPRF, Level 1 data cache refill, hardware
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81BD,
L2D_CACHE_REFILL_HWPRF, Level 2 data cache refill, hardware
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81BD,
L2D_CACHE_REFILL_HWPRF, Level 2 data cache refill, hardware
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81BE,
L3D_CACHE_REFILL_HWPRF, Level 3 data cache refill, hardware
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81BE,
L3D_CACHE_REFILL_HWPRF, Level 3 data cache refill, hardware
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81BF,
LL_CACHE_REFILL_HWPRF, Last level cache refill, hardware
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81BF,
LL_CACHE_REFILL_HWPRF, Last level cache refill, hardware
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81C0, L1I_CACHE_HIT_RD,
Level 1 instruction cache demand fetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81C0, L1I_CACHE_HIT_RD,
Level 1 instruction cache demand fetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x81C1, L2I_CACHE_HIT_RD,
Level 2 instruction cache demand fetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81C1, L2I_CACHE_HIT_RD,
Level 2 instruction cache demand fetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x81C4, L1D_CACHE_HIT_RD,
Level 1 data cache demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81C4, L1D_CACHE_HIT_RD,
Level 1 data cache demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x81C5, L2D_CACHE_HIT_RD,
Level 2 data cache demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81C5, L2D_CACHE_HIT_RD,
Level 2 data cache demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x81C6, L3D_CACHE_HIT_RD,
Level 3 data cache demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81C6, L3D_CACHE_HIT_RD,
Level 3 data cache demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x81C7, LL_CACHE_HIT_RD,
Last level cache demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81C7, LL_CACHE_HIT_RD,
Last level cache demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x81C8, L1D_CACHE_HIT_WR,
Level 1 data cache demand access hit, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81C8, L1D_CACHE_HIT_WR,
Level 1 data cache demand access hit, write

# topic.topics[].topics[].topics[].topics[].label
​0x81C9, L2D_CACHE_HIT_WR,
Level 2 data cache demand access hit, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81C9, L2D_CACHE_HIT_WR,
Level 2 data cache demand access hit, write

# topic.topics[].topics[].topics[].topics[].label
​0x81CA, L3D_CACHE_HIT_WR,
Level 3 data cache demand access hit, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81CA, L3D_CACHE_HIT_WR,
Level 3 data cache demand access hit, write

# topic.topics[].topics[].topics[].topics[].label
​0x81CB, LL_CACHE_HIT_WR,
Last level cache demand access hit, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81CB, LL_CACHE_HIT_WR,
Last level cache demand access hit, write

# topic.topics[].topics[].topics[].topics[].label
​0x81CC, L1D_CACHE_HIT_RW,
Level 1 data cache demand access hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81CC, L1D_CACHE_HIT_RW,
Level 1 data cache demand access hit

# topic.topics[].topics[].topics[].topics[].label
​0x81CD, L2D_CACHE_HIT_RW,
Level 2 data cache demand access hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81CD, L2D_CACHE_HIT_RW,
Level 2 data cache demand access hit

# topic.topics[].topics[].topics[].topics[].label
​0x81CE, L3D_CACHE_HIT_RW,
Level 3 data cache demand access hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81CE, L3D_CACHE_HIT_RW,
Level 3 data cache demand access hit

# topic.topics[].topics[].topics[].topics[].label
​0x81CF, LL_CACHE_HIT_RW,
Last level cache demand access hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81CF, LL_CACHE_HIT_RW,
Last level cache demand access hit

# topic.topics[].topics[].topics[].topics[].label
​0x81D0,
L1I_CACHE_HIT_RD_FPRFM, Level 1 instruction cache demand fetch first
hit, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81D0,
L1I_CACHE_HIT_RD_FPRFM, Level 1 instruction cache demand fetch first
hit, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81D1,
L2I_CACHE_HIT_RD_FPRFM, Level 2 instruction cache demand fetch first
hit, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81D1,
L2I_CACHE_HIT_RD_FPRFM, Level 2 instruction cache demand fetch first
hit, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81D4,
L1D_CACHE_HIT_RD_FPRFM, Level 1 data cache demand access first hit,
read, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81D4,
L1D_CACHE_HIT_RD_FPRFM, Level 1 data cache demand access first hit,
read, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81D5,
L2D_CACHE_HIT_RD_FPRFM, Level 2 data cache demand access first hit,
read, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81D5,
L2D_CACHE_HIT_RD_FPRFM, Level 2 data cache demand access first hit,
read, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81D6,
L3D_CACHE_HIT_RD_FPRFM, Level 3 data cache demand access first hit,
read, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81D6,
L3D_CACHE_HIT_RD_FPRFM, Level 3 data cache demand access first hit,
read, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81D7,
LL_CACHE_HIT_RD_FPRFM, Last level cache demand access first hit, read,
fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81D7,
LL_CACHE_HIT_RD_FPRFM, Last level cache demand access first hit, read,
fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81D8,
L1D_CACHE_HIT_WR_FPRFM, Level 1 data cache demand access first hit,
write, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81D8,
L1D_CACHE_HIT_WR_FPRFM, Level 1 data cache demand access first hit,
write, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81D9,
L2D_CACHE_HIT_WR_FPRFM, Level 2 data cache demand access first hit,
write, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81D9,
L2D_CACHE_HIT_WR_FPRFM, Level 2 data cache demand access first hit,
write, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81DA,
L3D_CACHE_HIT_WR_FPRFM, Level 3 data cache demand access first hit,
write, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81DA,
L3D_CACHE_HIT_WR_FPRFM, Level 3 data cache demand access first hit,
write, fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81DB,
LL_CACHE_HIT_WR_FPRFM, Last level cache demand access first hit, write,
fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81DB,
LL_CACHE_HIT_WR_FPRFM, Last level cache demand access first hit, write,
fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81DC,
L1D_CACHE_HIT_RW_FPRFM, Level 1 data cache demand access first hit,
fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81DC,
L1D_CACHE_HIT_RW_FPRFM, Level 1 data cache demand access first hit,
fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81DD,
L2D_CACHE_HIT_RW_FPRFM, Level 2 data cache demand access first hit,
fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81DD,
L2D_CACHE_HIT_RW_FPRFM, Level 2 data cache demand access first hit,
fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81DE,
L3D_CACHE_HIT_RW_FPRFM, Level 3 data cache demand access first hit,
fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81DE,
L3D_CACHE_HIT_RW_FPRFM, Level 3 data cache demand access first hit,
fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81DF,
LL_CACHE_HIT_RW_FPRFM, Last level cache demand access first hit, fetched
by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81DF,
LL_CACHE_HIT_RW_FPRFM, Last level cache demand access first hit, fetched
by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81E0,
L1I_CACHE_HIT_RD_FHWPRF, Level 1 instruction cache demand fetch first
hit, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81E0,
L1I_CACHE_HIT_RD_FHWPRF, Level 1 instruction cache demand fetch first
hit, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x81E1,
L2I_CACHE_HIT_RD_FHWPRF, Level 2 instruction cache demand fetch first
hit, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81E1,
L2I_CACHE_HIT_RD_FHWPRF, Level 2 instruction cache demand fetch first
hit, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x81E4,
L1D_CACHE_HIT_RD_FHWPRF, Level 1 data cache demand access first hit,
read, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81E4,
L1D_CACHE_HIT_RD_FHWPRF, Level 1 data cache demand access first hit,
read, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x81E5,
L2D_CACHE_HIT_RD_FHWPRF, Level 2 data cache demand access first hit,
read, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81E5,
L2D_CACHE_HIT_RD_FHWPRF, Level 2 data cache demand access first hit,
read, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x81E6,
L3D_CACHE_HIT_RD_FHWPRF, Level 3 data cache demand access first hit,
read, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81E6,
L3D_CACHE_HIT_RD_FHWPRF, Level 3 data cache demand access first hit,
read, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x81E7,
LL_CACHE_HIT_RD_FHWPRF, Last level cache demand access first hit, read,
fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81E7,
LL_CACHE_HIT_RD_FHWPRF, Last level cache demand access first hit, read,
fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x81E8,
L1D_CACHE_HIT_WR_FHWPRF, Level 1 data cache demand access first hit,
write, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81E8,
L1D_CACHE_HIT_WR_FHWPRF, Level 1 data cache demand access first hit,
write, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x81E9,
L2D_CACHE_HIT_WR_FHWPRF, Level 2 data cache demand access first hit,
write, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81E9,
L2D_CACHE_HIT_WR_FHWPRF, Level 2 data cache demand access first hit,
write, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x81EA,
L3D_CACHE_HIT_WR_FHWPRF, Level 3 data cache demand access first hit,
write, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81EA,
L3D_CACHE_HIT_WR_FHWPRF, Level 3 data cache demand access first hit,
write, fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x81EB,
LL_CACHE_HIT_WR_FHWPRF, Last level cache demand access first hit, write,
fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81EB,
LL_CACHE_HIT_WR_FHWPRF, Last level cache demand access first hit, write,
fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x81EC,
L1D_CACHE_HIT_RW_FHWPRF, Level 1 data cache demand access first hit,
fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81EC,
L1D_CACHE_HIT_RW_FHWPRF, Level 1 data cache demand access first hit,
fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x81ED,
L2D_CACHE_HIT_RW_FHWPRF, Level 2 data cache demand access first hit,
fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81ED,
L2D_CACHE_HIT_RW_FHWPRF, Level 2 data cache demand access first hit,
fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x81EE,
L3D_CACHE_HIT_RW_FHWPRF, Level 3 data cache demand access first hit,
fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81EE,
L3D_CACHE_HIT_RW_FHWPRF, Level 3 data cache demand access first hit,
fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x81EF,
LL_CACHE_HIT_RW_FHWPRF, Last level cache demand access first hit,
fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81EF,
LL_CACHE_HIT_RW_FHWPRF, Last level cache demand access first hit,
fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x81F0,
L1I_CACHE_HIT_RD_FPRF, Level 1 instruction cache demand fetch first hit,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81F0,
L1I_CACHE_HIT_RD_FPRF, Level 1 instruction cache demand fetch first hit,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81F1,
L2I_CACHE_HIT_RD_FPRF, Level 2 instruction cache demand fetch first hit,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81F1,
L2I_CACHE_HIT_RD_FPRF, Level 2 instruction cache demand fetch first hit,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81F4,
L1D_CACHE_HIT_RD_FPRF, Level 1 data cache demand access first hit, read,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81F4,
L1D_CACHE_HIT_RD_FPRF, Level 1 data cache demand access first hit, read,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81F5,
L2D_CACHE_HIT_RD_FPRF, Level 2 data cache demand access first hit, read,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81F5,
L2D_CACHE_HIT_RD_FPRF, Level 2 data cache demand access first hit, read,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81F6,
L3D_CACHE_HIT_RD_FPRF, Level 3 data cache demand access first hit, read,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81F6,
L3D_CACHE_HIT_RD_FPRF, Level 3 data cache demand access first hit, read,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81F7,
LL_CACHE_HIT_RD_FPRF, Last level cache demand access first hit, read,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81F7,
LL_CACHE_HIT_RD_FPRF, Last level cache demand access first hit, read,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81F8,
L1D_CACHE_HIT_WR_FPRF, Level 1 data cache demand access first hit,
write, fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81F8,
L1D_CACHE_HIT_WR_FPRF, Level 1 data cache demand access first hit,
write, fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81F9,
L2D_CACHE_HIT_WR_FPRF, Level 2 data cache demand access first hit,
write, fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81F9,
L2D_CACHE_HIT_WR_FPRF, Level 2 data cache demand access first hit,
write, fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81FA,
L3D_CACHE_HIT_WR_FPRF, Level 3 data cache demand access first hit,
write, fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81FA,
L3D_CACHE_HIT_WR_FPRF, Level 3 data cache demand access first hit,
write, fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81FB,
LL_CACHE_HIT_WR_FPRF, Last level cache demand access first hit, write,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81FB,
LL_CACHE_HIT_WR_FPRF, Last level cache demand access first hit, write,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81FC,
L1D_CACHE_HIT_RW_FPRF, Level 1 data cache demand access first hit,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81FC,
L1D_CACHE_HIT_RW_FPRF, Level 1 data cache demand access first hit,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81FD,
L2D_CACHE_HIT_RW_FPRF, Level 2 data cache demand access first hit,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81FD,
L2D_CACHE_HIT_RW_FPRF, Level 2 data cache demand access first hit,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81FE,
L3D_CACHE_HIT_RW_FPRF, Level 3 data cache demand access first hit,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81FE,
L3D_CACHE_HIT_RW_FPRF, Level 3 data cache demand access first hit,
fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x81FF,
LL_CACHE_HIT_RW_FPRF, Last level cache demand access first hit, fetched
by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x81FF,
LL_CACHE_HIT_RW_FPRF, Last level cache demand access first hit, fetched
by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8200, L1I_CACHE_HIT, Level 1
instruction cache hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8200, L1I_CACHE_HIT, Level 1
instruction cache hit

# topic.topics[].topics[].topics[].topics[].label
​0x8201, L2I_CACHE_HIT, Level 2
instruction cache hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8201, L2I_CACHE_HIT, Level 2
instruction cache hit

# topic.topics[].topics[].topics[].topics[].label
​0x8204, L1D_CACHE_HIT, Level 1
data cache hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8204, L1D_CACHE_HIT, Level 1
data cache hit

# topic.topics[].topics[].topics[].topics[].label
​0x8205, L2D_CACHE_HIT, Level 2
data cache hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8205, L2D_CACHE_HIT, Level 2
data cache hit

# topic.topics[].topics[].topics[].topics[].label
​0x8206, L3D_CACHE_HIT, Level 3
data cache hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8206, L3D_CACHE_HIT, Level 3
data cache hit

# topic.topics[].topics[].topics[].topics[].label
​0x8207, LL_CACHE_HIT, Last
level cache hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8207, LL_CACHE_HIT, Last
level cache hit

# topic.topics[].topics[].topics[].topics[].label
​0x8208,
L1I_CACHE_HIT_PRFM, Level 1 instruction cache software prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8208,
L1I_CACHE_HIT_PRFM, Level 1 instruction cache software prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x8209,
L2I_CACHE_HIT_PRFM, Level 2 instruction cache software prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8209,
L2I_CACHE_HIT_PRFM, Level 2 instruction cache software prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x820C,
L1D_CACHE_HIT_PRFM, Level 1 data cache software prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x820C,
L1D_CACHE_HIT_PRFM, Level 1 data cache software prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x820D,
L2D_CACHE_HIT_PRFM, Level 2 data cache software prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x820D,
L2D_CACHE_HIT_PRFM, Level 2 data cache software prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x820E,
L3D_CACHE_HIT_PRFM, Level 3 data cache software prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x820E,
L3D_CACHE_HIT_PRFM, Level 3 data cache software prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x820F, LL_CACHE_HIT_PRFM,
Last level cache software prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x820F, LL_CACHE_HIT_PRFM,
Last level cache software prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x8214, L1D_CACHE_HITM_RD,
Level 1 data cache demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8214, L1D_CACHE_HITM_RD,
Level 1 data cache demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x8215, L2D_CACHE_HITM_RD,
Level 2 data cache demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8215, L2D_CACHE_HITM_RD,
Level 2 data cache demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x8216, L3D_CACHE_HITM_RD,
Level 3 data cache demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8216, L3D_CACHE_HITM_RD,
Level 3 data cache demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x8217, LL_CACHE_HITM_RD,
Last level cache demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8217, LL_CACHE_HITM_RD,
Last level cache demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x8218, L1D_CACHE_HITM_WR,
Level 1 data cache demand access hit modified, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8218, L1D_CACHE_HITM_WR,
Level 1 data cache demand access hit modified, write

# topic.topics[].topics[].topics[].topics[].label
​0x8219, L2D_CACHE_HITM_WR,
Level 2 data cache demand access hit modified, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8219, L2D_CACHE_HITM_WR,
Level 2 data cache demand access hit modified, write

# topic.topics[].topics[].topics[].topics[].label
​0x821A, L3D_CACHE_HITM_WR,
Level 3 data cache demand access hit modified, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x821A, L3D_CACHE_HITM_WR,
Level 3 data cache demand access hit modified, write

# topic.topics[].topics[].topics[].topics[].label
​0x821B, LL_CACHE_HITM_WR,
Last level cache demand access hit modified, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x821B, LL_CACHE_HITM_WR,
Last level cache demand access hit modified, write

# topic.topics[].topics[].topics[].topics[].label
​0x821C, L1D_CACHE_HITM_RW,
Level 1 data cache demand access hit modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x821C, L1D_CACHE_HITM_RW,
Level 1 data cache demand access hit modified

# topic.topics[].topics[].topics[].topics[].label
​0x821D, L2D_CACHE_HITM_RW,
Level 2 data cache demand access hit modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x821D, L2D_CACHE_HITM_RW,
Level 2 data cache demand access hit modified

# topic.topics[].topics[].topics[].topics[].label
​0x821E, L3D_CACHE_HITM_RW,
Level 3 data cache demand access hit modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x821E, L3D_CACHE_HITM_RW,
Level 3 data cache demand access hit modified

# topic.topics[].topics[].topics[].topics[].label
​0x821F, LL_CACHE_HITM_RW,
Last level cache demand access hit modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x821F, LL_CACHE_HITM_RW,
Last level cache demand access hit modified

# topic.topics[].topics[].topics[].topics[].label
​0x8224, DSNP_HITM_RD, Snoop
hit, demand data read, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8224, DSNP_HITM_RD, Snoop
hit, demand data read, modified

# topic.topics[].topics[].topics[].topics[].label
​0x8225, DSNP_HITM_NEAR_RD,
Snoop hit in near local cache, demand data read, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8225, DSNP_HITM_NEAR_RD,
Snoop hit in near local cache, demand data read, modified

# topic.topics[].topics[].topics[].topics[].label
​0x8226, DSNP_HITM_FAR_RD,
Snoop hit in far local cache, demand data read, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8226, DSNP_HITM_FAR_RD,
Snoop hit in far local cache, demand data read, modified

# topic.topics[].topics[].topics[].topics[].label
​0x8227,
DSNP_HITM_REMOTE_RD, Snoop hit in remote cache, demand data read,
modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8227,
DSNP_HITM_REMOTE_RD, Snoop hit in remote cache, demand data read,
modified

# topic.topics[].topics[].topics[].topics[].label
​0x8228, DSNP_HITM_WR, Snoop
hit, demand data write, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8228, DSNP_HITM_WR, Snoop
hit, demand data write, modified

# topic.topics[].topics[].topics[].topics[].label
​0x8229, DSNP_HITM_NEAR_WR,
Snoop hit in near local cache, demand data write, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8229, DSNP_HITM_NEAR_WR,
Snoop hit in near local cache, demand data write, modified

# topic.topics[].topics[].topics[].topics[].label
​0x822A, DSNP_HITM_FAR_WR,
Snoop hit in far local cache, demand data write, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x822A, DSNP_HITM_FAR_WR,
Snoop hit in far local cache, demand data write, modified

# topic.topics[].topics[].topics[].topics[].label
​0x822B,
DSNP_HITM_REMOTE_WR, Snoop hit in remote cache, demand data write,
modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x822B,
DSNP_HITM_REMOTE_WR, Snoop hit in remote cache, demand data write,
modified

# topic.topics[].topics[].topics[].topics[].label
​0x822C, DSNP_HITM_RW, Snoop
hit, demand data access, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x822C, DSNP_HITM_RW, Snoop
hit, demand data access, modified

# topic.topics[].topics[].topics[].topics[].label
​0x822D, DSNP_HITM_NEAR_RW,
Snoop hit in near local cache, demand data access, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x822D, DSNP_HITM_NEAR_RW,
Snoop hit in near local cache, demand data access, modified

# topic.topics[].topics[].topics[].topics[].label
​0x822E, DSNP_HITM_FAR_RW,
Snoop hit in far local cache, demand data access, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x822E, DSNP_HITM_FAR_RW,
Snoop hit in far local cache, demand data access, modified

# topic.topics[].topics[].topics[].topics[].label
​0x822F,
DSNP_HITM_REMOTE_RW, Snoop hit in remote cache, demand data access,
modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x822F,
DSNP_HITM_REMOTE_RW, Snoop hit in remote cache, demand data access,
modified

# topic.topics[].topics[].topics[].topics[].label
​0x8230, LOCAL_MEM, Access to
memory attached to this device

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8230, LOCAL_MEM, Access to
memory attached to this device

# topic.topics[].topics[].topics[].topics[].label
​0x8231, LOCAL_MEM_RD, Access to
memory attached to this device, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8231, LOCAL_MEM_RD, Access to
memory attached to this device, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x8232, LOCAL_MEM_WR, Access to
memory attached to this device, demand access, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8232, LOCAL_MEM_WR, Access to
memory attached to this device, demand access, write

# topic.topics[].topics[].topics[].topics[].label
​0x8233, LOCAL_MEM_RW, Access to
memory attached to this device, demand access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8233, LOCAL_MEM_RW, Access to
memory attached to this device, demand access

# topic.topics[].topics[].topics[].topics[].label
​0x8234, LOCAL_MEM_PRFM,
Access to memory attached to this device, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8234, LOCAL_MEM_PRFM,
Access to memory attached to this device, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8235,
LOCAL_MEM_LD_RETIRED, Load instruction architecturally executed, access
to memory attached to this device

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8235,
LOCAL_MEM_LD_RETIRED, Load instruction architecturally executed, access
to memory attached to this device

# topic.topics[].topics[].topics[].topics[].label
​0x8236,
LOCAL_MEM_ST_RETIRED, Store instruction architecturally executed, access
to memory attached to this device

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8236,
LOCAL_MEM_ST_RETIRED, Store instruction architecturally executed, access
to memory attached to this device

# topic.topics[].topics[].topics[].topics[].label
​0x8237,
LOCAL_MEM_LDST_RETIRED, Load or store instruction architecturally
executed, access to memory attached to this device

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8237,
LOCAL_MEM_LDST_RETIRED, Load or store instruction architecturally
executed, access to memory attached to this device

# topic.topics[].topics[].topics[].topics[].label
​0x8238, REMOTE_MEM, Access to
memory attached to a remote device

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8238, REMOTE_MEM, Access to
memory attached to a remote device

# topic.topics[].topics[].topics[].topics[].label
​0x8239, REMOTE_MEM_RD, Access
to memory attached to a remote device, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8239, REMOTE_MEM_RD, Access
to memory attached to a remote device, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x823A, REMOTE_MEM_WR, Access
to memory attached to a remote device, demand access, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x823A, REMOTE_MEM_WR, Access
to memory attached to a remote device, demand access, write

# topic.topics[].topics[].topics[].topics[].label
​0x823B, REMOTE_MEM_RW, Access
to memory attached to a remote device, demand access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x823B, REMOTE_MEM_RW, Access
to memory attached to a remote device, demand access

# topic.topics[].topics[].topics[].topics[].label
​0x823C, REMOTE_MEM_PRFM,
Access to memory attached to a remote device, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x823C, REMOTE_MEM_PRFM,
Access to memory attached to a remote device, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x823D,
REMOTE_MEM_LD_RETIRED, Load instruction architecturally executed, access
to memory attached to a remote device

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x823D,
REMOTE_MEM_LD_RETIRED, Load instruction architecturally executed, access
to memory attached to a remote device

# topic.topics[].topics[].topics[].topics[].label
​0x823E,
REMOTE_MEM_ST_RETIRED, Store instruction architecturally executed,
access to memory attached to a remote device

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x823E,
REMOTE_MEM_ST_RETIRED, Store instruction architecturally executed,
access to memory attached to a remote device

# topic.topics[].topics[].topics[].topics[].label
​0x823F,
REMOTE_MEM_LDST_RETIRED, Load or store instruction architecturally
executed, access to memory attached to a remote device

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x823F,
REMOTE_MEM_LDST_RETIRED, Load or store instruction architecturally
executed, access to memory attached to a remote device

# topic.topics[].topics[].topics[].topics[].label
​0x8240, L1I_LFB_HIT_RD, Level
1 instruction cache demand fetch line-fill buffer hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8240, L1I_LFB_HIT_RD, Level
1 instruction cache demand fetch line-fill buffer hit

# topic.topics[].topics[].topics[].topics[].label
​0x8241, L2I_LFB_HIT_RD, Level
2 instruction cache demand fetch line-fill buffer hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8241, L2I_LFB_HIT_RD, Level
2 instruction cache demand fetch line-fill buffer hit

# topic.topics[].topics[].topics[].topics[].label
​0x8244, L1D_LFB_HIT_RD, Level
1 data cache demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8244, L1D_LFB_HIT_RD, Level
1 data cache demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x8245, L2D_LFB_HIT_RD, Level
2 data cache demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8245, L2D_LFB_HIT_RD, Level
2 data cache demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x8246, L3D_LFB_HIT_RD, Level
3 data cache demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8246, L3D_LFB_HIT_RD, Level
3 data cache demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x8247, LL_LFB_HIT_RD, Last
level cache demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8247, LL_LFB_HIT_RD, Last
level cache demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x8248, L1D_LFB_HIT_WR, Level
1 data cache demand access line-fill buffer hit, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8248, L1D_LFB_HIT_WR, Level
1 data cache demand access line-fill buffer hit, write

# topic.topics[].topics[].topics[].topics[].label
​0x8249, L2D_LFB_HIT_WR, Level
2 data cache demand access line-fill buffer hit, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8249, L2D_LFB_HIT_WR, Level
2 data cache demand access line-fill buffer hit, write

# topic.topics[].topics[].topics[].topics[].label
​0x824A, L3D_LFB_HIT_WR, Level
3 data cache demand access line-fill buffer hit, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x824A, L3D_LFB_HIT_WR, Level
3 data cache demand access line-fill buffer hit, write

# topic.topics[].topics[].topics[].topics[].label
​0x824B, LL_LFB_HIT_WR, Last
level cache demand access line-fill buffer hit, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x824B, LL_LFB_HIT_WR, Last
level cache demand access line-fill buffer hit, write

# topic.topics[].topics[].topics[].topics[].label
​0x824C, L1D_LFB_HIT_RW, Level
1 data cache demand access line-fill buffer hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x824C, L1D_LFB_HIT_RW, Level
1 data cache demand access line-fill buffer hit

# topic.topics[].topics[].topics[].topics[].label
​0x824D, L2D_LFB_HIT_RW, Level
2 data cache demand access line-fill buffer hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x824D, L2D_LFB_HIT_RW, Level
2 data cache demand access line-fill buffer hit

# topic.topics[].topics[].topics[].topics[].label
​0x824E, L3D_LFB_HIT_RW, Level
3 data cache demand access line-fill buffer hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x824E, L3D_LFB_HIT_RW, Level
3 data cache demand access line-fill buffer hit

# topic.topics[].topics[].topics[].topics[].label
​0x824F, LL_LFB_HIT_RW, Last
level cache demand access line-fill buffer hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x824F, LL_LFB_HIT_RW, Last
level cache demand access line-fill buffer hit

# topic.topics[].topics[].topics[].topics[].label
​0x8250,
L1I_LFB_HIT_RD_FPRFM, Level 1 instruction cache demand fetch line-fill
buffer first hit, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8250,
L1I_LFB_HIT_RD_FPRFM, Level 1 instruction cache demand fetch line-fill
buffer first hit, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8251,
L2I_LFB_HIT_RD_FPRFM, Level 2 instruction cache demand fetch line-fill
buffer first hit, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8251,
L2I_LFB_HIT_RD_FPRFM, Level 2 instruction cache demand fetch line-fill
buffer first hit, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8254,
L1D_LFB_HIT_RD_FPRFM, Level 1 data cache demand access line-fill buffer
first hit, read, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8254,
L1D_LFB_HIT_RD_FPRFM, Level 1 data cache demand access line-fill buffer
first hit, read, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8255,
L2D_LFB_HIT_RD_FPRFM, Level 2 data cache demand access line-fill buffer
first hit, read, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8255,
L2D_LFB_HIT_RD_FPRFM, Level 2 data cache demand access line-fill buffer
first hit, read, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8256,
L3D_LFB_HIT_RD_FPRFM, Level 3 data cache demand access line-fill buffer
first hit, read, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8256,
L3D_LFB_HIT_RD_FPRFM, Level 3 data cache demand access line-fill buffer
first hit, read, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8257,
LL_LFB_HIT_RD_FPRFM, Last level cache demand access line-fill buffer
first hit, read, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8257,
LL_LFB_HIT_RD_FPRFM, Last level cache demand access line-fill buffer
first hit, read, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8258,
L1D_LFB_HIT_WR_FPRFM, Level 1 data cache demand access line-fill buffer
first hit, write, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8258,
L1D_LFB_HIT_WR_FPRFM, Level 1 data cache demand access line-fill buffer
first hit, write, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8259,
L2D_LFB_HIT_WR_FPRFM, Level 2 data cache demand access line-fill buffer
first hit, write, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8259,
L2D_LFB_HIT_WR_FPRFM, Level 2 data cache demand access line-fill buffer
first hit, write, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x825A,
L3D_LFB_HIT_WR_FPRFM, Level 3 data cache demand access line-fill buffer
first hit, write, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x825A,
L3D_LFB_HIT_WR_FPRFM, Level 3 data cache demand access line-fill buffer
first hit, write, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x825B,
LL_LFB_HIT_WR_FPRFM, Last level cache demand access line-fill buffer
first hit, write, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x825B,
LL_LFB_HIT_WR_FPRFM, Last level cache demand access line-fill buffer
first hit, write, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x825C,
L1D_LFB_HIT_RW_FPRFM, Level 1 data cache demand access line-fill buffer
first hit, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x825C,
L1D_LFB_HIT_RW_FPRFM, Level 1 data cache demand access line-fill buffer
first hit, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x825D,
L2D_LFB_HIT_RW_FPRFM, Level 2 data cache demand access line-fill buffer
first hit, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x825D,
L2D_LFB_HIT_RW_FPRFM, Level 2 data cache demand access line-fill buffer
first hit, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x825E,
L3D_LFB_HIT_RW_FPRFM, Level 3 data cache demand access line-fill buffer
first hit, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x825E,
L3D_LFB_HIT_RW_FPRFM, Level 3 data cache demand access line-fill buffer
first hit, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x825F,
LL_LFB_HIT_RW_FPRFM, Last level cache demand access line-fill buffer
first hit, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x825F,
LL_LFB_HIT_RW_FPRFM, Last level cache demand access line-fill buffer
first hit, recently fetched by software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8260,
L1I_LFB_HIT_RD_FHWPRF, Level 1 instruction cache demand fetch line-fill
buffer first hit, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8260,
L1I_LFB_HIT_RD_FHWPRF, Level 1 instruction cache demand fetch line-fill
buffer first hit, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x8261,
L2I_LFB_HIT_RD_FHWPRF, Level 2 instruction cache demand fetch line-fill
buffer first hit, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8261,
L2I_LFB_HIT_RD_FHWPRF, Level 2 instruction cache demand fetch line-fill
buffer first hit, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x8264,
L1D_LFB_HIT_RD_FHWPRF, Level 1 data cache demand access line-fill buffer
first hit, read, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8264,
L1D_LFB_HIT_RD_FHWPRF, Level 1 data cache demand access line-fill buffer
first hit, read, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x8265,
L2D_LFB_HIT_RD_FHWPRF, Level 2 data cache demand access line-fill buffer
first hit, read, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8265,
L2D_LFB_HIT_RD_FHWPRF, Level 2 data cache demand access line-fill buffer
first hit, read, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x8266,
L3D_LFB_HIT_RD_FHWPRF, Level 3 data cache demand access line-fill buffer
first hit, read, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8266,
L3D_LFB_HIT_RD_FHWPRF, Level 3 data cache demand access line-fill buffer
first hit, read, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x8267,
LL_LFB_HIT_RD_FHWPRF, Last level cache demand access line-fill buffer
first hit, read, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8267,
LL_LFB_HIT_RD_FHWPRF, Last level cache demand access line-fill buffer
first hit, read, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x8268,
L1D_LFB_HIT_WR_FHWPRF, Level 1 data cache demand access line-fill buffer
first hit, write, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8268,
L1D_LFB_HIT_WR_FHWPRF, Level 1 data cache demand access line-fill buffer
first hit, write, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x8269,
L2D_LFB_HIT_WR_FHWPRF, Level 2 data cache demand access line-fill buffer
first hit, write, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8269,
L2D_LFB_HIT_WR_FHWPRF, Level 2 data cache demand access line-fill buffer
first hit, write, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x826A,
L3D_LFB_HIT_WR_FHWPRF, Level 3 data cache demand access line-fill buffer
first hit, write, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x826A,
L3D_LFB_HIT_WR_FHWPRF, Level 3 data cache demand access line-fill buffer
first hit, write, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x826B,
LL_LFB_HIT_WR_FHWPRF, Last level cache demand access line-fill buffer
first hit, write, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x826B,
LL_LFB_HIT_WR_FHWPRF, Last level cache demand access line-fill buffer
first hit, write, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x826C,
L1D_LFB_HIT_RW_FHWPRF, Level 1 data cache demand access line-fill buffer
first hit, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x826C,
L1D_LFB_HIT_RW_FHWPRF, Level 1 data cache demand access line-fill buffer
first hit, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x826D,
L2D_LFB_HIT_RW_FHWPRF, Level 2 data cache demand access line-fill buffer
first hit, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x826D,
L2D_LFB_HIT_RW_FHWPRF, Level 2 data cache demand access line-fill buffer
first hit, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x826E,
L3D_LFB_HIT_RW_FHWPRF, Level 3 data cache demand access line-fill buffer
first hit, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x826E,
L3D_LFB_HIT_RW_FHWPRF, Level 3 data cache demand access line-fill buffer
first hit, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x826F,
LL_LFB_HIT_RW_FHWPRF, Last level cache demand access line-fill buffer
first hit, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x826F,
LL_LFB_HIT_RW_FHWPRF, Last level cache demand access line-fill buffer
first hit, recently fetched by hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x8270,
L1I_LFB_HIT_RD_FPRF, Level 1 instruction cache demand fetch line-fill
buffer first hit, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8270,
L1I_LFB_HIT_RD_FPRF, Level 1 instruction cache demand fetch line-fill
buffer first hit, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8271,
L2I_LFB_HIT_RD_FPRF, Level 2 instruction cache demand fetch line-fill
buffer first hit, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8271,
L2I_LFB_HIT_RD_FPRF, Level 2 instruction cache demand fetch line-fill
buffer first hit, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8274,
L1D_LFB_HIT_RD_FPRF, Level 1 data cache demand access line-fill buffer
first hit, read, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8274,
L1D_LFB_HIT_RD_FPRF, Level 1 data cache demand access line-fill buffer
first hit, read, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8275,
L2D_LFB_HIT_RD_FPRF, Level 2 data cache demand access line-fill buffer
first hit, read, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8275,
L2D_LFB_HIT_RD_FPRF, Level 2 data cache demand access line-fill buffer
first hit, read, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8276,
L3D_LFB_HIT_RD_FPRF, Level 3 data cache demand access line-fill buffer
first hit, read, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8276,
L3D_LFB_HIT_RD_FPRF, Level 3 data cache demand access line-fill buffer
first hit, read, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8277,
LL_LFB_HIT_RD_FPRF, Last level cache demand access line-fill buffer
first hit, read, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8277,
LL_LFB_HIT_RD_FPRF, Last level cache demand access line-fill buffer
first hit, read, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8278,
L1D_LFB_HIT_WR_FPRF, Level 1 data cache demand access line-fill buffer
first hit, write, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8278,
L1D_LFB_HIT_WR_FPRF, Level 1 data cache demand access line-fill buffer
first hit, write, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8279,
L2D_LFB_HIT_WR_FPRF, Level 2 data cache demand access line-fill buffer
first hit, write, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8279,
L2D_LFB_HIT_WR_FPRF, Level 2 data cache demand access line-fill buffer
first hit, write, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x827A,
L3D_LFB_HIT_WR_FPRF, Level 3 data cache demand access line-fill buffer
first hit, write, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x827A,
L3D_LFB_HIT_WR_FPRF, Level 3 data cache demand access line-fill buffer
first hit, write, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x827B,
LL_LFB_HIT_WR_FPRF, Last level cache demand access line-fill buffer
first hit, write, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x827B,
LL_LFB_HIT_WR_FPRF, Last level cache demand access line-fill buffer
first hit, write, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x827C,
L1D_LFB_HIT_RW_FPRF, Level 1 data cache demand access line-fill buffer
first hit, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x827C,
L1D_LFB_HIT_RW_FPRF, Level 1 data cache demand access line-fill buffer
first hit, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x827D,
L2D_LFB_HIT_RW_FPRF, Level 2 data cache demand access line-fill buffer
first hit, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x827D,
L2D_LFB_HIT_RW_FPRF, Level 2 data cache demand access line-fill buffer
first hit, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x827E,
L3D_LFB_HIT_RW_FPRF, Level 3 data cache demand access line-fill buffer
first hit, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x827E,
L3D_LFB_HIT_RW_FPRF, Level 3 data cache demand access line-fill buffer
first hit, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x827F,
LL_LFB_HIT_RW_FPRF, Last level cache demand access line-fill buffer
first hit, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x827F,
LL_LFB_HIT_RW_FPRF, Last level cache demand access line-fill buffer
first hit, recently fetched by prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8280, L1I_CACHE_PRF, Level 1
instruction cache, prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8280, L1I_CACHE_PRF, Level 1
instruction cache, prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x8281, L2I_CACHE_PRF, Level 2
instruction cache, prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8281, L2I_CACHE_PRF, Level 2
instruction cache, prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x8284, L1D_CACHE_PRF, Level 1
data cache, prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8284, L1D_CACHE_PRF, Level 1
data cache, prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x8285, L2D_CACHE_PRF, Level 2
data cache, prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8285, L2D_CACHE_PRF, Level 2
data cache, prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x8286, L3D_CACHE_PRF, Level 3
data cache, prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8286, L3D_CACHE_PRF, Level 3
data cache, prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x8287, LL_CACHE_PRF, Last
level cache, prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8287, LL_CACHE_PRF, Last
level cache, prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x8288,
L1I_CACHE_REFILL_PRF, Level 1 instruction cache refill, prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8288,
L1I_CACHE_REFILL_PRF, Level 1 instruction cache refill, prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x8289,
L2I_CACHE_REFILL_PRF, Level 2 instruction cache refill, prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8289,
L2I_CACHE_REFILL_PRF, Level 2 instruction cache refill, prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x828C,
L1D_CACHE_REFILL_PRF, Level 1 data cache refill, prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x828C,
L1D_CACHE_REFILL_PRF, Level 1 data cache refill, prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x828D,
L2D_CACHE_REFILL_PRF, Level 2 data cache refill, prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x828D,
L2D_CACHE_REFILL_PRF, Level 2 data cache refill, prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x828E,
L3D_CACHE_REFILL_PRF, Level 3 data cache refill, prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x828E,
L3D_CACHE_REFILL_PRF, Level 3 data cache refill, prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x828F,
LL_CACHE_REFILL_PRF, Last level cache refill, prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x828F,
LL_CACHE_REFILL_PRF, Last level cache refill, prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x8290, ISNP_HIT_PRF, Snoop
hit, instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8290, ISNP_HIT_PRF, Snoop
hit, instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8291, ISNP_HIT_NEAR_PRF,
Snoop hit in near local cache, instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8291, ISNP_HIT_NEAR_PRF,
Snoop hit in near local cache, instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8292, ISNP_HIT_FAR_PRF,
Snoop hit in far local cache, instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8292, ISNP_HIT_FAR_PRF,
Snoop hit in far local cache, instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8293,
ISNP_HIT_REMOTE_PRF, Snoop hit in remote cache, instruction
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8293,
ISNP_HIT_REMOTE_PRF, Snoop hit in remote cache, instruction
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8294, DSNP_HIT_PRF, Snoop
hit, data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8294, DSNP_HIT_PRF, Snoop
hit, data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8295, DSNP_HIT_NEAR_PRF,
Snoop hit in near local cache, data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8295, DSNP_HIT_NEAR_PRF,
Snoop hit in near local cache, data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8296, DSNP_HIT_FAR_PRF,
Snoop hit in far local cache, data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8296, DSNP_HIT_FAR_PRF,
Snoop hit in far local cache, data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8297,
DSNP_HIT_REMOTE_PRF, Snoop hit in remote cache, data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8297,
DSNP_HIT_REMOTE_PRF, Snoop hit in remote cache, data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8298, LL_CACHE_RW, Last level
cache demand access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8298, LL_CACHE_RW, Last level
cache demand access

# topic.topics[].topics[].topics[].topics[].label
​0x8299, LL_CACHE_PRFM, Last
level cache software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8299, LL_CACHE_PRFM, Last
level cache software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x829A, LL_CACHE_REFILL,
Last level cache refill

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x829A, LL_CACHE_REFILL,
Last level cache refill

# topic.topics[].topics[].topics[].topics[].label
​0x829B,
LL_CACHE_REFILL_PRFM, Last level cache refill, software
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x829B,
LL_CACHE_REFILL_PRFM, Last level cache refill, software
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x829C, LL_CACHE_WB, Last level
cache write-back

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x829C, LL_CACHE_WB, Last level
cache write-back

# topic.topics[].topics[].topics[].topics[].label
​0x829D, LL_CACHE_WR, Last level
cache access, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x829D, LL_CACHE_WR, Last level
cache access, write

# topic.topics[].topics[].topics[].topics[].label
​0x829F,
LL_CACHE_REFILL_WR, Last level cache refill, write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x829F,
LL_CACHE_REFILL_WR, Last level cache refill, write

# topic.topics[].topics[].topics[].topics[].label
​0x82A0, MEM_ACCESS_RW, Data
memory access, demand access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82A0, MEM_ACCESS_RW, Data
memory access, demand access

# topic.topics[].topics[].topics[].topics[].label
​0x82A1, INST_FETCH_RD,
Instruction memory access, demand fetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82A1, INST_FETCH_RD,
Instruction memory access, demand fetch

# topic.topics[].topics[].topics[].topics[].label
​0x82A2, MEM_ACCESS_PRFM,
Data memory access, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82A2, MEM_ACCESS_PRFM,
Data memory access, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x82A3, INST_FETCH_PRFM,
Instruction memory access, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82A3, INST_FETCH_PRFM,
Instruction memory access, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x82B0,
L1I_CACHE_MISS_RETIRED, Instruction architecturally executed, miss in
Level 1 instruction cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82B0,
L1I_CACHE_MISS_RETIRED, Instruction architecturally executed, miss in
Level 1 instruction cache

# topic.topics[].topics[].topics[].topics[].label
​0x82B1,
L2I_CACHE_MISS_RETIRED, Instruction architecturally executed, miss in
Level 2 instruction cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82B1,
L2I_CACHE_MISS_RETIRED, Instruction architecturally executed, miss in
Level 2 instruction cache

# topic.topics[].topics[].topics[].topics[].label
​0x82B4,
L1D_CACHE_MISS_LD_RETIRED, Load instruction architecturally executed,
miss in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82B4,
L1D_CACHE_MISS_LD_RETIRED, Load instruction architecturally executed,
miss in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82B5,
L2D_CACHE_MISS_LD_RETIRED, Load instruction architecturally executed,
miss in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82B5,
L2D_CACHE_MISS_LD_RETIRED, Load instruction architecturally executed,
miss in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82B6,
L3D_CACHE_MISS_LD_RETIRED, Load instruction architecturally executed,
miss in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82B6,
L3D_CACHE_MISS_LD_RETIRED, Load instruction architecturally executed,
miss in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82B7,
LL_CACHE_MISS_LD_RETIRED, Load instruction architecturally executed,
miss in Last level cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82B7,
LL_CACHE_MISS_LD_RETIRED, Load instruction architecturally executed,
miss in Last level cache

# topic.topics[].topics[].topics[].topics[].label
​0x82B8,
L1D_CACHE_MISS_ST_RETIRED, Store instruction architecturally executed,
miss in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82B8,
L1D_CACHE_MISS_ST_RETIRED, Store instruction architecturally executed,
miss in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82B9,
L2D_CACHE_MISS_ST_RETIRED, Store instruction architecturally executed,
miss in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82B9,
L2D_CACHE_MISS_ST_RETIRED, Store instruction architecturally executed,
miss in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82BA,
L3D_CACHE_MISS_ST_RETIRED, Store instruction architecturally executed,
miss in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82BA,
L3D_CACHE_MISS_ST_RETIRED, Store instruction architecturally executed,
miss in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82BB,
LL_CACHE_MISS_ST_RETIRED, Store instruction architecturally executed,
miss in Last level cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82BB,
LL_CACHE_MISS_ST_RETIRED, Store instruction architecturally executed,
miss in Last level cache

# topic.topics[].topics[].topics[].topics[].label
​0x82BC,
L1D_CACHE_MISS_LDST_RETIRED, Load or store instruction architecturally
executed, miss in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82BC,
L1D_CACHE_MISS_LDST_RETIRED, Load or store instruction architecturally
executed, miss in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82BD,
L2D_CACHE_MISS_LDST_RETIRED, Load or store instruction architecturally
executed, miss in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82BD,
L2D_CACHE_MISS_LDST_RETIRED, Load or store instruction architecturally
executed, miss in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82BE,
L3D_CACHE_MISS_LDST_RETIRED, Load or store instruction architecturally
executed, miss in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82BE,
L3D_CACHE_MISS_LDST_RETIRED, Load or store instruction architecturally
executed, miss in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82BF,
LL_CACHE_MISS_LDST_RETIRED, Load or store instruction architecturally
executed, miss in Last level cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82BF,
LL_CACHE_MISS_LDST_RETIRED, Load or store instruction architecturally
executed, miss in Last level cache

# topic.topics[].topics[].topics[].topics[].label
​0x82C4,
L1D_CACHE_HITM_LD_RETIRED, Load instruction architecturally executed,
hit modified data in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82C4,
L1D_CACHE_HITM_LD_RETIRED, Load instruction architecturally executed,
hit modified data in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82C5,
L2D_CACHE_HITM_LD_RETIRED, Load instruction architecturally executed,
hit modified data in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82C5,
L2D_CACHE_HITM_LD_RETIRED, Load instruction architecturally executed,
hit modified data in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82C6,
L3D_CACHE_HITM_LD_RETIRED, Load instruction architecturally executed,
hit modified data in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82C6,
L3D_CACHE_HITM_LD_RETIRED, Load instruction architecturally executed,
hit modified data in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82C7,
LL_CACHE_HITM_LD_RETIRED, Load instruction architecturally executed, hit
modified data in Last level cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82C7,
LL_CACHE_HITM_LD_RETIRED, Load instruction architecturally executed, hit
modified data in Last level cache

# topic.topics[].topics[].topics[].topics[].label
​0x82C8,
L1D_CACHE_HITM_ST_RETIRED, Store instruction architecturally executed,
hit modified data in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82C8,
L1D_CACHE_HITM_ST_RETIRED, Store instruction architecturally executed,
hit modified data in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82C9,
L2D_CACHE_HITM_ST_RETIRED, Store instruction architecturally executed,
hit modified data in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82C9,
L2D_CACHE_HITM_ST_RETIRED, Store instruction architecturally executed,
hit modified data in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82CA,
L3D_CACHE_HITM_ST_RETIRED, Store instruction architecturally executed,
hit modified data in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82CA,
L3D_CACHE_HITM_ST_RETIRED, Store instruction architecturally executed,
hit modified data in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82CB,
LL_CACHE_HITM_ST_RETIRED, Store instruction architecturally executed,
hit modified data in Last level cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82CB,
LL_CACHE_HITM_ST_RETIRED, Store instruction architecturally executed,
hit modified data in Last level cache

# topic.topics[].topics[].topics[].topics[].label
​0x82CC,
L1D_CACHE_HITM_LDST_RETIRED, Load or store instruction architecturally
executed, hit modified data in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82CC,
L1D_CACHE_HITM_LDST_RETIRED, Load or store instruction architecturally
executed, hit modified data in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82CD,
L2D_CACHE_HITM_LDST_RETIRED, Load or store instruction architecturally
executed, hit modified data in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82CD,
L2D_CACHE_HITM_LDST_RETIRED, Load or store instruction architecturally
executed, hit modified data in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82CE,
L3D_CACHE_HITM_LDST_RETIRED, Load or store instruction architecturally
executed, hit modified data in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82CE,
L3D_CACHE_HITM_LDST_RETIRED, Load or store instruction architecturally
executed, hit modified data in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82CF,
LL_CACHE_HITM_LDST_RETIRED, Load or store instruction architecturally
executed, hit modified data in Last level cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82CF,
LL_CACHE_HITM_LDST_RETIRED, Load or store instruction architecturally
executed, hit modified data in Last level cache

# topic.topics[].topics[].topics[].topics[].label
​0x82D0,
L1I_LFB_HIT_RETIRED, Instruction architecturally executed, line-fill
buffer hit in Level 1 instruction cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82D0,
L1I_LFB_HIT_RETIRED, Instruction architecturally executed, line-fill
buffer hit in Level 1 instruction cache

# topic.topics[].topics[].topics[].topics[].label
​0x82D1,
L2I_LFB_HIT_RETIRED, Instruction architecturally executed, line-fill
buffer hit in Level 2 instruction cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82D1,
L2I_LFB_HIT_RETIRED, Instruction architecturally executed, line-fill
buffer hit in Level 2 instruction cache

# topic.topics[].topics[].topics[].topics[].label
​0x82D4,
L1D_LFB_HIT_LD_RETIRED, Load instruction architecturally executed,
line-fill buffer hit in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82D4,
L1D_LFB_HIT_LD_RETIRED, Load instruction architecturally executed,
line-fill buffer hit in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82D5,
L2D_LFB_HIT_LD_RETIRED, Load instruction architecturally executed,
line-fill buffer hit in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82D5,
L2D_LFB_HIT_LD_RETIRED, Load instruction architecturally executed,
line-fill buffer hit in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82D6,
L3D_LFB_HIT_LD_RETIRED, Load instruction architecturally executed,
line-fill buffer hit in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82D6,
L3D_LFB_HIT_LD_RETIRED, Load instruction architecturally executed,
line-fill buffer hit in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82D7,
LL_LFB_HIT_LD_RETIRED, Load instruction architecturally executed,
line-fill buffer hit in Last level cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82D7,
LL_LFB_HIT_LD_RETIRED, Load instruction architecturally executed,
line-fill buffer hit in Last level cache

# topic.topics[].topics[].topics[].topics[].label
​0x82D8,
L1D_LFB_HIT_ST_RETIRED, Store instruction architecturally executed,
line-fill buffer hit in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82D8,
L1D_LFB_HIT_ST_RETIRED, Store instruction architecturally executed,
line-fill buffer hit in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82D9,
L2D_LFB_HIT_ST_RETIRED, Store instruction architecturally executed,
line-fill buffer hit in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82D9,
L2D_LFB_HIT_ST_RETIRED, Store instruction architecturally executed,
line-fill buffer hit in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82DA,
L3D_LFB_HIT_ST_RETIRED, Store instruction architecturally executed,
line-fill buffer hit in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82DA,
L3D_LFB_HIT_ST_RETIRED, Store instruction architecturally executed,
line-fill buffer hit in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82DB,
LL_LFB_HIT_ST_RETIRED, Store instruction architecturally executed,
line-fill buffer hit in Last level cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82DB,
LL_LFB_HIT_ST_RETIRED, Store instruction architecturally executed,
line-fill buffer hit in Last level cache

# topic.topics[].topics[].topics[].topics[].label
​0x82DC,
L1D_LFB_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, line-fill buffer hit in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82DC,
L1D_LFB_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, line-fill buffer hit in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82DD,
L2D_LFB_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, line-fill buffer hit in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82DD,
L2D_LFB_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, line-fill buffer hit in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82DE,
L3D_LFB_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, line-fill buffer hit in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82DE,
L3D_LFB_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, line-fill buffer hit in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82DF,
LL_LFB_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, line-fill buffer hit in Last level cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82DF,
LL_LFB_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, line-fill buffer hit in Last level cache

# topic.topics[].topics[].topics[].topics[].label
​0x82E0,
L1I_CACHE_HIT_RETIRED, Instruction architecturally executed, hit in
Level 1 instruction cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82E0,
L1I_CACHE_HIT_RETIRED, Instruction architecturally executed, hit in
Level 1 instruction cache

# topic.topics[].topics[].topics[].topics[].label
​0x82E1,
L2I_CACHE_HIT_RETIRED, Instruction architecturally executed, hit in
Level 2 instruction cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82E1,
L2I_CACHE_HIT_RETIRED, Instruction architecturally executed, hit in
Level 2 instruction cache

# topic.topics[].topics[].topics[].topics[].label
​0x82E4,
L1D_CACHE_HIT_LD_RETIRED, Load instruction architecturally executed, hit
in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82E4,
L1D_CACHE_HIT_LD_RETIRED, Load instruction architecturally executed, hit
in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82E5,
L2D_CACHE_HIT_LD_RETIRED, Load instruction architecturally executed, hit
in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82E5,
L2D_CACHE_HIT_LD_RETIRED, Load instruction architecturally executed, hit
in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82E6,
L3D_CACHE_HIT_LD_RETIRED, Load instruction architecturally executed, hit
in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82E6,
L3D_CACHE_HIT_LD_RETIRED, Load instruction architecturally executed, hit
in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82E7,
LL_CACHE_HIT_LD_RETIRED, Load instruction architecturally executed, hit
in Last level cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82E7,
LL_CACHE_HIT_LD_RETIRED, Load instruction architecturally executed, hit
in Last level cache

# topic.topics[].topics[].topics[].topics[].label
​0x82E8,
L1D_CACHE_HIT_ST_RETIRED, Store instruction architecturally executed,
hit in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82E8,
L1D_CACHE_HIT_ST_RETIRED, Store instruction architecturally executed,
hit in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82E9,
L2D_CACHE_HIT_ST_RETIRED, Store instruction architecturally executed,
hit in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82E9,
L2D_CACHE_HIT_ST_RETIRED, Store instruction architecturally executed,
hit in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82EA,
L3D_CACHE_HIT_ST_RETIRED, Store instruction architecturally executed,
hit in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82EA,
L3D_CACHE_HIT_ST_RETIRED, Store instruction architecturally executed,
hit in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82EB,
LL_CACHE_HIT_ST_RETIRED, Store instruction architecturally executed, hit
in Last level cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82EB,
LL_CACHE_HIT_ST_RETIRED, Store instruction architecturally executed, hit
in Last level cache

# topic.topics[].topics[].topics[].topics[].label
​0x82EC,
L1D_CACHE_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, hit in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82EC,
L1D_CACHE_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, hit in Level 1 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82ED,
L2D_CACHE_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, hit in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82ED,
L2D_CACHE_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, hit in Level 2 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82EE,
L3D_CACHE_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, hit in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82EE,
L3D_CACHE_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, hit in Level 3 data cache

# topic.topics[].topics[].topics[].topics[].label
​0x82EF,
LL_CACHE_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, hit in Last level cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82EF,
LL_CACHE_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, hit in Last level cache

# topic.topics[].topics[].topics[].topics[].label
​0x82F0, ITLB_HIT_RETIRED,
Instruction architecturally executed, no translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82F0, ITLB_HIT_RETIRED,
Instruction architecturally executed, no translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x82F1,
DTLB_HIT_LD_RETIRED, Load instruction architecturally executed, no
translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82F1,
DTLB_HIT_LD_RETIRED, Load instruction architecturally executed, no
translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x82F2,
DTLB_HIT_ST_RETIRED, Store instruction architecturally executed, no
translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82F2,
DTLB_HIT_ST_RETIRED, Store instruction architecturally executed, no
translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x82F3,
DTLB_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, no translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82F3,
DTLB_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, no translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x82F4, ITLB_WALK_RETIRED,
Instruction architecturally executed, at least one translation table
walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82F4, ITLB_WALK_RETIRED,
Instruction architecturally executed, at least one translation table
walk

# topic.topics[].topics[].topics[].topics[].label
​0x82F5,
DTLB_WALK_LD_RETIRED, Load instruction architecturally executed, at
least one translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82F5,
DTLB_WALK_LD_RETIRED, Load instruction architecturally executed, at
least one translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x82F6,
DTLB_WALK_ST_RETIRED, Store instruction architecturally executed, at
least one translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82F6,
DTLB_WALK_ST_RETIRED, Store instruction architecturally executed, at
least one translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x82F7,
DTLB_WALK_LDST_RETIRED, Load or store instruction architecturally
executed, at least one translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82F7,
DTLB_WALK_LDST_RETIRED, Load or store instruction architecturally
executed, at least one translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x82F8, DTLB_WALK_PRF, Data
TLB prefetch, with at least one translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82F8, DTLB_WALK_PRF, Data
TLB prefetch, with at least one translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x82F9, ITLB_WALK_PRF,
Instruction TLB prefetch, with at least one translation table
walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82F9, ITLB_WALK_PRF,
Instruction TLB prefetch, with at least one translation table
walk

# topic.topics[].topics[].topics[].topics[].label
​0x82FA, DTLB_WALK_HWPRF,
Data TLB hardware prefetch, with at least one translation table
walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82FA, DTLB_WALK_HWPRF,
Data TLB hardware prefetch, with at least one translation table
walk

# topic.topics[].topics[].topics[].topics[].label
​0x82FB, ITLB_WALK_HWPRF,
Instruction TLB hardware prefetch, with at least one translation table
walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82FB, ITLB_WALK_HWPRF,
Instruction TLB hardware prefetch, with at least one translation table
walk

# topic.topics[].topics[].topics[].topics[].label
​0x82FC, L1D_TLB_PRF, Level 1
data TLB access, prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82FC, L1D_TLB_PRF, Level 1
data TLB access, prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x82FD, L1I_TLB_PRF, Level 1
instruction TLB access, prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82FD, L1I_TLB_PRF, Level 1
instruction TLB access, prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x82FE, L1D_TLB_HWPRF, Level 1
data TLB access, hardware prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82FE, L1D_TLB_HWPRF, Level 1
data TLB access, hardware prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x82FF, L1I_TLB_HWPRF, Level 1
instruction TLB access, hardware prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x82FF, L1I_TLB_HWPRF, Level 1
instruction TLB access, hardware prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8304,
DSNP_HITM_LD_RETIRED, Load instruction architecturally executed, snoop
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8304,
DSNP_HITM_LD_RETIRED, Load instruction architecturally executed, snoop
hit

# topic.topics[].topics[].topics[].topics[].label
​0x8305,
DSNP_HITM_NEAR_LD_RETIRED, Load instruction architecturally executed,
snoop hit in near cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8305,
DSNP_HITM_NEAR_LD_RETIRED, Load instruction architecturally executed,
snoop hit in near cache

# topic.topics[].topics[].topics[].topics[].label
​0x8306,
DSNP_HITM_FAR_LD_RETIRED, Load instruction architecturally executed,
snoop hit in far cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8306,
DSNP_HITM_FAR_LD_RETIRED, Load instruction architecturally executed,
snoop hit in far cache

# topic.topics[].topics[].topics[].topics[].label
​0x8307,
DSNP_HITM_REMOTE_LD_RETIRED, Load instruction architecturally executed,
snoop hit in remote cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8307,
DSNP_HITM_REMOTE_LD_RETIRED, Load instruction architecturally executed,
snoop hit in remote cache

# topic.topics[].topics[].topics[].topics[].label
​0x8308,
DSNP_HITM_ST_RETIRED, Store instruction architecturally executed, snoop
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8308,
DSNP_HITM_ST_RETIRED, Store instruction architecturally executed, snoop
hit

# topic.topics[].topics[].topics[].topics[].label
​0x8309,
DSNP_HITM_NEAR_ST_RETIRED, Store instruction architecturally executed,
snoop hit in near cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8309,
DSNP_HITM_NEAR_ST_RETIRED, Store instruction architecturally executed,
snoop hit in near cache

# topic.topics[].topics[].topics[].topics[].label
​0x830A,
DSNP_HITM_FAR_ST_RETIRED, Store instruction architecturally executed,
snoop hit in far cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x830A,
DSNP_HITM_FAR_ST_RETIRED, Store instruction architecturally executed,
snoop hit in far cache

# topic.topics[].topics[].topics[].topics[].label
​0x830B,
DSNP_HITM_REMOTE_ST_RETIRED, Store instruction architecturally executed,
snoop hit in remote cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x830B,
DSNP_HITM_REMOTE_ST_RETIRED, Store instruction architecturally executed,
snoop hit in remote cache

# topic.topics[].topics[].topics[].topics[].label
​0x830C,
DSNP_HITM_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x830C,
DSNP_HITM_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit

# topic.topics[].topics[].topics[].topics[].label
​0x830D,
DSNP_HITM_NEAR_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit in near cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x830D,
DSNP_HITM_NEAR_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit in near cache

# topic.topics[].topics[].topics[].topics[].label
​0x830E,
DSNP_HITM_FAR_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit in far cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x830E,
DSNP_HITM_FAR_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit in far cache

# topic.topics[].topics[].topics[].topics[].label
​0x830F,
DSNP_HITM_REMOTE_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit in remote cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x830F,
DSNP_HITM_REMOTE_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit in remote cache

# topic.topics[].topics[].topics[].topics[].label
​0x8310, ISNP_HIT_RETIRED,
Instruction architecturally executed, instruction fetch snoop
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8310, ISNP_HIT_RETIRED,
Instruction architecturally executed, instruction fetch snoop
hit

# topic.topics[].topics[].topics[].topics[].label
​0x8311,
ISNP_HIT_NEAR_RETIRED, Instruction architecturally executed, instruction
fetch snoop hit in near cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8311,
ISNP_HIT_NEAR_RETIRED, Instruction architecturally executed, instruction
fetch snoop hit in near cache

# topic.topics[].topics[].topics[].topics[].label
​0x8312,
ISNP_HIT_FAR_RETIRED, Instruction architecturally executed, instruction
fetch snoop hit in far cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8312,
ISNP_HIT_FAR_RETIRED, Instruction architecturally executed, instruction
fetch snoop hit in far cache

# topic.topics[].topics[].topics[].topics[].label
​0x8313,
ISNP_HIT_REMOTE_RETIRED, Instruction architecturally executed,
instruction fetch snoop hit in remote cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8313,
ISNP_HIT_REMOTE_RETIRED, Instruction architecturally executed,
instruction fetch snoop hit in remote cache

# topic.topics[].topics[].topics[].topics[].label
​0x8314,
DSNP_HIT_LD_RETIRED, Load instruction architecturally executed, snoop
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8314,
DSNP_HIT_LD_RETIRED, Load instruction architecturally executed, snoop
hit

# topic.topics[].topics[].topics[].topics[].label
​0x8315,
DSNP_HIT_NEAR_LD_RETIRED, Load instruction architecturally executed,
snoop hit in near cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8315,
DSNP_HIT_NEAR_LD_RETIRED, Load instruction architecturally executed,
snoop hit in near cache

# topic.topics[].topics[].topics[].topics[].label
​0x8316,
DSNP_HIT_FAR_LD_RETIRED, Load instruction architecturally executed,
snoop hit in far cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8316,
DSNP_HIT_FAR_LD_RETIRED, Load instruction architecturally executed,
snoop hit in far cache

# topic.topics[].topics[].topics[].topics[].label
​0x8317,
DSNP_HIT_REMOTE_LD_RETIRED, Load instruction architecturally executed,
snoop hit in remote cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8317,
DSNP_HIT_REMOTE_LD_RETIRED, Load instruction architecturally executed,
snoop hit in remote cache

# topic.topics[].topics[].topics[].topics[].label
​0x8318,
DSNP_HIT_ST_RETIRED, Store instruction architecturally executed, snoop
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8318,
DSNP_HIT_ST_RETIRED, Store instruction architecturally executed, snoop
hit

# topic.topics[].topics[].topics[].topics[].label
​0x8319,
DSNP_HIT_NEAR_ST_RETIRED, Store instruction architecturally executed,
snoop hit in near cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8319,
DSNP_HIT_NEAR_ST_RETIRED, Store instruction architecturally executed,
snoop hit in near cache

# topic.topics[].topics[].topics[].topics[].label
​0x831A,
DSNP_HIT_FAR_ST_RETIRED, Store instruction architecturally executed,
snoop hit in far cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x831A,
DSNP_HIT_FAR_ST_RETIRED, Store instruction architecturally executed,
snoop hit in far cache

# topic.topics[].topics[].topics[].topics[].label
​0x831B,
DSNP_HIT_REMOTE_ST_RETIRED, Store instruction architecturally executed,
snoop hit in remote cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x831B,
DSNP_HIT_REMOTE_ST_RETIRED, Store instruction architecturally executed,
snoop hit in remote cache

# topic.topics[].topics[].topics[].topics[].label
​0x831C,
DSNP_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x831C,
DSNP_HIT_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit

# topic.topics[].topics[].topics[].topics[].label
​0x831D,
DSNP_HIT_NEAR_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit in near cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x831D,
DSNP_HIT_NEAR_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit in near cache

# topic.topics[].topics[].topics[].topics[].label
​0x831E,
DSNP_HIT_FAR_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit in far cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x831E,
DSNP_HIT_FAR_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit in far cache

# topic.topics[].topics[].topics[].topics[].label
​0x831F,
DSNP_HIT_REMOTE_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit in remote cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x831F,
DSNP_HIT_REMOTE_LDST_RETIRED, Load or store instruction architecturally
executed, snoop hit in remote cache

# topic.topics[].topics[].topics[].topics[].label
​0x8320,
L1D_CACHE_REFILL_PERCYC, Level 1 data or unified cache refills in
progress

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8320,
L1D_CACHE_REFILL_PERCYC, Level 1 data or unified cache refills in
progress

# topic.topics[].topics[].topics[].topics[].label
​0x8321,
L2D_CACHE_REFILL_PERCYC, Level 2 data or unified cache refills in
progress

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8321,
L2D_CACHE_REFILL_PERCYC, Level 2 data or unified cache refills in
progress

# topic.topics[].topics[].topics[].topics[].label
​0x8322,
L3D_CACHE_REFILL_PERCYC, Level 3 data or unified cache refills in
progress

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8322,
L3D_CACHE_REFILL_PERCYC, Level 3 data or unified cache refills in
progress

# topic.topics[].topics[].topics[].topics[].label
​0x8324,
L1I_CACHE_REFILL_PERCYC, Level 1 instruction or unified cache refills in
progress

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8324,
L1I_CACHE_REFILL_PERCYC, Level 1 instruction or unified cache refills in
progress

# topic.topics[].topics[].topics[].topics[].label
​0x8325,
L2I_CACHE_REFILL_PERCYC, Level 2 instruction or unified cache refills in
progress

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8325,
L2I_CACHE_REFILL_PERCYC, Level 2 instruction or unified cache refills in
progress

# topic.topics[].topics[].topics[].topics[].label
​0x8328,
REMOTE_CACHE_HIT_RD, Remote cache demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8328,
REMOTE_CACHE_HIT_RD, Remote cache demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x8329,
REMOTE_CACHE_HITM_RD, Remote cache demand access hit modified,
read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8329,
REMOTE_CACHE_HITM_RD, Remote cache demand access hit modified,
read

# topic.topics[].topics[].topics[].topics[].label
​0x832A, REMOTE_LFB_HIT_RD,
Remote cache demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x832A, REMOTE_LFB_HIT_RD,
Remote cache demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x832B,
REMOTE_CACHE_HIT_PRFM, Remote cache software prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x832B,
REMOTE_CACHE_HIT_PRFM, Remote cache software prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x832C,
STALL_BACKEND_ATOMIC_FP, Backend stall cycles, atomic in-memory
floating-point load or store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x832C,
STALL_BACKEND_ATOMIC_FP, Backend stall cycles, atomic in-memory
floating-point load or store

# topic.topics[].topics[].topics[].topics[].label
​0x832D, LSE_FP_LD_SPEC,
Atomic in-memory floating-point Operation speculatively executed,
load

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x832D, LSE_FP_LD_SPEC,
Atomic in-memory floating-point Operation speculatively executed,
load

# topic.topics[].topics[].topics[].topics[].label
​0x832E, LSE_FP_ST_SPEC,
Atomic in-memory floating-point Operation speculatively executed,
store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x832E, LSE_FP_ST_SPEC,
Atomic in-memory floating-point Operation speculatively executed,
store

# topic.topics[].topics[].topics[].topics[].label
​0x832F, LSE_FP_LDST_SPEC,
Atomic in-memory floating-point Operation speculatively executed, load
or store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x832F, LSE_FP_LDST_SPEC,
Atomic in-memory floating-point Operation speculatively executed, load
or store

# topic.topics[].topics[].topics[].topics[].label
​0x8330, L1GCS_CACHE, Level 1 GCS
cache access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8330, L1GCS_CACHE, Level 1 GCS
cache access

# topic.topics[].topics[].topics[].topics[].label
​0x8331, L1GCS_CACHE_RW, Level
1 GCS cache demand access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8331, L1GCS_CACHE_RW, Level
1 GCS cache demand access

# topic.topics[].topics[].topics[].topics[].label
​0x8332, L1GCS_CACHE_HWPRF,
Level 1 GCS cache hardware prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8332, L1GCS_CACHE_HWPRF,
Level 1 GCS cache hardware prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8334, L1GCS_CACHE_MISS,
Level 1 GCS cache demand access miss

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8334, L1GCS_CACHE_MISS,
Level 1 GCS cache demand access miss

# topic.topics[].topics[].topics[].topics[].label
​0x8335,
L1GCS_CACHE_MISS_RD, Level 1 GCS cache demand access read miss

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8335,
L1GCS_CACHE_MISS_RD, Level 1 GCS cache demand access read miss

# topic.topics[].topics[].topics[].topics[].label
​0x8336,
L1GCS_CACHE_HIT_RW, Level 1 GCS cache demand access hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8336,
L1GCS_CACHE_HIT_RW, Level 1 GCS cache demand access hit

# topic.topics[].topics[].topics[].topics[].label
​0x8337,
L1GCS_CACHE_HIT_RW_FHWPRF, Level 1 GCS cache demand access first hit,
fetched by GCS hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8337,
L1GCS_CACHE_HIT_RW_FHWPRF, Level 1 GCS cache demand access first hit,
fetched by GCS hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x8338,
L1GCS_CACHE_REFILL, Level 1 GCS cache refill

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8338,
L1GCS_CACHE_REFILL, Level 1 GCS cache refill

# topic.topics[].topics[].topics[].topics[].label
​0x8339,
L1GCS_CACHE_REFILL_HWPRF, Level 1 GCS cache refill, hardware
prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8339,
L1GCS_CACHE_REFILL_HWPRF, Level 1 GCS cache refill, hardware
prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x833A,
L1GCS_CACHE_REFILL_PERCYC, Level 1 GCS cache refills in
progress

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x833A,
L1GCS_CACHE_REFILL_PERCYC, Level 1 GCS cache refills in
progress

# topic.topics[].topics[].topics[].topics[].label
​0x833C, L1GCS_LFB_HIT_RW,
Level 1 GCS cache demand access line-fill buffer hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x833C, L1GCS_LFB_HIT_RW,
Level 1 GCS cache demand access line-fill buffer hit

# topic.topics[].topics[].topics[].topics[].label
​0x833D,
L1GCS_LFB_HIT_RW_FHWPRF, Level 1 GCS cache demand access line-fill
buffer first hit, recently fetched by GCS hardware prefetcher

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x833D,
L1GCS_LFB_HIT_RW_FHWPRF, Level 1 GCS cache demand access line-fill
buffer first hit, recently fetched by GCS hardware prefetcher

# topic.topics[].topics[].topics[].topics[].label
​0x833E, L1GCS_CACHE_INVAL,
Level 1 GCS cache invalidate

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x833E, L1GCS_CACHE_INVAL,
Level 1 GCS cache invalidate

# topic.topics[].topics[].topics[].topics[].label
​0x8340, L1GCS_TLB, Level 1 GCS TLB
access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8340, L1GCS_TLB, Level 1 GCS TLB
access

# topic.topics[].topics[].topics[].topics[].label
​0x8341, L1GCS_TLB_RW, Level 1
GCS demand TLB access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8341, L1GCS_TLB_RW, Level 1
GCS demand TLB access

# topic.topics[].topics[].topics[].topics[].label
​0x8342, L1GCS_TLB_HWPRF,
Level 1 GCS demand TLB access, GCS hardware prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8342, L1GCS_TLB_HWPRF,
Level 1 GCS demand TLB access, GCS hardware prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8344, GCSTLB_WALK, GCS TLB
access with at least one translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8344, GCSTLB_WALK, GCS TLB
access with at least one translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x8345, GCSTLB_WALK_RW, GCS
TLB demand access with at least one translation table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8345, GCSTLB_WALK_RW, GCS
TLB demand access with at least one translation table walk

# topic.topics[].topics[].topics[].topics[].label
​0x8346,
GCSTLB_WALK_PERCYC, Translation table walks in progress

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8346,
GCSTLB_WALK_PERCYC, Translation table walks in progress

# topic.topics[].topics[].topics[].topics[].label
​0x8347, GCSTLB_WALK_STEP,
GCS TLB translation table walk, step

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8347, GCSTLB_WALK_STEP,
GCS TLB translation table walk, step

# topic.topics[].topics[].topics[].topics[].label
​0x8349, SAMPLE_FEED_SIMD,
Statistical Profiling sample taken, SIMD

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8349, SAMPLE_FEED_SIMD,
Statistical Profiling sample taken, SIMD

# topic.topics[].topics[].topics[].topics[].label
​0x8350,
STALL_BACKEND_L1GCS, Backend stall cycles, Level 1 GCS cache

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8350,
STALL_BACKEND_L1GCS, Backend stall cycles, Level 1 GCS cache

# topic.topics[].topics[].topics[].topics[].label
​0x8351,
STALL_BACKEND_GCSTLB, Backend stall cycles, GCS TLB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8351,
STALL_BACKEND_GCSTLB, Backend stall cycles, GCS TLB

# topic.topics[].topics[].topics[].topics[].label
​0x8353, SE_FP_SPEC, Operation
speculatively executed, Advanced SIMD, SVE, or SME SIMD floating-point,
data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8353, SE_FP_SPEC, Operation
speculatively executed, Advanced SIMD, SVE, or SME SIMD floating-point,
data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x8356, SVE_BITPERM_SPEC,
Operation speculatively executed, SVE in-element permute

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8356, SVE_BITPERM_SPEC,
Operation speculatively executed, SVE in-element permute

# topic.topics[].topics[].topics[].topics[].label
​0x835C, SME_SPEC, Operation
speculatively executed, SME data processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x835C, SME_SPEC, Operation
speculatively executed, SME data processing

# topic.topics[].topics[].topics[].topics[].label
​0x835D, SE_SPEC, Operation
speculatively executed, Advanced SIMD, SVE, or SME data
processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x835D, SE_SPEC, Operation
speculatively executed, Advanced SIMD, SVE, or SME data
processing

# topic.topics[].topics[].topics[].topics[].label
​0x835F, SE_INST_SPEC, Operation
speculatively executed, Advanced SIMD, SVE, or SME

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x835F, SE_INST_SPEC, Operation
speculatively executed, Advanced SIMD, SVE, or SME

# topic.topics[].topics[].topics[].topics[].label
​0x8360, SME_INT8_SPEC,
Operation speculatively executed, SME 8-bit integer,
data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8360, SME_INT8_SPEC,
Operation speculatively executed, SME 8-bit integer,
data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x8361, SE_INT8_SPEC, Operation
speculatively executed, Advanced SIMD, SVE, or SME SIMD 8-bit integer,
data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8361, SE_INT8_SPEC, Operation
speculatively executed, Advanced SIMD, SVE, or SME SIMD 8-bit integer,
data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x8363, SE_FP_BF16_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
BFloat16 floating-point, data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8363, SE_FP_BF16_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
BFloat16 floating-point, data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x8364, SME_INT16_SPEC,
Operation speculatively executed, SME 16-bit integer,
data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8364, SME_INT16_SPEC,
Operation speculatively executed, SME 16-bit integer,
data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x8365, SE_INT16_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD 16-bit
integer, data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8365, SE_INT16_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD 16-bit
integer, data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x8367, SE_FP_HP_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
half-precision floating-point, data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8367, SE_FP_HP_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
half-precision floating-point, data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x8368, SME_INT32_SPEC,
Operation speculatively executed, SME 32-bit integer,
data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8368, SME_INT32_SPEC,
Operation speculatively executed, SME 32-bit integer,
data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x8369, SE_INT32_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD 32-bit
integer, data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8369, SE_INT32_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD 32-bit
integer, data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x836B, SE_FP_SP_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
single-precision floating-point, data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x836B, SE_FP_SP_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
single-precision floating-point, data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x836C, SME_INT64_SPEC,
Operation speculatively executed, SME 64-bit integer,
data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x836C, SME_INT64_SPEC,
Operation speculatively executed, SME 64-bit integer,
data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x836D, SE_INT64_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD 64-bit
integer, data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x836D, SE_INT64_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD 64-bit
integer, data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x836F, SE_FP_DP_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
double-precision floating-point, data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x836F, SE_FP_DP_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
double-precision floating-point, data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x8370,
SME_FP_ADDSUB_SPEC, Operation speculatively executed, SME floating-point
addition or subtraction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8370,
SME_FP_ADDSUB_SPEC, Operation speculatively executed, SME floating-point
addition or subtraction

# topic.topics[].topics[].topics[].topics[].label
​0x8371, SE_FP_ADDSUB_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
floating-point addition or subtraction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8371, SE_FP_ADDSUB_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
floating-point addition or subtraction

# topic.topics[].topics[].topics[].topics[].label
​0x8373, SE_FP_FMA_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
floating-point multiply-add or multiply-subtract

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8373, SE_FP_FMA_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
floating-point multiply-add or multiply-subtract

# topic.topics[].topics[].topics[].topics[].label
​0x8374, SME_FP_DOT_SPEC,
Operation speculatively executed, SME floating-point dot
product

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8374, SME_FP_DOT_SPEC,
Operation speculatively executed, SME floating-point dot
product

# topic.topics[].topics[].topics[].topics[].label
​0x8375, SE_FP_DOT_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
floating-point dot product

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8375, SE_FP_DOT_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
floating-point dot product

# topic.topics[].topics[].topics[].topics[].label
​0x8376, SME_FP_MOPA_SPEC,
Operation speculatively executed, SME floating-point outer product and
accumulate, or outer product and subtract

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8376, SME_FP_MOPA_SPEC,
Operation speculatively executed, SME floating-point outer product and
accumulate, or outer product and subtract

# topic.topics[].topics[].topics[].topics[].label
​0x8379, SE_INT_SPEC, Operation
speculatively executed, Advanced SIMD, SVE, or SME SIMD integer,
data-processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8379, SE_INT_SPEC, Operation
speculatively executed, Advanced SIMD, SVE, or SME SIMD integer,
data-processing

# topic.topics[].topics[].topics[].topics[].label
​0x837A, SME_INT_MUL_SPEC,
Operation speculatively executed, SME integer multiply or
multiply-accumulate

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x837A, SME_INT_MUL_SPEC,
Operation speculatively executed, SME integer multiply or
multiply-accumulate

# topic.topics[].topics[].topics[].topics[].label
​0x837B, SE_INT_MUL_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
integer multiply or multiply-accumulate

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x837B, SE_INT_MUL_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
integer multiply or multiply-accumulate

# topic.topics[].topics[].topics[].topics[].label
​0x837C, SME_INT_DOT_SPEC,
Operation speculatively executed, SME integer dot product

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x837C, SME_INT_DOT_SPEC,
Operation speculatively executed, SME integer dot product

# topic.topics[].topics[].topics[].topics[].label
​0x837D, SE_INT_DOT_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
integer dot product

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x837D, SE_INT_DOT_SPEC,
Operation speculatively executed, Advanced SIMD, SVE, or SME SIMD
integer dot product

# topic.topics[].topics[].topics[].topics[].label
​0x837E, SME_INT_MOPA_SPEC,
Operation speculatively executed, SME integer outer product and
accumulate, or outer product and subtract

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x837E, SME_INT_MOPA_SPEC,
Operation speculatively executed, SME integer outer product and
accumulate, or outer product and subtract

# topic.topics[].topics[].topics[].topics[].label
​0x8380, ZA_ACTIVE, CPU cycles, ZA
enabled

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8380, ZA_ACTIVE, CPU cycles, ZA
enabled

# topic.topics[].topics[].topics[].topics[].label
​0x8381,
SME_PRED2_NOT_FULL_SPEC, Operation speculatively executed, SME 2D
predicated with at least one inactive element

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8381,
SME_PRED2_NOT_FULL_SPEC, Operation speculatively executed, SME 2D
predicated with at least one inactive element

# topic.topics[].topics[].topics[].topics[].label
​0x8384, SME_PRED2_SPEC,
Operation speculatively executed, SME 2D predicated

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8384, SME_PRED2_SPEC,
Operation speculatively executed, SME 2D predicated

# topic.topics[].topics[].topics[].topics[].label
​0x8385,
SME_PRED2_EMPTY_SPEC, Operation speculatively executed, SME 2D
predicated with no active elements

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8385,
SME_PRED2_EMPTY_SPEC, Operation speculatively executed, SME 2D
predicated with no active elements

# topic.topics[].topics[].topics[].topics[].label
​0x8386,
SME_PRED2_FULL_SPEC, Operation speculatively executed, SME 2D predicated
with all active elements

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8386,
SME_PRED2_FULL_SPEC, Operation speculatively executed, SME 2D predicated
with all active elements

# topic.topics[].topics[].topics[].topics[].label
​0x8387,
SME_PRED2_PARTIAL_SPEC, Operation speculatively executed, SME 2D
predicated with partially active elements

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8387,
SME_PRED2_PARTIAL_SPEC, Operation speculatively executed, SME 2D
predicated with partially active elements

# topic.topics[].topics[].topics[].topics[].label
​0x8388,
SME_LDST_ZAREG_SPEC, SME ZA unpredicated load/store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8388,
SME_LDST_ZAREG_SPEC, SME ZA unpredicated load/store

# topic.topics[].topics[].topics[].topics[].label
​0x8389, SME_LD_ZAREG_SPEC,
SME ZA unpredicated load

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8389, SME_LD_ZAREG_SPEC,
SME ZA unpredicated load

# topic.topics[].topics[].topics[].topics[].label
​0x838A, SME_ST_ZAREG_SPEC,
SME ZA unpredicated store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x838A, SME_ST_ZAREG_SPEC,
SME ZA unpredicated store

# topic.topics[].topics[].topics[].topics[].label
​0x838C,
SME_LDST_ZTREG_SPEC, SME ZT unpredicated load/store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x838C,
SME_LDST_ZTREG_SPEC, SME ZT unpredicated load/store

# topic.topics[].topics[].topics[].topics[].label
​0x838D, SME_LD_ZTREG_SPEC,
SME ZT unpredicated load

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x838D, SME_LD_ZTREG_SPEC,
SME ZT unpredicated load

# topic.topics[].topics[].topics[].topics[].label
​0x838E, SME_ST_ZTREG_SPEC,
SME ZT unpredicated store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x838E, SME_ST_ZTREG_SPEC,
SME ZT unpredicated store

# topic.topics[].topics[].topics[].topics[].label
​0x8391, SME_LD_REG_SPEC, SME
unpredicated load

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8391, SME_LD_REG_SPEC, SME
unpredicated load

# topic.topics[].topics[].topics[].topics[].label
​0x8392, SME_ST_REG_SPEC, SME
unpredicated store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8392, SME_ST_REG_SPEC, SME
unpredicated store

# topic.topics[].topics[].topics[].topics[].label
​0x8394,
SME_LDST_TILE_SPEC, SME predicated tile load/store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8394,
SME_LDST_TILE_SPEC, SME predicated tile load/store

# topic.topics[].topics[].topics[].topics[].label
​0x8395, SME_LD_TILE_SPEC,
SME predicated tile load

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8395, SME_LD_TILE_SPEC,
SME predicated tile load

# topic.topics[].topics[].topics[].topics[].label
​0x8396, SME_ST_TILE_SPEC,
SME predicated tile store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8396, SME_ST_TILE_SPEC,
SME predicated tile store

# topic.topics[].topics[].topics[].topics[].label
​0x8398, ASE_LUT_SPEC, Lookup
table operation speculatively executed, Advanced SIMD data
processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8398, ASE_LUT_SPEC, Lookup
table operation speculatively executed, Advanced SIMD data
processing

# topic.topics[].topics[].topics[].topics[].label
​0x8399, SVE_LUT_SPEC, Lookup
table operation speculatively executed, SVE data processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8399, SVE_LUT_SPEC, Lookup
table operation speculatively executed, SVE data processing

# topic.topics[].topics[].topics[].topics[].label
​0x839A, SME_LUT_SPEC, Lookup
table operation speculatively executed, SME data processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x839A, SME_LUT_SPEC, Lookup
table operation speculatively executed, SME data processing

# topic.topics[].topics[].topics[].topics[].label
​0x839B, SE_LUT_SPEC, Lookup
table operation speculatively executed, Advanced SIMD, SVE, or SME data
processing

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x839B, SE_LUT_SPEC, Lookup
table operation speculatively executed, Advanced SIMD, SVE, or SME data
processing

# topic.topics[].topics[].topics[].topics[].label
​0x83A0, N1_CACHE_HIT_RD,
Cache at distance 1, demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83A0, N1_CACHE_HIT_RD,
Cache at distance 1, demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83A1, N2_CACHE_HIT_RD,
Cache at distance 2, demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83A1, N2_CACHE_HIT_RD,
Cache at distance 2, demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83A2, N3_CACHE_HIT_RD,
Cache at distance 3, demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83A2, N3_CACHE_HIT_RD,
Cache at distance 3, demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83A3, N4_CACHE_HIT_RD,
Cache at distance 4, demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83A3, N4_CACHE_HIT_RD,
Cache at distance 4, demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83A4, N1_CACHE_HIT_PRFM,
Cache at distance 1, software prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83A4, N1_CACHE_HIT_PRFM,
Cache at distance 1, software prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x83A5, N2_CACHE_HIT_PRFM,
Cache at distance 2, software prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83A5, N2_CACHE_HIT_PRFM,
Cache at distance 2, software prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x83A6, N3_CACHE_HIT_PRFM,
Cache at distance 3, software prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83A6, N3_CACHE_HIT_PRFM,
Cache at distance 3, software prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x83A7, N4_CACHE_HIT_PRFM,
Cache at distance 4, software prefetch hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83A7, N4_CACHE_HIT_PRFM,
Cache at distance 4, software prefetch hit

# topic.topics[].topics[].topics[].topics[].label
​0x83A8, N1_CACHE1_HIT_RD,
Cache type 1 at distance 1 demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83A8, N1_CACHE1_HIT_RD,
Cache type 1 at distance 1 demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83A9, N2_CACHE1_HIT_RD,
Cache type 1 at distance 2 demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83A9, N2_CACHE1_HIT_RD,
Cache type 1 at distance 2 demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83AA, N3_CACHE1_HIT_RD,
Cache type 1 at distance 3 demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83AA, N3_CACHE1_HIT_RD,
Cache type 1 at distance 3 demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83AB, N4_CACHE1_HIT_RD,
Cache type 1 at distance 4 demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83AB, N4_CACHE1_HIT_RD,
Cache type 1 at distance 4 demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83AC,
N1_CACHE1_HIT_PRFM, Cache type 1 at distance 1 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83AC,
N1_CACHE1_HIT_PRFM, Cache type 1 at distance 1 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x83AD,
N2_CACHE1_HIT_PRFM, Cache type 1 at distance 2 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83AD,
N2_CACHE1_HIT_PRFM, Cache type 1 at distance 2 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x83AE,
N3_CACHE1_HIT_PRFM, Cache type 1 at distance 3 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83AE,
N3_CACHE1_HIT_PRFM, Cache type 1 at distance 3 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x83AF,
N4_CACHE1_HIT_PRFM, Cache type 1 at distance 4 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83AF,
N4_CACHE1_HIT_PRFM, Cache type 1 at distance 4 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x83B0, N1_CACHE2_HIT_RD,
Cache type 2 at distance 1 demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83B0, N1_CACHE2_HIT_RD,
Cache type 2 at distance 1 demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83B1, N2_CACHE2_HIT_RD,
Cache type 2 at distance 2 demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83B1, N2_CACHE2_HIT_RD,
Cache type 2 at distance 2 demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83B2, N3_CACHE2_HIT_RD,
Cache type 2 at distance 3 demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83B2, N3_CACHE2_HIT_RD,
Cache type 2 at distance 3 demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83B3, N4_CACHE2_HIT_RD,
Cache type 2 at distance 4 demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83B3, N4_CACHE2_HIT_RD,
Cache type 2 at distance 4 demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83B4,
N1_CACHE2_HIT_PRFM, Cache type 2 at distance 1 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83B4,
N1_CACHE2_HIT_PRFM, Cache type 2 at distance 1 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x83B5,
N2_CACHE2_HIT_PRFM, Cache type 2 at distance 2 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83B5,
N2_CACHE2_HIT_PRFM, Cache type 2 at distance 2 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x83B6,
N3_CACHE2_HIT_PRFM, Cache type 2 at distance 3 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83B6,
N3_CACHE2_HIT_PRFM, Cache type 2 at distance 3 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x83B7,
N4_CACHE2_HIT_PRFM, Cache type 2 at distance 4 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83B7,
N4_CACHE2_HIT_PRFM, Cache type 2 at distance 4 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x83B8, N1_CACHE3_HIT_RD,
Cache type 3 at distance 1 demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83B8, N1_CACHE3_HIT_RD,
Cache type 3 at distance 1 demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83B9, N2_CACHE3_HIT_RD,
Cache type 3 at distance 2 demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83B9, N2_CACHE3_HIT_RD,
Cache type 3 at distance 2 demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83BA, N3_CACHE3_HIT_RD,
Cache type 3 at distance 3 demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83BA, N3_CACHE3_HIT_RD,
Cache type 3 at distance 3 demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83BB, N4_CACHE3_HIT_RD,
Cache type 3 at distance 4 demand access hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83BB, N4_CACHE3_HIT_RD,
Cache type 3 at distance 4 demand access hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83BC,
N1_CACHE3_HIT_PRFM, Cache type 3 at distance 1 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83BC,
N1_CACHE3_HIT_PRFM, Cache type 3 at distance 1 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x83BD,
N2_CACHE3_HIT_PRFM, Cache type 3 at distance 2 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83BD,
N2_CACHE3_HIT_PRFM, Cache type 3 at distance 2 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x83BE,
N3_CACHE3_HIT_PRFM, Cache type 3 at distance 3 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83BE,
N3_CACHE3_HIT_PRFM, Cache type 3 at distance 3 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x83BF,
N4_CACHE3_HIT_PRFM, Cache type 3 at distance 4 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83BF,
N4_CACHE3_HIT_PRFM, Cache type 3 at distance 4 software prefetch
hit

# topic.topics[].topics[].topics[].topics[].label
​0x83C0, N1_CACHE_HITM_RD,
Cache at distance 1, demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83C0, N1_CACHE_HITM_RD,
Cache at distance 1, demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83C1, N2_CACHE_HITM_RD,
Cache at distance 2, demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83C1, N2_CACHE_HITM_RD,
Cache at distance 2, demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83C2, N3_CACHE_HITM_RD,
Cache at distance 3, demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83C2, N3_CACHE_HITM_RD,
Cache at distance 3, demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83C3, N4_CACHE_HITM_RD,
Cache at distance 4, demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83C3, N4_CACHE_HITM_RD,
Cache at distance 4, demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83C4, N1_LFB_HIT_RD, Cache
at distance 1 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83C4, N1_LFB_HIT_RD, Cache
at distance 1 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83C5, N2_LFB_HIT_RD, Cache
at distance 2 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83C5, N2_LFB_HIT_RD, Cache
at distance 2 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83C6, N3_LFB_HIT_RD, Cache
at distance 3 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83C6, N3_LFB_HIT_RD, Cache
at distance 3 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83C7, N4_LFB_HIT_RD, Cache
at distance 4 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83C7, N4_LFB_HIT_RD, Cache
at distance 4 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83C8, N1_CACHE1_HITM_RD,
Cache type 1 at distance 1 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83C8, N1_CACHE1_HITM_RD,
Cache type 1 at distance 1 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83C9, N2_CACHE1_HITM_RD,
Cache type 1 at distance 2 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83C9, N2_CACHE1_HITM_RD,
Cache type 1 at distance 2 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83CA, N3_CACHE1_HITM_RD,
Cache type 1 at distance 3 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83CA, N3_CACHE1_HITM_RD,
Cache type 1 at distance 3 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83CB, N4_CACHE1_HITM_RD,
Cache type 1 at distance 4 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83CB, N4_CACHE1_HITM_RD,
Cache type 1 at distance 4 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83CC, N1_LFB1_HIT_RD, Cache
type 1 at distance 1 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83CC, N1_LFB1_HIT_RD, Cache
type 1 at distance 1 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83CD, N2_LFB1_HIT_RD, Cache
type 1 at distance 2 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83CD, N2_LFB1_HIT_RD, Cache
type 1 at distance 2 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83CE, N3_LFB1_HIT_RD, Cache
type 1 at distance 3 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83CE, N3_LFB1_HIT_RD, Cache
type 1 at distance 3 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83CF, N4_LFB1_HIT_RD, Cache
type 1 at distance 4 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83CF, N4_LFB1_HIT_RD, Cache
type 1 at distance 4 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83D0, N1_CACHE2_HITM_RD,
Cache type 2 at distance 1 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83D0, N1_CACHE2_HITM_RD,
Cache type 2 at distance 1 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83D1, N2_CACHE2_HITM_RD,
Cache type 2 at distance 2 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83D1, N2_CACHE2_HITM_RD,
Cache type 2 at distance 2 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83D2, N3_CACHE2_HITM_RD,
Cache type 2 at distance 3 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83D2, N3_CACHE2_HITM_RD,
Cache type 2 at distance 3 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83D3, N4_CACHE2_HITM_RD,
Cache type 2 at distance 4 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83D3, N4_CACHE2_HITM_RD,
Cache type 2 at distance 4 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83D4, N1_LFB2_HIT_RD, Cache
type 2 at distance 1 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83D4, N1_LFB2_HIT_RD, Cache
type 2 at distance 1 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83D5, N2_LFB2_HIT_RD, Cache
type 2 at distance 2 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83D5, N2_LFB2_HIT_RD, Cache
type 2 at distance 2 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83D6, N3_LFB2_HIT_RD, Cache
type 2 at distance 3 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83D6, N3_LFB2_HIT_RD, Cache
type 2 at distance 3 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83D7, N4_LFB2_HIT_RD, Cache
type 2 at distance 4 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83D7, N4_LFB2_HIT_RD, Cache
type 2 at distance 4 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83D8, N1_CACHE3_HITM_RD,
Cache type 3 at distance 1 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83D8, N1_CACHE3_HITM_RD,
Cache type 3 at distance 1 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83D9, N2_CACHE3_HITM_RD,
Cache type 3 at distance 2 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83D9, N2_CACHE3_HITM_RD,
Cache type 3 at distance 2 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83DA, N3_CACHE3_HITM_RD,
Cache type 3 at distance 3 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83DA, N3_CACHE3_HITM_RD,
Cache type 3 at distance 3 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83DB, N4_CACHE3_HITM_RD,
Cache type 3 at distance 4 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83DB, N4_CACHE3_HITM_RD,
Cache type 3 at distance 4 demand access hit modified, read

# topic.topics[].topics[].topics[].topics[].label
​0x83DC, N1_LFB3_HIT_RD, Cache
type 3 at distance 1 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83DC, N1_LFB3_HIT_RD, Cache
type 3 at distance 1 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83DD, N2_LFB3_HIT_RD, Cache
type 3 at distance 2 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83DD, N2_LFB3_HIT_RD, Cache
type 3 at distance 2 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83DE, N3_LFB3_HIT_RD, Cache
type 3 at distance 3 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83DE, N3_LFB3_HIT_RD, Cache
type 3 at distance 3 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83DF, N4_LFB3_HIT_RD, Cache
type 3 at distance 4 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83DF, N4_LFB3_HIT_RD, Cache
type 3 at distance 4 demand access line-fill buffer hit, read

# topic.topics[].topics[].topics[].topics[].label
​0x83E0, N1_MEM_RD, Access to
memory at distance 1, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83E0, N1_MEM_RD, Access to
memory at distance 1, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83E1, N2_MEM_RD, Access to
memory at distance 2, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83E1, N2_MEM_RD, Access to
memory at distance 2, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83E2, N3_MEM_RD, Access to
memory at distance 3, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83E2, N3_MEM_RD, Access to
memory at distance 3, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83E3, N4_MEM_RD, Access to
memory at distance 4, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83E3, N4_MEM_RD, Access to
memory at distance 4, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83E4, N1_MEM_PRFM, Access to
memory at distance 1, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83E4, N1_MEM_PRFM, Access to
memory at distance 1, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83E5, N2_MEM_PRFM, Access to
memory at distance 2, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83E5, N2_MEM_PRFM, Access to
memory at distance 2, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83E6, N3_MEM_PRFM, Access to
memory at distance 3, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83E6, N3_MEM_PRFM, Access to
memory at distance 3, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83E7, N4_MEM_PRFM, Access to
memory at distance 4, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83E7, N4_MEM_PRFM, Access to
memory at distance 4, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83E8, N1_MEM1_RD, Access to
type 1 memory at distance 1, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83E8, N1_MEM1_RD, Access to
type 1 memory at distance 1, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83E9, N2_MEM1_RD, Access to
type 1 memory at distance 2, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83E9, N2_MEM1_RD, Access to
type 1 memory at distance 2, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83EA, N3_MEM1_RD, Access to
type 1 memory at distance 3, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83EA, N3_MEM1_RD, Access to
type 1 memory at distance 3, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83EB, N4_MEM1_RD, Access to
type 1 memory at distance 4, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83EB, N4_MEM1_RD, Access to
type 1 memory at distance 4, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83EC, N1_MEM1_PRFM, Access to
type 1 memory at distance 1, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83EC, N1_MEM1_PRFM, Access to
type 1 memory at distance 1, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83ED, N2_MEM1_PRFM, Access to
type 1 memory at distance 2, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83ED, N2_MEM1_PRFM, Access to
type 1 memory at distance 2, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83EE, N3_MEM1_PRFM, Access to
type 1 memory at distance 3, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83EE, N3_MEM1_PRFM, Access to
type 1 memory at distance 3, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83EF, N4_MEM1_PRFM, Access to
type 1 memory at distance 4, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83EF, N4_MEM1_PRFM, Access to
type 1 memory at distance 4, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83F0, N1_MEM2_RD, Access to
type 2 memory at distance 1, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83F0, N1_MEM2_RD, Access to
type 2 memory at distance 1, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83F1, N2_MEM2_RD, Access to
type 2 memory at distance 2, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83F1, N2_MEM2_RD, Access to
type 2 memory at distance 2, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83F2, N3_MEM2_RD, Access to
type 2 memory at distance 3, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83F2, N3_MEM2_RD, Access to
type 2 memory at distance 3, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83F3, N4_MEM2_RD, Access to
type 2 memory at distance 4, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83F3, N4_MEM2_RD, Access to
type 2 memory at distance 4, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83F4, N1_MEM2_PRFM, Access to
type 2 memory at distance 1, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83F4, N1_MEM2_PRFM, Access to
type 2 memory at distance 1, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83F5, N2_MEM2_PRFM, Access to
type 2 memory at distance 2, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83F5, N2_MEM2_PRFM, Access to
type 2 memory at distance 2, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83F6, N3_MEM2_PRFM, Access to
type 2 memory at distance 3, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83F6, N3_MEM2_PRFM, Access to
type 2 memory at distance 3, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83F7, N4_MEM2_PRFM, Access to
type 2 memory at distance 4, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83F7, N4_MEM2_PRFM, Access to
type 2 memory at distance 4, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83F8, N1_MEM3_RD, Access to
type 3 memory at distance 1, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83F8, N1_MEM3_RD, Access to
type 3 memory at distance 1, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83F9, N2_MEM3_RD, Access to
type 3 memory at distance 2, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83F9, N2_MEM3_RD, Access to
type 3 memory at distance 2, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83FA, N3_MEM3_RD, Access to
type 3 memory at distance 3, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83FA, N3_MEM3_RD, Access to
type 3 memory at distance 3, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83FB, N4_MEM3_RD, Access to
type 3 memory at distance 4, demand access, read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83FB, N4_MEM3_RD, Access to
type 3 memory at distance 4, demand access, read

# topic.topics[].topics[].topics[].topics[].label
​0x83FC, N1_MEM3_PRFM, Access to
type 3 memory at distance 1, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83FC, N1_MEM3_PRFM, Access to
type 3 memory at distance 1, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83FD, N2_MEM3_PRFM, Access to
type 3 memory at distance 2, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83FD, N2_MEM3_PRFM, Access to
type 3 memory at distance 2, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83FE, N3_MEM3_PRFM, Access to
type 3 memory at distance 3, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83FE, N3_MEM3_PRFM, Access to
type 3 memory at distance 3, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x83FF, N4_MEM3_PRFM, Access to
type 3 memory at distance 4, software prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x83FF, N4_MEM3_PRFM, Access to
type 3 memory at distance 4, software prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8400, ISNP_HIT_N1_RD, Snoop
hit in cache at distance 1, demand instruction fetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8400, ISNP_HIT_N1_RD, Snoop
hit in cache at distance 1, demand instruction fetch

# topic.topics[].topics[].topics[].topics[].label
​0x8401, ISNP_HIT_N2_RD, Snoop
hit in cache at distance 2, demand instruction fetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8401, ISNP_HIT_N2_RD, Snoop
hit in cache at distance 2, demand instruction fetch

# topic.topics[].topics[].topics[].topics[].label
​0x8402, ISNP_HIT_N3_RD, Snoop
hit in cache at distance 3, demand instruction fetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8402, ISNP_HIT_N3_RD, Snoop
hit in cache at distance 3, demand instruction fetch

# topic.topics[].topics[].topics[].topics[].label
​0x8403, ISNP_HIT_N4_RD, Snoop
hit in cache at distance 4, demand instruction fetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8403, ISNP_HIT_N4_RD, Snoop
hit in cache at distance 4, demand instruction fetch

# topic.topics[].topics[].topics[].topics[].label
​0x8404, DSNP_HIT_N1_RD, Snoop
hit in cache at distance 1, demand data read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8404, DSNP_HIT_N1_RD, Snoop
hit in cache at distance 1, demand data read

# topic.topics[].topics[].topics[].topics[].label
​0x8405, DSNP_HIT_N2_RD, Snoop
hit in cache at distance 2, demand data read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8405, DSNP_HIT_N2_RD, Snoop
hit in cache at distance 2, demand data read

# topic.topics[].topics[].topics[].topics[].label
​0x8406, DSNP_HIT_N3_RD, Snoop
hit in cache at distance 3, demand data read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8406, DSNP_HIT_N3_RD, Snoop
hit in cache at distance 3, demand data read

# topic.topics[].topics[].topics[].topics[].label
​0x8407, DSNP_HIT_N4_RD, Snoop
hit in cache at distance 4, demand data read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8407, DSNP_HIT_N4_RD, Snoop
hit in cache at distance 4, demand data read

# topic.topics[].topics[].topics[].topics[].label
​0x8408, DSNP_HIT_N1_WR, Snoop
hit in cache at distance 1, demand data write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8408, DSNP_HIT_N1_WR, Snoop
hit in cache at distance 1, demand data write

# topic.topics[].topics[].topics[].topics[].label
​0x8409, DSNP_HIT_N2_WR, Snoop
hit in cache at distance 2, demand data write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8409, DSNP_HIT_N2_WR, Snoop
hit in cache at distance 2, demand data write

# topic.topics[].topics[].topics[].topics[].label
​0x840A, DSNP_HIT_N3_WR, Snoop
hit in cache at distance 3, demand data write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x840A, DSNP_HIT_N3_WR, Snoop
hit in cache at distance 3, demand data write

# topic.topics[].topics[].topics[].topics[].label
​0x840B, DSNP_HIT_N4_WR, Snoop
hit in cache at distance 4, demand data write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x840B, DSNP_HIT_N4_WR, Snoop
hit in cache at distance 4, demand data write

# topic.topics[].topics[].topics[].topics[].label
​0x840C, DSNP_HIT_N1_RW, Snoop
hit in cache at distance 1, demand data access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x840C, DSNP_HIT_N1_RW, Snoop
hit in cache at distance 1, demand data access

# topic.topics[].topics[].topics[].topics[].label
​0x840D, DSNP_HIT_N2_RW, Snoop
hit in cache at distance 2, demand data access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x840D, DSNP_HIT_N2_RW, Snoop
hit in cache at distance 2, demand data access

# topic.topics[].topics[].topics[].topics[].label
​0x840E, DSNP_HIT_N3_RW, Snoop
hit in cache at distance 3, demand data access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x840E, DSNP_HIT_N3_RW, Snoop
hit in cache at distance 3, demand data access

# topic.topics[].topics[].topics[].topics[].label
​0x840F, DSNP_HIT_N4_RW, Snoop
hit in cache at distance 4, demand data access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x840F, DSNP_HIT_N4_RW, Snoop
hit in cache at distance 4, demand data access

# topic.topics[].topics[].topics[].topics[].label
​0x8410, DSNP_HIT_N1_PRFM,
Snoop hit in cache at distance 1, software data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8410, DSNP_HIT_N1_PRFM,
Snoop hit in cache at distance 1, software data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8411, DSNP_HIT_N2_PRFM,
Snoop hit in cache at distance 2, software data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8411, DSNP_HIT_N2_PRFM,
Snoop hit in cache at distance 2, software data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8412, DSNP_HIT_N3_PRFM,
Snoop hit in cache at distance 3, software data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8412, DSNP_HIT_N3_PRFM,
Snoop hit in cache at distance 3, software data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8413, DSNP_HIT_N4_PRFM,
Snoop hit in cache at distance 4, software data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8413, DSNP_HIT_N4_PRFM,
Snoop hit in cache at distance 4, software data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8414, DSNP_HIT_N1_HWPRF,
Snoop hit in cache at distance 1, hardware data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8414, DSNP_HIT_N1_HWPRF,
Snoop hit in cache at distance 1, hardware data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8415, DSNP_HIT_N2_HWPRF,
Snoop hit in cache at distance 2, hardware data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8415, DSNP_HIT_N2_HWPRF,
Snoop hit in cache at distance 2, hardware data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8416, DSNP_HIT_N3_HWPRF,
Snoop hit in cache at distance 3, hardware data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8416, DSNP_HIT_N3_HWPRF,
Snoop hit in cache at distance 3, hardware data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8417, DSNP_HIT_N4_HWPRF,
Snoop hit in cache at distance 4, hardware data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8417, DSNP_HIT_N4_HWPRF,
Snoop hit in cache at distance 4, hardware data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8418, ISNP_HIT_N1_PRFM,
Snoop hit in cache at distance 1, software instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8418, ISNP_HIT_N1_PRFM,
Snoop hit in cache at distance 1, software instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8419, ISNP_HIT_N2_PRFM,
Snoop hit in cache at distance 2, software instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8419, ISNP_HIT_N2_PRFM,
Snoop hit in cache at distance 2, software instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x841A, ISNP_HIT_N3_PRFM,
Snoop hit in cache at distance 3, software instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x841A, ISNP_HIT_N3_PRFM,
Snoop hit in cache at distance 3, software instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x841B, ISNP_HIT_N4_PRFM,
Snoop hit in cache at distance 4, software instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x841B, ISNP_HIT_N4_PRFM,
Snoop hit in cache at distance 4, software instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x841C, ISNP_HIT_N1_HWPRF,
Snoop hit in cache at distance 1, hardware instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x841C, ISNP_HIT_N1_HWPRF,
Snoop hit in cache at distance 1, hardware instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x841D, ISNP_HIT_N2_HWPRF,
Snoop hit in cache at distance 2, hardware instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x841D, ISNP_HIT_N2_HWPRF,
Snoop hit in cache at distance 2, hardware instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x841E, ISNP_HIT_N3_HWPRF,
Snoop hit in cache at distance 3, hardware instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x841E, ISNP_HIT_N3_HWPRF,
Snoop hit in cache at distance 3, hardware instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x841F, ISNP_HIT_N4_HWPRF,
Snoop hit in cache at distance 4, hardware instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x841F, ISNP_HIT_N4_HWPRF,
Snoop hit in cache at distance 4, hardware instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8420, DSNP_HIT_N1_PRF,
Snoop hit in cache at distance 1, data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8420, DSNP_HIT_N1_PRF,
Snoop hit in cache at distance 1, data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8421, DSNP_HIT_N2_PRF,
Snoop hit in cache at distance 2, data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8421, DSNP_HIT_N2_PRF,
Snoop hit in cache at distance 2, data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8422, DSNP_HIT_N3_PRF,
Snoop hit in cache at distance 3, data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8422, DSNP_HIT_N3_PRF,
Snoop hit in cache at distance 3, data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8423, DSNP_HIT_N4_PRF,
Snoop hit in cache at distance 4, data prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8423, DSNP_HIT_N4_PRF,
Snoop hit in cache at distance 4, data prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8424, ISNP_HIT_N1_PRF,
Snoop hit in cache at distance 1, instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8424, ISNP_HIT_N1_PRF,
Snoop hit in cache at distance 1, instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8425, ISNP_HIT_N2_PRF,
Snoop hit in cache at distance 2, instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8425, ISNP_HIT_N2_PRF,
Snoop hit in cache at distance 2, instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8426, ISNP_HIT_N3_PRF,
Snoop hit in cache at distance 3, instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8426, ISNP_HIT_N3_PRF,
Snoop hit in cache at distance 3, instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8427, ISNP_HIT_N4_PRF,
Snoop hit in cache at distance 4, instruction prefetch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8427, ISNP_HIT_N4_PRF,
Snoop hit in cache at distance 4, instruction prefetch

# topic.topics[].topics[].topics[].topics[].label
​0x8428, ISNP_HIT_N1, Snoop hit
in cache at distance 1, instruction access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8428, ISNP_HIT_N1, Snoop hit
in cache at distance 1, instruction access

# topic.topics[].topics[].topics[].topics[].label
​0x8429, ISNP_HIT_N2, Snoop hit
in cache at distance 2, instruction access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8429, ISNP_HIT_N2, Snoop hit
in cache at distance 2, instruction access

# topic.topics[].topics[].topics[].topics[].label
​0x842A, ISNP_HIT_N3, Snoop hit
in cache at distance 3, instruction access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x842A, ISNP_HIT_N3, Snoop hit
in cache at distance 3, instruction access

# topic.topics[].topics[].topics[].topics[].label
​0x842B, ISNP_HIT_N4, Snoop hit
in cache at distance 4, instruction access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x842B, ISNP_HIT_N4, Snoop hit
in cache at distance 4, instruction access

# topic.topics[].topics[].topics[].topics[].label
​0x842C, DSNP_HIT_N1, Snoop hit
in cache at distance 1, data access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x842C, DSNP_HIT_N1, Snoop hit
in cache at distance 1, data access

# topic.topics[].topics[].topics[].topics[].label
​0x842D, DSNP_HIT_N2, Snoop hit
in cache at distance 2, data access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x842D, DSNP_HIT_N2, Snoop hit
in cache at distance 2, data access

# topic.topics[].topics[].topics[].topics[].label
​0x842E, DSNP_HIT_N3, Snoop hit
in cache at distance 3, data access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x842E, DSNP_HIT_N3, Snoop hit
in cache at distance 3, data access

# topic.topics[].topics[].topics[].topics[].label
​0x842F, DSNP_HIT_N4, Snoop hit
in cache at distance 4, data access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x842F, DSNP_HIT_N4, Snoop hit
in cache at distance 4, data access

# topic.topics[].topics[].topics[].topics[].label
​0x8431,
ASE_FP_VREDUCE_SPEC, Floating-point operation speculatively executed,
Advanced SIMD pairwise or reduction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8431,
ASE_FP_VREDUCE_SPEC, Floating-point operation speculatively executed,
Advanced SIMD pairwise or reduction

# topic.topics[].topics[].topics[].topics[].label
​0x8432,
SVE_FP_PREDUCE_SPEC, Floating-point operation speculatively executed,
SVE pairwise add step or pairwise reduce step

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8432,
SVE_FP_PREDUCE_SPEC, Floating-point operation speculatively executed,
SVE pairwise add step or pairwise reduce step

# topic.topics[].topics[].topics[].topics[].label
​0x8434, DSNP_HITM_N1_RD,
Snoop hit in cache at distance 1, demand data read, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8434, DSNP_HITM_N1_RD,
Snoop hit in cache at distance 1, demand data read, modified

# topic.topics[].topics[].topics[].topics[].label
​0x8435, DSNP_HITM_N2_RD,
Snoop hit in cache at distance 2, demand data read, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8435, DSNP_HITM_N2_RD,
Snoop hit in cache at distance 2, demand data read, modified

# topic.topics[].topics[].topics[].topics[].label
​0x8436, DSNP_HITM_N3_RD,
Snoop hit in cache at distance 3, demand data read, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8436, DSNP_HITM_N3_RD,
Snoop hit in cache at distance 3, demand data read, modified

# topic.topics[].topics[].topics[].topics[].label
​0x8437, DSNP_HITM_N4_RD,
Snoop hit in cache at distance 4, demand data read, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8437, DSNP_HITM_N4_RD,
Snoop hit in cache at distance 4, demand data read, modified

# topic.topics[].topics[].topics[].topics[].label
​0x8438, DSNP_HITM_N1_WR,
Snoop hit in cache at distance 1, demand data write, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8438, DSNP_HITM_N1_WR,
Snoop hit in cache at distance 1, demand data write, modified

# topic.topics[].topics[].topics[].topics[].label
​0x8439, DSNP_HITM_N2_WR,
Snoop hit in cache at distance 2, demand data write, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8439, DSNP_HITM_N2_WR,
Snoop hit in cache at distance 2, demand data write, modified

# topic.topics[].topics[].topics[].topics[].label
​0x843A, DSNP_HITM_N3_WR,
Snoop hit in cache at distance 3, demand data write, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x843A, DSNP_HITM_N3_WR,
Snoop hit in cache at distance 3, demand data write, modified

# topic.topics[].topics[].topics[].topics[].label
​0x843B, DSNP_HITM_N4_WR,
Snoop hit in cache at distance 4, demand data write, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x843B, DSNP_HITM_N4_WR,
Snoop hit in cache at distance 4, demand data write, modified

# topic.topics[].topics[].topics[].topics[].label
​0x843C, DSNP_HITM_N1_RW,
Snoop hit in cache at distance 1, demand data access, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x843C, DSNP_HITM_N1_RW,
Snoop hit in cache at distance 1, demand data access, modified

# topic.topics[].topics[].topics[].topics[].label
​0x843D, DSNP_HITM_N2_RW,
Snoop hit in cache at distance 2, demand data access, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x843D, DSNP_HITM_N2_RW,
Snoop hit in cache at distance 2, demand data access, modified

# topic.topics[].topics[].topics[].topics[].label
​0x843E, DSNP_HITM_N3_RW,
Snoop hit in cache at distance 3, demand data access, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x843E, DSNP_HITM_N3_RW,
Snoop hit in cache at distance 3, demand data access, modified

# topic.topics[].topics[].topics[].topics[].label
​0x843F, DSNP_HITM_N4_RW,
Snoop hit in cache at distance 4, demand data access, modified

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x843F, DSNP_HITM_N4_RW,
Snoop hit in cache at distance 4, demand data access, modified

# topic.topics[].topics[].topics[].topics[].label
​0x8440,
ASE_FP_SP_MIN_SPEC, Advanced SIMD data processing operation
speculatively executed, smallest type is single-precision
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8440,
ASE_FP_SP_MIN_SPEC, Advanced SIMD data processing operation
speculatively executed, smallest type is single-precision
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8442,
ASE_FP_HP_MIN_SPEC, Advanced SIMD data processing operation
speculatively executed, smallest type is half-precision
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8442,
ASE_FP_HP_MIN_SPEC, Advanced SIMD data processing operation
speculatively executed, smallest type is half-precision
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8443,
ASE_FP_BF16_MIN_SPEC, Advanced SIMD data processing operation
speculatively executed, smallest type is BFloat16
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8443,
ASE_FP_BF16_MIN_SPEC, Advanced SIMD data processing operation
speculatively executed, smallest type is BFloat16
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8444,
ASE_FP_FP8_MIN_SPEC, Advanced SIMD data processing operation
speculatively executed, smallest type is 8-bit floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8444,
ASE_FP_FP8_MIN_SPEC, Advanced SIMD data processing operation
speculatively executed, smallest type is 8-bit floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8448,
ASE_SVE_FP_SP_MIN_SPEC, Advanced SIMD data processing or SVE data
processing operation speculatively executed, smallest type is
single-precision floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8448,
ASE_SVE_FP_SP_MIN_SPEC, Advanced SIMD data processing or SVE data
processing operation speculatively executed, smallest type is
single-precision floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x844A,
ASE_SVE_FP_HP_MIN_SPEC, Advanced SIMD data processing or SVE data
processing operation speculatively executed, smallest type is
half-precision floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x844A,
ASE_SVE_FP_HP_MIN_SPEC, Advanced SIMD data processing or SVE data
processing operation speculatively executed, smallest type is
half-precision floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x844B,
ASE_SVE_FP_BF16_MIN_SPEC, Advanced SIMD data processing or SVE data
processing operation speculatively executed, smallest type is BFloat16
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x844B,
ASE_SVE_FP_BF16_MIN_SPEC, Advanced SIMD data processing or SVE data
processing operation speculatively executed, smallest type is BFloat16
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x844C,
ASE_SVE_FP_FP8_MIN_SPEC, Advanced SIMD data processing or SVE data
processing operation speculatively executed, smallest type is 8-bit
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x844C,
ASE_SVE_FP_FP8_MIN_SPEC, Advanced SIMD data processing or SVE data
processing operation speculatively executed, smallest type is 8-bit
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8450, SE_FP_SP_MIN_SPEC,
Advanced SIMD, SVE, or SME data processing operation speculatively
executed, smallest type is single-precision floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8450, SE_FP_SP_MIN_SPEC,
Advanced SIMD, SVE, or SME data processing operation speculatively
executed, smallest type is single-precision floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8452, SE_FP_HP_MIN_SPEC,
Advanced SIMD, SVE, or SME data processing operation speculatively
executed, smallest type is half-precision floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8452, SE_FP_HP_MIN_SPEC,
Advanced SIMD, SVE, or SME data processing operation speculatively
executed, smallest type is half-precision floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8453,
SE_FP_BF16_MIN_SPEC, Advanced SIMD, SVE, or SME data processing
operation speculatively executed, smallest type is BFloat16
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8453,
SE_FP_BF16_MIN_SPEC, Advanced SIMD, SVE, or SME data processing
operation speculatively executed, smallest type is BFloat16
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8454,
SE_FP_FP8_MIN_SPEC, Advanced SIMD, SVE, or SME data processing operation
speculatively executed, smallest type is 8-bit floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8454,
SE_FP_FP8_MIN_SPEC, Advanced SIMD, SVE, or SME data processing operation
speculatively executed, smallest type is 8-bit floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8458,
SME_FP_SP_MIN_SPEC, SME data processing operation speculatively
executed, smallest type is single-precision floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8458,
SME_FP_SP_MIN_SPEC, SME data processing operation speculatively
executed, smallest type is single-precision floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x845A,
SME_FP_HP_MIN_SPEC, SME data processing operation speculatively
executed, smallest type is half-precision floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x845A,
SME_FP_HP_MIN_SPEC, SME data processing operation speculatively
executed, smallest type is half-precision floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x845B,
SME_FP_BF16_MIN_SPEC, SME data processing operation speculatively
executed, smallest type is BFloat16 floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x845B,
SME_FP_BF16_MIN_SPEC, SME data processing operation speculatively
executed, smallest type is BFloat16 floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x845C,
SME_FP_FP8_MIN_SPEC, SME data processing operation speculatively
executed, smallest type is 8-bit floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x845C,
SME_FP_FP8_MIN_SPEC, SME data processing operation speculatively
executed, smallest type is 8-bit floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8460,
SVE_FP_SP_MIN_SPEC, SVE data processing operation speculatively
executed, smallest type is single-precision floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8460,
SVE_FP_SP_MIN_SPEC, SVE data processing operation speculatively
executed, smallest type is single-precision floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8462,
SVE_FP_HP_MIN_SPEC, SVE data processing operation speculatively
executed, smallest type is half-precision floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8462,
SVE_FP_HP_MIN_SPEC, SVE data processing operation speculatively
executed, smallest type is half-precision floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8463,
SVE_FP_BF16_MIN_SPEC, SVE data processing operation speculatively
executed, smallest type is BFloat16 floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8463,
SVE_FP_BF16_MIN_SPEC, SVE data processing operation speculatively
executed, smallest type is BFloat16 floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8464,
SVE_FP_FP8_MIN_SPEC, SVE data processing operation speculatively
executed, smallest type is 8-bit floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8464,
SVE_FP_FP8_MIN_SPEC, SVE data processing operation speculatively
executed, smallest type is 8-bit floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x846B,
FP_BF16_FIXED_OPS_SPEC, Non-scalable element arithmetic operations
speculatively executed, largest type is BFloat16 floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x846B,
FP_BF16_FIXED_OPS_SPEC, Non-scalable element arithmetic operations
speculatively executed, largest type is BFloat16 floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8472, FP_HP_MIN_SPEC,
Floating-point operation speculatively executed, smallest type is
half-precision floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8472, FP_HP_MIN_SPEC,
Floating-point operation speculatively executed, smallest type is
half-precision floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8473, FP_BF16_MIN_SPEC,
Floating-point operation speculatively executed, smallest type is
BFloat16 floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8473, FP_BF16_MIN_SPEC,
Floating-point operation speculatively executed, smallest type is
BFloat16 floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8474, FP_FP8_MIN_SPEC,
Floating-point operation speculatively executed, smallest type is 8-bit
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8474, FP_FP8_MIN_SPEC,
Floating-point operation speculatively executed, smallest type is 8-bit
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8483,
FP_BF16_FIXED_MIN_OPS_SPEC, Non-scalable element arithmetic operations
speculatively executed, smallest type is BFloat16
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8483,
FP_BF16_FIXED_MIN_OPS_SPEC, Non-scalable element arithmetic operations
speculatively executed, smallest type is BFloat16
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8484,
FP_FP8_FIXED_MIN_OPS_SPEC, Non-scalable element arithmetic operations
speculatively executed, smallest type is 8-bit floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8484,
FP_FP8_FIXED_MIN_OPS_SPEC, Non-scalable element arithmetic operations
speculatively executed, smallest type is 8-bit floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x848A,
FP_HP_SCALE_MIN_OPS_SPEC, Scalable element arithmetic operations
speculatively executed, smallest type is half-precision
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x848A,
FP_HP_SCALE_MIN_OPS_SPEC, Scalable element arithmetic operations
speculatively executed, smallest type is half-precision
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x848B,
FP_BF16_SCALE_MIN_OPS_SPEC, Scalable element arithmetic operations
speculatively executed, smallest type is BFloat16
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x848B,
FP_BF16_SCALE_MIN_OPS_SPEC, Scalable element arithmetic operations
speculatively executed, smallest type is BFloat16
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x848C,
FP_FP8_SCALE_MIN_OPS_SPEC, Scalable element arithmetic operations
speculatively executed, smallest type is 8-bit floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x848C,
FP_FP8_SCALE_MIN_OPS_SPEC, Scalable element arithmetic operations
speculatively executed, smallest type is 8-bit floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8490,
FP_SP_SCALE2_MIN_OPS_SPEC, Scalable tile arithmetic operations
speculatively executed, smallest type is single-precision
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8490,
FP_SP_SCALE2_MIN_OPS_SPEC, Scalable tile arithmetic operations
speculatively executed, smallest type is single-precision
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8492,
FP_HP_SCALE2_MIN_OPS_SPEC, Scalable tile arithmetic operations
speculatively executed, smallest type is half-precision
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8492,
FP_HP_SCALE2_MIN_OPS_SPEC, Scalable tile arithmetic operations
speculatively executed, smallest type is half-precision
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8493,
FP_BF16_SCALE2_MIN_OPS_SPEC, Scalable tile arithmetic operations
speculatively executed, smallest type is BFloat16
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8493,
FP_BF16_SCALE2_MIN_OPS_SPEC, Scalable tile arithmetic operations
speculatively executed, smallest type is BFloat16
floating-point

# topic.topics[].topics[].topics[].topics[].label
​0x8494,
FP_FP8_SCALE2_MIN_OPS_SPEC, Scalable tile arithmetic operations
speculatively executed, smallest type is 8-bit floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​0x8494,
FP_FP8_SCALE2_MIN_OPS_SPEC, Scalable tile arithmetic operations
speculatively executed, smallest type is 8-bit floating-point

# topic.topics[].topics[].topics[].topics[].label
​D14.4.1 Cycle event counting in
multithreaded implementations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D14.4.1 Cycle event counting in
multithreaded implementations

# topic.topics[].topics[].topics[].topics[].label
​D14.4.2 Time as measured by the Performance
Monitors cycle counter

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D14.4.2 Time as measured by the Performance
Monitors cycle counter

# topic.topics[].topics[].topics[].label
​D14.5 Meaningful combinations of common
events

# topic.topics[].topics[].topics[].topics[].label
​D14.5.1 Refill events and associated access
events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D14.5.1 Refill events and associated access
events

# topic.topics[].topics[].topics[].topics[].label
​D14.5.3 Cache hit events and associated
data source events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D14.5.3 Cache hit events and associated
data source events

# topic.topics[].topics[].topics[].topics[].label
​D14.5.4 Cache line state tracking
events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D14.5.4 Cache line state tracking
events

# topic.topics[].topics[].topics[].topics[].label
​D14.5.7 Speculatively executed operation
events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D14.5.7 Speculatively executed operation
events

# topic.topics[].topics[].topics[].topics[].label
​D14.5.9 Overall vector utilization
events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D14.5.9 Overall vector utilization
events

# topic.topics[].topics[].topics[].anchors[].title
​D14.5 Meaningful combinations of common
events

# topic.topics[].topics[].topics[].label
​D14.8 IMPLEMENTATION DEFINED event
numbers

# topic.topics[].topics[].topics[].anchors[].title
​D14.8 IMPLEMENTATION DEFINED event
numbers

# topic.topics[].topics[].label
​Chapter D15
The System Performance Monitors Extension

# topic.topics[].topics[].topics[].label
​D15.1 About the System Performance
Monitors

# topic.topics[].topics[].topics[].anchors[].title
​D15.1 About the System Performance
Monitors

# topic.topics[].topics[].topics[].label
​D15.4 Generating System PMU overflow
interrupt requests

# topic.topics[].topics[].topics[].anchors[].title
​D15.4 Generating System PMU overflow
interrupt requests

# topic.topics[].topics[].anchors[].title
​Chapter D15
The System Performance Monitors Extension

# topic.topics[].topics[].label
​Chapter D16 The Activity Monitors
Extension

# topic.topics[].topics[].topics[].label
​D16.1 About the Activity Monitors
Extension

# topic.topics[].topics[].topics[].anchors[].title
​D16.1 About the Activity Monitors
Extension

# topic.topics[].topics[].topics[].label
​D16.2 Properties and behavior of the
activity monitors

# topic.topics[].topics[].topics[].topics[].label
​D16.2.1 Basic characteristics of the
activity monitor event counters

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D16.2.1 Basic characteristics of the
activity monitor event counters

# topic.topics[].topics[].topics[].topics[].label
​D16.2.2 Counter configuration and
controls

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D16.2.2 Counter configuration and
controls

# topic.topics[].topics[].topics[].topics[].label
​D16.2.4 Accuracy and non-invasive
behavior

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D16.2.4 Accuracy and non-invasive
behavior

# topic.topics[].topics[].topics[].anchors[].title
​D16.2 Properties and behavior of the
activity monitors

# topic.topics[].topics[].anchors[].title
​Chapter D16 The Activity Monitors
Extension

# topic.topics[].topics[].label
​Chapter D17 The Statistical Profiling
Extension

# topic.topics[].topics[].topics[].label
​D17.1 About the Statistical Profiling
Extension

# topic.topics[].topics[].topics[].anchors[].title
​D17.1 About the Statistical Profiling
Extension

# topic.topics[].topics[].topics[].topics[].label
​D17.2.1 Operations that might be excluded
from the sample population

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.2.1 Operations that might be excluded
from the sample population

# topic.topics[].topics[].topics[].label
​D17.3 Controlling when an operation is
sampled

# topic.topics[].topics[].topics[].topics[].label
​D17.3.2 Generating random numbers for
sampling

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.3.2 Generating random numbers for
sampling

# topic.topics[].topics[].topics[].topics[].label
​D17.3.3 Initializing the sample interval
counters

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.3.3 Initializing the sample interval
counters

# topic.topics[].topics[].topics[].topics[].label
​D17.3.4 Behavior of the sample interval
counter while profiling is enabled

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.3.4 Behavior of the sample interval
counter while profiling is enabled

# topic.topics[].topics[].topics[].topics[].label
​D17.3.5 Behavior of the sample interval
counter while profiling is disabled

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.3.5 Behavior of the sample interval
counter while profiling is disabled

# topic.topics[].topics[].topics[].anchors[].title
​D17.3 Controlling when an operation is
sampled

# topic.topics[].topics[].topics[].topics[].label
​D17.5.2 Filtering by the contents of the
Events packet

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.5.2 Filtering by the contents of the
Events packet

# topic.topics[].topics[].topics[].topics[].label
​D17.6.2 Information collected for
micro-ops

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.6.2 Information collected for
micro-ops

# topic.topics[].topics[].topics[].topics[].label
​D17.6.3 Additional information for each
profiled branch or exception return

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.6.3 Additional information for each
profiled branch or exception return

# topic.topics[].topics[].topics[].topics[].label
​D17.6.4 Additional information for each
profiled memory access operation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.6.4 Additional information for each
profiled memory access operation

# topic.topics[].topics[].topics[].topics[].label
​D17.6.5 Additional information for each
profiled conditional instruction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.6.5 Additional information for each
profiled conditional instruction

# topic.topics[].topics[].topics[].topics[].label
​D17.6.6 Additional information for each
profiled SVE and SME operation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.6.6 Additional information for each
profiled SVE and SME operation

# topic.topics[].topics[].topics[].topics[].label
​D17.6.7 Sample operation records for
misspeculated and non-architectural operations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.6.7 Sample operation records for
misspeculated and non-architectural operations

# topic.topics[].topics[].topics[].topics[].label
​D17.6.8 Additional information for other
operations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.6.8 Additional information for other
operations

# topic.topics[].topics[].topics[].topics[].label
​D17.6.9 Controlling the data that is
collected

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.6.9 Controlling the data that is
collected

# topic.topics[].topics[].topics[].topics[].label
​D17.7.1 Behavior when address translation
is enabled

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.7.1 Behavior when address translation
is enabled

# topic.topics[].topics[].topics[].topics[].label
​D17.7.2 Behavior when address translation
is disabled

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.7.2 Behavior when address translation
is disabled

# topic.topics[].topics[].topics[].topics[].label
​D17.7.4 Restrictions on the current write
pointer

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.7.4 Restrictions on the current write
pointer

# topic.topics[].topics[].topics[].topics[].label
​D17.7.6 Memory access types and
coherency

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.7.6 Memory access types and
coherency

# topic.topics[].topics[].topics[].topics[].label
​D17.7.7 Memory access and crossing page
boundaries

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.7.7 Memory access and crossing page
boundaries

# topic.topics[].topics[].topics[].topics[].label
​D17.7.9 Effect on the exclusive
monitors

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.7.9 Effect on the exclusive
monitors

# topic.topics[].topics[].topics[].topics[].label
​D17.8.1 Prioritization of Profiling Buffer
management events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D17.8.1 Prioritization of Profiling Buffer
management events

# topic.topics[].topics[].topics[].label
​D17.9 Synchronization and Statistical
Profiling

# topic.topics[].topics[].topics[].anchors[].title
​D17.9 Synchronization and Statistical
Profiling

# topic.topics[].topics[].anchors[].title
​Chapter D17 The Statistical Profiling
Extension

# topic.topics[].topics[].label
​Chapter D18 Statistical Profiling Extension
Sample Record Specification

# topic.topics[].topics[].topics[].label
​D18.1 About the Statistical Profiling
Extension sample records

# topic.topics[].topics[].topics[].topics[].label
​D18.1.3
Protocol framing packets and forwards compatibility

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D18.1.3
Protocol framing packets and forwards compatibility

# topic.topics[].topics[].topics[].topics[].label
​D18.1.4
Statistical Profiling Extension protocol packet headers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D18.1.4
Statistical Profiling Extension protocol packet headers

# topic.topics[].topics[].topics[].anchors[].title
​D18.1 About the Statistical Profiling
Extension sample records

# topic.topics[].topics[].topics[].label
​D18.2 Alphabetical list of Statistical
Profiling Extension packets

# topic.topics[].topics[].topics[].anchors[].title
​D18.2 Alphabetical list of Statistical
Profiling Extension packets

# topic.topics[].topics[].anchors[].title
​Chapter D18 Statistical Profiling Extension
Sample Record Specification

# topic.topics[].topics[].label
​Chapter D19
The Branch Record Buffer Extension

# topic.topics[].topics[].topics[].label
​D19.1 About the Branch Record Buffer
Extension

# topic.topics[].topics[].topics[].topics[].label
​D19.1.6 Branch records for exception
returns

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D19.1.6 Branch records for exception
returns

# topic.topics[].topics[].topics[].topics[].label
​D19.1.7 The Branch Record Buffer Extension
and the Transactional Memory Extension

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D19.1.7 The Branch Record Buffer Extension
and the Transactional Memory Extension

# topic.topics[].topics[].topics[].anchors[].title
​D19.1 About the Branch Record Buffer
Extension

# topic.topics[].topics[].topics[].topics[].label
​D19.5.1 Manual injection of Branch
records

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D19.5.1 Manual injection of Branch
records

# topic.topics[].topics[].anchors[].title
​Chapter D19
The Branch Record Buffer Extension

# topic.topics[].topics[].topics[].topics[].label
​D20.2.3 Clearing Deferred errors from
poisoned Locations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D20.2.3 Clearing Deferred errors from
poisoned Locations

# topic.topics[].topics[].topics[].topics[].label
​D20.4.1
PE error state recording in the exception syndrome

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D20.4.1
PE error state recording in the exception syndrome

# topic.topics[].topics[].topics[].topics[].label
​D20.4.4 Target Exception level for External
abort and SError exceptions taken to AArch64 state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D20.4.4 Target Exception level for External
abort and SError exceptions taken to AArch64 state

# topic.topics[].topics[].topics[].topics[].label
​D20.4.5 Target Exception level for External
abort and SError exceptions taken to AArch32 state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D20.4.5 Target Exception level for External
abort and SError exceptions taken to AArch32 state

# topic.topics[].topics[].topics[].topics[].label
​D20.5.1 ESB and virtual SError
exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D20.5.1 ESB and virtual SError
exceptions

# topic.topics[].topics[].topics[].topics[].label
​D20.5.2 ESB and delegated SError
exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D20.5.2 ESB and delegated SError
exceptions

# topic.topics[].topics[].topics[].topics[].label
​D20.5.3 Extension for synchronization at
exception entry and return

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D20.5.3 Extension for synchronization at
exception entry and return

# topic.topics[].topics[].topics[].topics[].label
​D20.5.4 Error synchronization barriers in a
minimal implementation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D20.5.4 Error synchronization barriers in a
minimal implementation

# topic.topics[].topics[].topics[].label
​D20.6 Virtual SError exceptions and
delegated SError exceptions

# topic.topics[].topics[].topics[].anchors[].title
​D20.6 Virtual SError exceptions and
delegated SError exceptions

# topic.topics[].topics[].topics[].topics[].label
​D20.7.1 Error record System register
view

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D20.7.1 Error record System register
view

# topic.topics[].topics[].topics[].topics[].label
​D21.1.3 Memory system resource
partitioning

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.1.3 Memory system resource
partitioning

# topic.topics[].topics[].topics[].topics[].label
​D21.1.4 Memory system resource usage
monitoring

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.1.4 Memory system resource usage
monitoring

# topic.topics[].topics[].topics[].topics[].label
​D21.1.5 MPAMn_ELx register naming
convention

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.1.5 MPAMn_ELx register naming
convention

# topic.topics[].topics[].topics[].topics[].label
​D21.2.2 In an MPAM PE with FEAT_RME,
selection of primary or alternative PARTID space

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.2.2 In an MPAM PE with FEAT_RME,
selection of primary or alternative PARTID space

# topic.topics[].topics[].topics[].topics[].label
​D21.2.3 Encoding PARTID spaces onto PARTID
space signals

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.2.3 Encoding PARTID spaces onto PARTID
space signals

# topic.topics[].topics[].topics[].label
​D21.4 Performance Monitoring Groups
(PMGs)

# topic.topics[].topics[].topics[].anchors[].title
​D21.4 Performance Monitoring Groups
(PMGs)

# topic.topics[].topics[].topics[].label
​D21.5 Effect of the MPAM3_EL3.{SDEFLT,
FORCE_NS} controls on PE Secure state execution

# topic.topics[].topics[].topics[].topics[].label
​D21.5.1 Interaction of MPAM3_EL3.SDEFLT and
the MPAM enable control

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.5.1 Interaction of MPAM3_EL3.SDEFLT and
the MPAM enable control

# topic.topics[].topics[].topics[].anchors[].title
​D21.5 Effect of the MPAM3_EL3.{SDEFLT,
FORCE_NS} controls on PE Secure state execution

# topic.topics[].topics[].topics[].label
​D21.6 Effect of access type on MPAM
information

# topic.topics[].topics[].topics[].topics[].label
​D21.6.2
Granule Protection Table (GPT) accesses

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.6.2
Granule Protection Table (GPT) accesses

# topic.topics[].topics[].topics[].topics[].label
​D21.6.3 Accesses by enhanced support for
nested virtualization

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.6.3 Accesses by enhanced support for
nested virtualization

# topic.topics[].topics[].topics[].topics[].label
​D21.6.5 Unprivileged memory access
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.6.5 Unprivileged memory access
instructions

# topic.topics[].topics[].topics[].topics[].label
​D21.6.6
Accesses by Statistical Profiling Extension

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.6.6
Accesses by Statistical Profiling Extension

# topic.topics[].topics[].topics[].topics[].label
​D21.6.7 Accesses by Trace Buffer
Extension

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.6.7 Accesses by Trace Buffer
Extension

# topic.topics[].topics[].topics[].anchors[].title
​D21.6 Effect of access type on MPAM
information

# topic.topics[].topics[].topics[].topics[].label
​D21.7.1 Single PARTID for an EL1 guest OS
and all its EL0 applications

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.7.1 Single PARTID for an EL1 guest OS
and all its EL0 applications

# topic.topics[].topics[].topics[].topics[].label
​D21.7.2 Trap controls to virtualize
MPAMIDR_EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.7.2 Trap controls to virtualize
MPAMIDR_EL1

# topic.topics[].topics[].topics[].topics[].label
​D21.7.3 Trap controls to trap accesses to
MPAM System registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.7.3 Trap controls to trap accesses to
MPAM System registers

# topic.topics[].topics[].topics[].topics[].label
​D21.7.7 Support for nested
virtualization

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.7.7 Support for nested
virtualization

# topic.topics[].topics[].topics[].label
​D21.8
PE-side Maximum-bandwidth limit injection control

# topic.topics[].topics[].topics[].anchors[].title
​D21.8
PE-side Maximum-bandwidth limit injection control

# topic.topics[].topics[].topics[].topics[].label
​D21.9.1 Behavior when a PARTID is
out-of-range

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.9.1 Behavior when a PARTID is
out-of-range

# topic.topics[].topics[].topics[].topics[].label
​D21.9.2 Behavior when a valid mapping does
not exist for a PARTID that is treated as virtual

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.9.2 Behavior when a valid mapping does
not exist for a PARTID that is treated as virtual

# topic.topics[].topics[].topics[].topics[].label
​D21.9.3 Behavior when a PMG is
out-of-range

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.9.3 Behavior when a PMG is
out-of-range

# topic.topics[].topics[].topics[].topics[].label
​D21.9.4 PMG value when a Default PARTID is
generated due to an MPAM error

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D21.9.4 PMG value when a Default PARTID is
generated due to an MPAM error

# topic.topics[].topics[].topics[].label
​D21.10 Synchronization of MPAM System
register changes

# topic.topics[].topics[].topics[].anchors[].title
​D21.10 Synchronization of MPAM System
register changes

# topic.topics[].topics[].label
​Chapter D22 The Scalable Matrix
Extension

# topic.topics[].topics[].topics[].topics[].label
​D22.4.1 Streaming execution priority for
shared implementations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D22.4.1 Streaming execution priority for
shared implementations

# topic.topics[].topics[].topics[].label
​D22.5 Floating-point behaviors in Streaming
SVE mode

# topic.topics[].topics[].topics[].anchors[].title
​D22.5 Floating-point behaviors in Streaming
SVE mode

# topic.topics[].topics[].topics[].label
​D22.6 Floating-point behaviors for
instructions that target the SME ZA array

# topic.topics[].topics[].topics[].anchors[].title
​D22.6 Floating-point behaviors for
instructions that target the SME ZA array

# topic.topics[].topics[].topics[].label
​D22.7 Security and power considerations

# topic.topics[].topics[].topics[].anchors[].title
​D22.7 Security and power considerations

# topic.topics[].topics[].anchors[].title
​Chapter D22 The Scalable Matrix
Extension

# topic.topics[].topics[].label
​Chapter D23 AArch64 System Register
Encoding

# topic.topics[].topics[].topics[].label
​D23.1 The System register encoding
space

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​D23.1 The System register encoding
space

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​D23.2 Moves to and from debug and trace
System registers

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​D23.2.1 Instructions for accessing debug
System registers

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​D23.2.1 Instructions for accessing debug
System registers

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​D23.2 Moves to and from debug and trace
System registers

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​D23.3 Moves to and from non-debug System
registers, Special-purpose registers

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​D23.3.1 Instructions for accessing
non-debug System registers

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​D23.3.1 Instructions for accessing
non-debug System registers

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​D23.3.2 Reserved encodings for
IMPLEMENTATION DEFINED registers

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​D23.3.2 Reserved encodings for
IMPLEMENTATION DEFINED registers

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​D23.3 Moves to and from non-debug System
registers, Special-purpose registers

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​Chapter D23 AArch64 System Register
Encoding

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​Chapter
D24 AArch64 System Register Descriptions

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​D24.1 About the AArch64 System
registers

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​D24.1.1 Fixed values and reserved values in
the System register descriptions

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​D24.1.1 Fixed values and reserved values in
the System register descriptions

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​D24.1.2 General behavior of accesses to the
AArch64 System registers

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​D24.1.2 General behavior of accesses to the
AArch64 System registers

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​D24.1.3 Principles of the ID scheme for
fields in ID registers

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​D24.1.3 Principles of the ID scheme for
fields in ID registers

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​D24.1 About the AArch64 System
registers

# topic.topics[].topics[].topics[].topics[].label
​D24.2.2
ACTLR_EL1, Auxiliary Control Register (EL1)

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​D24.2.2
ACTLR_EL1, Auxiliary Control Register (EL1)

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​D24.2.3
ACTLR_EL2, Auxiliary Control Register (EL2)

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​D24.2.3
ACTLR_EL2, Auxiliary Control Register (EL2)

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​D24.2.4
ACTLR_EL3, Auxiliary Control Register (EL3)

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​D24.2.4
ACTLR_EL3, Auxiliary Control Register (EL3)

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​D24.2.5
ACTLRMASK_EL1, Auxiliary Control Masking Register (EL1)

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​D24.2.5
ACTLRMASK_EL1, Auxiliary Control Masking Register (EL1)

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​D24.2.6
ACTLRMASK_EL2, Auxiliary Control Masking Register (EL2)

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​D24.2.6
ACTLRMASK_EL2, Auxiliary Control Masking Register (EL2)

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​D24.2.7
AFSR0_EL1, Auxiliary Fault Status Register 0 (EL1)

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​D24.2.7
AFSR0_EL1, Auxiliary Fault Status Register 0 (EL1)

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​D24.2.8
AFSR0_EL2, Auxiliary Fault Status Register 0 (EL2)

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​D24.2.8
AFSR0_EL2, Auxiliary Fault Status Register 0 (EL2)

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​D24.2.9
AFSR0_EL3, Auxiliary Fault Status Register 0 (EL3)

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​D24.2.9
AFSR0_EL3, Auxiliary Fault Status Register 0 (EL3)

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​D24.2.10
AFSR1_EL1, Auxiliary Fault Status Register 1 (EL1)

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​D24.2.10
AFSR1_EL1, Auxiliary Fault Status Register 1 (EL1)

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​D24.2.11
AFSR1_EL2, Auxiliary Fault Status Register 1 (EL2)

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​D24.2.11
AFSR1_EL2, Auxiliary Fault Status Register 1 (EL2)

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​D24.2.12
AFSR1_EL3, Auxiliary Fault Status Register 1 (EL3)

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​D24.2.12
AFSR1_EL3, Auxiliary Fault Status Register 1 (EL3)

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​D24.2.13
AIDR_EL1, Auxiliary ID Register

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​D24.2.13
AIDR_EL1, Auxiliary ID Register

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​D24.2.14
AMAIR2_EL1, Extended Auxiliary Memory Attribute Indirection
Register (EL1)

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​D24.2.14
AMAIR2_EL1, Extended Auxiliary Memory Attribute Indirection
Register (EL1)

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​D24.2.15
AMAIR2_EL2, Extended Auxiliary Memory Attribute Indirection
Register (EL2)

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​D24.2.15
AMAIR2_EL2, Extended Auxiliary Memory Attribute Indirection
Register (EL2)

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​D24.2.16
AMAIR2_EL3, Extended Auxiliary Memory Attribute Indirection
Register (EL3)

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​D24.2.16
AMAIR2_EL3, Extended Auxiliary Memory Attribute Indirection
Register (EL3)

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​D24.2.17
AMAIR_EL1, Auxiliary Memory Attribute Indirection Register
(EL1)

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​D24.2.17
AMAIR_EL1, Auxiliary Memory Attribute Indirection Register
(EL1)

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​D24.2.18
AMAIR_EL2, Auxiliary Memory Attribute Indirection Register
(EL2)

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​D24.2.18
AMAIR_EL2, Auxiliary Memory Attribute Indirection Register
(EL2)

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​D24.2.19
AMAIR_EL3, Auxiliary Memory Attribute Indirection Register
(EL3)

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​D24.2.19
AMAIR_EL3, Auxiliary Memory Attribute Indirection Register
(EL3)

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​D24.2.21
APDAKeyHi_EL1, Pointer Authentication Key A for Data
(bits[127:64])

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​D24.2.21
APDAKeyHi_EL1, Pointer Authentication Key A for Data
(bits[127:64])

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​D24.2.22
APDAKeyLo_EL1, Pointer Authentication Key A for Data
(bits[63:0])

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​D24.2.22
APDAKeyLo_EL1, Pointer Authentication Key A for Data
(bits[63:0])

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​D24.2.23
APDBKeyHi_EL1, Pointer Authentication Key B for Data
(bits[127:64])

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​D24.2.23
APDBKeyHi_EL1, Pointer Authentication Key B for Data
(bits[127:64])

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​D24.2.24
APDBKeyLo_EL1, Pointer Authentication Key B for Data
(bits[63:0])

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​D24.2.24
APDBKeyLo_EL1, Pointer Authentication Key B for Data
(bits[63:0])

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​D24.2.25
APGAKeyHi_EL1, Pointer Authentication Key A for Code
(bits[127:64])

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​D24.2.25
APGAKeyHi_EL1, Pointer Authentication Key A for Code
(bits[127:64])

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​D24.2.26
APGAKeyLo_EL1, Pointer Authentication Key A for Code
(bits[63:0])

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​D24.2.26
APGAKeyLo_EL1, Pointer Authentication Key A for Code
(bits[63:0])

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​D24.2.27
APIAKeyHi_EL1, Pointer Authentication Key A for Instruction
(bits[127:64])

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​D24.2.27
APIAKeyHi_EL1, Pointer Authentication Key A for Instruction
(bits[127:64])

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​D24.2.28
APIAKeyLo_EL1, Pointer Authentication Key A for Instruction
(bits[63:0])

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​D24.2.28
APIAKeyLo_EL1, Pointer Authentication Key A for Instruction
(bits[63:0])

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​D24.2.29
APIBKeyHi_EL1, Pointer Authentication Key B for Instruction
(bits[127:64])

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​D24.2.29
APIBKeyHi_EL1, Pointer Authentication Key B for Instruction
(bits[127:64])

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​D24.2.30
APIBKeyLo_EL1, Pointer Authentication Key B for Instruction
(bits[63:0])

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​D24.2.30
APIBKeyLo_EL1, Pointer Authentication Key B for Instruction
(bits[63:0])

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​D24.2.31
CCSIDR2_EL1, Current Cache Size ID Register 2

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​D24.2.31
CCSIDR2_EL1, Current Cache Size ID Register 2

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​D24.2.32
CCSIDR_EL1, Current Cache Size ID Register

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​D24.2.32
CCSIDR_EL1, Current Cache Size ID Register

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​D24.2.33
CLIDR_EL1, Cache Level ID Register

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​D24.2.33
CLIDR_EL1, Cache Level ID Register

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​D24.2.34
CONTEXTIDR_EL1, Context ID Register (EL1)

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​D24.2.34
CONTEXTIDR_EL1, Context ID Register (EL1)

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​D24.2.35
CONTEXTIDR_EL2, Context ID Register (EL2)

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​D24.2.35
CONTEXTIDR_EL2, Context ID Register (EL2)

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​D24.2.36
CPACR_EL1, Architectural Feature Access Control Register

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​D24.2.36
CPACR_EL1, Architectural Feature Access Control Register

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​D24.2.37
CPACRMASK_EL1, Architectural Feature Access Control Masking
Register

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​D24.2.37
CPACRMASK_EL1, Architectural Feature Access Control Masking
Register

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​D24.2.38
CPTR_EL2, Architectural Feature Trap Register (EL2)

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​D24.2.38
CPTR_EL2, Architectural Feature Trap Register (EL2)

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​D24.2.39
CPTR_EL3, Architectural Feature Trap Register (EL3)

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​D24.2.39
CPTR_EL3, Architectural Feature Trap Register (EL3)

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​D24.2.40
CPTRMASK_EL2, Architectural Feature Trap Masking
Register

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​D24.2.40
CPTRMASK_EL2, Architectural Feature Trap Masking
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.41
CSSELR_EL1, Cache Size Selection Register

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​D24.2.41
CSSELR_EL1, Cache Size Selection Register

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​D24.2.43
DACR32_EL2, Domain Access Control Register

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​D24.2.43
DACR32_EL2, Domain Access Control Register

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​D24.2.44
DCZID_EL0, Data Cache Zero ID Register

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​D24.2.44
DCZID_EL0, Data Cache Zero ID Register

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​D24.2.45
ESR_EL1, Exception Syndrome Register (EL1)

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​D24.2.45
ESR_EL1, Exception Syndrome Register (EL1)

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​D24.2.46
ESR_EL2, Exception Syndrome Register (EL2)

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​D24.2.46
ESR_EL2, Exception Syndrome Register (EL2)

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​D24.2.47
ESR_EL3, Exception Syndrome Register (EL3)

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​D24.2.47
ESR_EL3, Exception Syndrome Register (EL3)

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​D24.2.48
FAR_EL1, Fault Address Register (EL1)

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​D24.2.48
FAR_EL1, Fault Address Register (EL1)

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​D24.2.49
FAR_EL2, Fault Address Register (EL2)

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​D24.2.49
FAR_EL2, Fault Address Register (EL2)

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​D24.2.50
FAR_EL3, Fault Address Register (EL3)

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​D24.2.50
FAR_EL3, Fault Address Register (EL3)

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​D24.2.51
FGWTE3_EL3, Fine-Grained Write Traps EL3

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​D24.2.51
FGWTE3_EL3, Fine-Grained Write Traps EL3

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​D24.2.53
GCR_EL1, Tag Control Register.

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​D24.2.53
GCR_EL1, Tag Control Register.

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​D24.2.54
GMID_EL1, Multiple tag transfer ID Register

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​D24.2.54
GMID_EL1, Multiple tag transfer ID Register

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​D24.2.55
GPCBW_EL3, Granule Protection Check Bypass Window Register
(EL3)

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​D24.2.55
GPCBW_EL3, Granule Protection Check Bypass Window Register
(EL3)

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​D24.2.56
GPCCR_EL3, Granule Protection Check Control Register
(EL3)

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​D24.2.56
GPCCR_EL3, Granule Protection Check Control Register
(EL3)

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​D24.2.57
GPTBR_EL3, Granule Protection Table Base Register

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​D24.2.57
GPTBR_EL3, Granule Protection Table Base Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.58
HACDBSBR_EL2, Hardware Accelerator for Cleaning Dirty State Base
Register

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​D24.2.58
HACDBSBR_EL2, Hardware Accelerator for Cleaning Dirty State Base
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.59
HACDBSCONS_EL2, Hardware Accelerator for Cleaning Dirty State
Consumer Register

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​D24.2.59
HACDBSCONS_EL2, Hardware Accelerator for Cleaning Dirty State
Consumer Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.60
HACR_EL2, Hypervisor Auxiliary Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.60
HACR_EL2, Hypervisor Auxiliary Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.61
HAFGRTR_EL2, Hypervisor Activity Monitors Fine-Grained Read Trap
Register

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​D24.2.61
HAFGRTR_EL2, Hypervisor Activity Monitors Fine-Grained Read Trap
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.64
HDBSSBR_EL2, Hardware Dirty State Tracking Structure Base
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.64
HDBSSBR_EL2, Hardware Dirty State Tracking Structure Base
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.65
HDBSSPROD_EL2, Hardware Dirty State Tracking Structure Producer
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.65
HDBSSPROD_EL2, Hardware Dirty State Tracking Structure Producer
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.66
HDFGRTR2_EL2, Hypervisor Debug Fine-Grained Read Trap Register
2

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​D24.2.66
HDFGRTR2_EL2, Hypervisor Debug Fine-Grained Read Trap Register
2

# topic.topics[].topics[].topics[].topics[].label
​D24.2.67
HDFGRTR_EL2, Hypervisor Debug Fine-Grained Read Trap
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.67
HDFGRTR_EL2, Hypervisor Debug Fine-Grained Read Trap
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.68
HDFGWTR2_EL2, Hypervisor Debug Fine-Grained Write Trap Register
2

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​D24.2.68
HDFGWTR2_EL2, Hypervisor Debug Fine-Grained Write Trap Register
2

# topic.topics[].topics[].topics[].topics[].label
​D24.2.69
HDFGWTR_EL2, Hypervisor Debug Fine-Grained Write Trap
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.69
HDFGWTR_EL2, Hypervisor Debug Fine-Grained Write Trap
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.70
HFGITR2_EL2, Hypervisor Fine-Grained Instruction Trap Register
2

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​D24.2.70
HFGITR2_EL2, Hypervisor Fine-Grained Instruction Trap Register
2

# topic.topics[].topics[].topics[].topics[].label
​D24.2.71
HFGITR_EL2, Hypervisor Fine-Grained Instruction Trap
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.71
HFGITR_EL2, Hypervisor Fine-Grained Instruction Trap
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.72
HFGRTR2_EL2, Hypervisor Fine-Grained Read Trap Register
2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.72
HFGRTR2_EL2, Hypervisor Fine-Grained Read Trap Register
2

# topic.topics[].topics[].topics[].topics[].label
​D24.2.73
HFGRTR_EL2, Hypervisor Fine-Grained Read Trap Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.73
HFGRTR_EL2, Hypervisor Fine-Grained Read Trap Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.74
HFGWTR2_EL2, Hypervisor Fine-Grained Write Trap Register
2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.74
HFGWTR2_EL2, Hypervisor Fine-Grained Write Trap Register
2

# topic.topics[].topics[].topics[].topics[].label
​D24.2.75
HFGWTR_EL2, Hypervisor Fine-Grained Write Trap Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.75
HFGWTR_EL2, Hypervisor Fine-Grained Write Trap Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.76
HPFAR_EL2, Hypervisor IPA Fault Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.76
HPFAR_EL2, Hypervisor IPA Fault Address Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.77
HSTR_EL2, Hypervisor System Trap Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.77
HSTR_EL2, Hypervisor System Trap Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.78 ID_AA64AFR0_EL1, AArch64 Auxiliary
Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.78 ID_AA64AFR0_EL1, AArch64 Auxiliary
Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.2.79 ID_AA64AFR1_EL1, AArch64 Auxiliary
Feature Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.79 ID_AA64AFR1_EL1, AArch64 Auxiliary
Feature Register 1

# topic.topics[].topics[].topics[].topics[].label
​D24.2.80 ID_AA64DFR0_EL1, AArch64 Debug
Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.80 ID_AA64DFR0_EL1, AArch64 Debug
Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.2.81 ID_AA64DFR1_EL1, AArch64 Debug
Feature Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.81 ID_AA64DFR1_EL1, AArch64 Debug
Feature Register 1

# topic.topics[].topics[].topics[].topics[].label
​D24.2.82 ID_AA64DFR2_EL1, AArch64 Debug
Feature Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.82 ID_AA64DFR2_EL1, AArch64 Debug
Feature Register 2

# topic.topics[].topics[].topics[].topics[].label
​D24.2.83 ID_AA64FPFR0_EL1, AArch64
Floating-point Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.83 ID_AA64FPFR0_EL1, AArch64
Floating-point Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.2.84 ID_AA64ISAR0_EL1, AArch64
Instruction Set Attribute Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.84 ID_AA64ISAR0_EL1, AArch64
Instruction Set Attribute Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.2.85 ID_AA64ISAR1_EL1, AArch64
Instruction Set Attribute Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.85 ID_AA64ISAR1_EL1, AArch64
Instruction Set Attribute Register 1

# topic.topics[].topics[].topics[].topics[].label
​D24.2.86 ID_AA64ISAR2_EL1, AArch64
Instruction Set Attribute Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.86 ID_AA64ISAR2_EL1, AArch64
Instruction Set Attribute Register 2

# topic.topics[].topics[].topics[].topics[].label
​D24.2.87 ID_AA64ISAR3_EL1, AArch64
Instruction Set Attribute Register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.87 ID_AA64ISAR3_EL1, AArch64
Instruction Set Attribute Register 3

# topic.topics[].topics[].topics[].topics[].label
​D24.2.88 ID_AA64MMFR0_EL1, AArch64 Memory
Model Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.88 ID_AA64MMFR0_EL1, AArch64 Memory
Model Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.2.89 ID_AA64MMFR1_EL1, AArch64 Memory
Model Feature Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.89 ID_AA64MMFR1_EL1, AArch64 Memory
Model Feature Register 1

# topic.topics[].topics[].topics[].topics[].label
​D24.2.90 ID_AA64MMFR2_EL1, AArch64 Memory
Model Feature Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.90 ID_AA64MMFR2_EL1, AArch64 Memory
Model Feature Register 2

# topic.topics[].topics[].topics[].topics[].label
​D24.2.91 ID_AA64MMFR3_EL1, AArch64 Memory
Model Feature Register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.91 ID_AA64MMFR3_EL1, AArch64 Memory
Model Feature Register 3

# topic.topics[].topics[].topics[].topics[].label
​D24.2.92 ID_AA64MMFR4_EL1, AArch64 Memory
Model Feature Register 4

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.92 ID_AA64MMFR4_EL1, AArch64 Memory
Model Feature Register 4

# topic.topics[].topics[].topics[].topics[].label
​D24.2.93 ID_AA64PFR0_EL1, AArch64 Processor
Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.93 ID_AA64PFR0_EL1, AArch64 Processor
Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.2.94 ID_AA64PFR1_EL1, AArch64 Processor
Feature Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.94 ID_AA64PFR1_EL1, AArch64 Processor
Feature Register 1

# topic.topics[].topics[].topics[].topics[].label
​D24.2.95 ID_AA64PFR2_EL1, AArch64 Processor
Feature Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.95 ID_AA64PFR2_EL1, AArch64 Processor
Feature Register 2

# topic.topics[].topics[].topics[].topics[].label
​D24.2.96 ID_AA64SMFR0_EL1, SME Feature ID
Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.96 ID_AA64SMFR0_EL1, SME Feature ID
Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.2.97 ID_AA64ZFR0_EL1, SVE Feature ID
Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.97 ID_AA64ZFR0_EL1, SVE Feature ID
Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.2.98
ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.98
ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.2.99
ID_DFR0_EL1, AArch32 Debug Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.99
ID_DFR0_EL1, AArch32 Debug Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.2.100
ID_DFR1_EL1, AArch32 Debug Feature Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.100
ID_DFR1_EL1, AArch32 Debug Feature Register 1

# topic.topics[].topics[].topics[].topics[].label
​D24.2.101
ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.101
ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register
0

# topic.topics[].topics[].topics[].topics[].label
​D24.2.102
ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.102
ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register
1

# topic.topics[].topics[].topics[].topics[].label
​D24.2.103
ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register
2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.103
ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register
2

# topic.topics[].topics[].topics[].topics[].label
​D24.2.104
ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register
3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.104
ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register
3

# topic.topics[].topics[].topics[].topics[].label
​D24.2.105
ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register
4

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.105
ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register
4

# topic.topics[].topics[].topics[].topics[].label
​D24.2.106
ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register
5

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.106
ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register
5

# topic.topics[].topics[].topics[].topics[].label
​D24.2.107
ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register
6

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.107
ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register
6

# topic.topics[].topics[].topics[].topics[].label
​D24.2.108
ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.108
ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.2.109
ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.109
ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1

# topic.topics[].topics[].topics[].topics[].label
​D24.2.110
ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.110
ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2

# topic.topics[].topics[].topics[].topics[].label
​D24.2.111
ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.111
ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3

# topic.topics[].topics[].topics[].topics[].label
​D24.2.112
ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.112
ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4

# topic.topics[].topics[].topics[].topics[].label
​D24.2.113
ID_MMFR5_EL1, AArch32 Memory Model Feature Register 5

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.113
ID_MMFR5_EL1, AArch32 Memory Model Feature Register 5

# topic.topics[].topics[].topics[].topics[].label
​D24.2.114
ID_PFR0_EL1, AArch32 Processor Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.114
ID_PFR0_EL1, AArch32 Processor Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.2.115
ID_PFR1_EL1, AArch32 Processor Feature Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.115
ID_PFR1_EL1, AArch32 Processor Feature Register 1

# topic.topics[].topics[].topics[].topics[].label
​D24.2.116
ID_PFR2_EL1, AArch32 Processor Feature Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.116
ID_PFR2_EL1, AArch32 Processor Feature Register 2

# topic.topics[].topics[].topics[].topics[].label
​D24.2.117
IFSR32_EL2, Instruction Fault Status Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.117
IFSR32_EL2, Instruction Fault Status Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.118
ISR_EL1, Interrupt Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.118
ISR_EL1, Interrupt Status Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.119
LORC_EL1, LORegion Control (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.119
LORC_EL1, LORegion Control (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.120
LOREA_EL1, LORegion End Address (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.120
LOREA_EL1, LORegion End Address (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.122
LORN_EL1, LORegion Number (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.122
LORN_EL1, LORegion Number (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.123
LORSA_EL1, LORegion Start Address (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.123
LORSA_EL1, LORegion Start Address (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.124
MAIR2_EL1, Extended Memory Attribute Indirection Register
(EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.124
MAIR2_EL1, Extended Memory Attribute Indirection Register
(EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.125
MAIR2_EL2, Extended Memory Attribute Indirection Register
(EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.125
MAIR2_EL2, Extended Memory Attribute Indirection Register
(EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.126
MAIR2_EL3, Extended Memory Attribute Indirection Register
(EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.126
MAIR2_EL3, Extended Memory Attribute Indirection Register
(EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.127
MAIR_EL1, Memory Attribute Indirection Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.127
MAIR_EL1, Memory Attribute Indirection Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.128
MAIR_EL2, Memory Attribute Indirection Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.128
MAIR_EL2, Memory Attribute Indirection Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.129
MAIR_EL3, Memory Attribute Indirection Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.129
MAIR_EL3, Memory Attribute Indirection Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.130
MECID_A0_EL2, Alternate MECID for EL2 and EL2&0 translation
regimes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.130
MECID_A0_EL2, Alternate MECID for EL2 and EL2&0 translation
regimes

# topic.topics[].topics[].topics[].topics[].label
​D24.2.131
MECID_A1_EL2, Alternate MECID for EL2&0 translation
regimes.

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.131
MECID_A1_EL2, Alternate MECID for EL2&0 translation
regimes.

# topic.topics[].topics[].topics[].topics[].label
​D24.2.132
MECID_P0_EL2, Primary MECID for EL2 and EL2&0 translation
regimes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.132
MECID_P0_EL2, Primary MECID for EL2 and EL2&0 translation
regimes

# topic.topics[].topics[].topics[].topics[].label
​D24.2.133
MECID_P1_EL2, Primary MECID for EL2&0 translation
regimes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.133
MECID_P1_EL2, Primary MECID for EL2&0 translation
regimes

# topic.topics[].topics[].topics[].topics[].label
​D24.2.134 MECID_RL_A_EL3, Realm PA space
Alternate MECID for EL3 stage 1 translation regime

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.134 MECID_RL_A_EL3, Realm PA space
Alternate MECID for EL3 stage 1 translation regime

# topic.topics[].topics[].topics[].topics[].label
​D24.2.136
MFAR_EL3, Physical Fault Address Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.136
MFAR_EL3, Physical Fault Address Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.139
MVFR0_EL1, AArch32 Media and VFP Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.139
MVFR0_EL1, AArch32 Media and VFP Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.2.140
MVFR1_EL1, AArch32 Media and VFP Feature Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.140
MVFR1_EL1, AArch32 Media and VFP Feature Register 1

# topic.topics[].topics[].topics[].topics[].label
​D24.2.141
MVFR2_EL1, AArch32 Media and VFP Feature Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.141
MVFR2_EL1, AArch32 Media and VFP Feature Register 2

# topic.topics[].topics[].topics[].topics[].label
​D24.2.142
PAR_EL1, Physical Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.142
PAR_EL1, Physical Address Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.143
PFAR_EL1, Physical Fault Address Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.143
PFAR_EL1, Physical Fault Address Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.144
PFAR_EL2, Physical Fault Address Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.144
PFAR_EL2, Physical Fault Address Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.145
PIR_EL1, Permission Indirection Register 1 (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.145
PIR_EL1, Permission Indirection Register 1 (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.146
PIR_EL2, Permission Indirection Register 2 (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.146
PIR_EL2, Permission Indirection Register 2 (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.147
PIR_EL3, Permission Indirection Register 3 (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.147
PIR_EL3, Permission Indirection Register 3 (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.148
PIRE0_EL1, Permission Indirection Register 0 (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.148
PIRE0_EL1, Permission Indirection Register 0 (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.149
PIRE0_EL2, Permission Indirection Register 0 (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.149
PIRE0_EL2, Permission Indirection Register 0 (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.150
POR_EL0, Permission Overlay Register 0 (EL0)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.150
POR_EL0, Permission Overlay Register 0 (EL0)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.151
POR_EL1, Permission Overlay Register 1 (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.151
POR_EL1, Permission Overlay Register 1 (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.152
POR_EL2, Permission Overlay Register 2 (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.152
POR_EL2, Permission Overlay Register 2 (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.153
POR_EL3, Permission Overlay Register 3 (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.153
POR_EL3, Permission Overlay Register 3 (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.154
RCWMASK_EL1, Read Check Write Instruction Mask (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.154
RCWMASK_EL1, Read Check Write Instruction Mask (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.155
RCWSMASK_EL1, Software Read Check Write Instruction Mask
(EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.155
RCWSMASK_EL1, Software Read Check Write Instruction Mask
(EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.156
REVIDR_EL1, Revision ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.156
REVIDR_EL1, Revision ID Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.157
RGSR_EL1, Random Allocation Tag Seed Register.

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.157
RGSR_EL1, Random Allocation Tag Seed Register.

# topic.topics[].topics[].topics[].topics[].label
​D24.2.158
RMR_EL1, Reset Management Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.158
RMR_EL1, Reset Management Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.159
RMR_EL2, Reset Management Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.159
RMR_EL2, Reset Management Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.160
RMR_EL3, Reset Management Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.160
RMR_EL3, Reset Management Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.162
RNDRRS, Random Number Full Entropy

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.162
RNDRRS, Random Number Full Entropy

# topic.topics[].topics[].topics[].topics[].label
​D24.2.163
RVBAR_EL1, Reset Vector Base Address Register (if EL2 and EL3 not
implemented)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.163
RVBAR_EL1, Reset Vector Base Address Register (if EL2 and EL3 not
implemented)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.164
RVBAR_EL2, Reset Vector Base Address Register (if EL3 not
implemented)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.164
RVBAR_EL2, Reset Vector Base Address Register (if EL3 not
implemented)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.165
RVBAR_EL3, Reset Vector Base Address Register (if EL3
implemented)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.165
RVBAR_EL3, Reset Vector Base Address Register (if EL3
implemented)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.166
S2PIR_EL2, Stage 2 Permission Indirection Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.166
S2PIR_EL2, Stage 2 Permission Indirection Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.167
S2POR_EL1, Stage 2 Permission Overlay Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.167
S2POR_EL1, Stage 2 Permission Overlay Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.168
S3_<op1>_<Cn>_<Cm>_<op2>, IMPLEMENTATION
DEFINED Registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.168
S3_<op1>_<Cn>_<Cm>_<op2>, IMPLEMENTATION
DEFINED Registers

# topic.topics[].topics[].topics[].topics[].label
​D24.2.170
SCTLR2_EL1, System Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.170
SCTLR2_EL1, System Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.171
SCTLR2_EL2, System Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.171
SCTLR2_EL2, System Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.172
SCTLR2_EL3, System Control Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.172
SCTLR2_EL3, System Control Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.173 SCTLR2MASK_EL1, Extended System
Control Masking Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.173 SCTLR2MASK_EL1, Extended System
Control Masking Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.174 SCTLR2MASK_EL2, Extended System
Control Masking Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.174 SCTLR2MASK_EL2, Extended System
Control Masking Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.175
SCTLR_EL1, System Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.175
SCTLR_EL1, System Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.176
SCTLR_EL2, System Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.176
SCTLR_EL2, System Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.177
SCTLR_EL3, System Control Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.177
SCTLR_EL3, System Control Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.178
SCTLRMASK_EL1, System Control Masking Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.178
SCTLRMASK_EL1, System Control Masking Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.179
SCTLRMASK_EL2, System Control Masking Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.179
SCTLRMASK_EL2, System Control Masking Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.180
SCXTNUM_EL0, EL0 Read/Write Software Context Number

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.180
SCXTNUM_EL0, EL0 Read/Write Software Context Number

# topic.topics[].topics[].topics[].topics[].label
​D24.2.181
SCXTNUM_EL1, EL1 Read/Write Software Context Number

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.181
SCXTNUM_EL1, EL1 Read/Write Software Context Number

# topic.topics[].topics[].topics[].topics[].label
​D24.2.182
SCXTNUM_EL2, EL2 Read/Write Software Context Number

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.182
SCXTNUM_EL2, EL2 Read/Write Software Context Number

# topic.topics[].topics[].topics[].topics[].label
​D24.2.183
SCXTNUM_EL3, EL3 Read/Write Software Context Number

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.183
SCXTNUM_EL3, EL3 Read/Write Software Context Number

# topic.topics[].topics[].topics[].topics[].label
​D24.2.184
SMCR_EL1, SME Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.184
SMCR_EL1, SME Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.185
SMCR_EL2, SME Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.185
SMCR_EL2, SME Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.186
SMCR_EL3, SME Control Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.186
SMCR_EL3, SME Control Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.187
SMIDR_EL1, Streaming Mode Identification Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.187
SMIDR_EL1, Streaming Mode Identification Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.188
SMPRI_EL1, Streaming Mode Priority Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.188
SMPRI_EL1, Streaming Mode Priority Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.189
SMPRIMAP_EL2, Streaming Mode Priority Mapping Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.189
SMPRIMAP_EL2, Streaming Mode Priority Mapping Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.190
TCR2_EL1, Extended Translation Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.190
TCR2_EL1, Extended Translation Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.191
TCR2_EL2, Extended Translation Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.191
TCR2_EL2, Extended Translation Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.192
TCR2MASK_EL1, Extended Translation Control Masking Register
(EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.192
TCR2MASK_EL1, Extended Translation Control Masking Register
(EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.193
TCR2MASK_EL2, Extended Translation Control Masking Register
(EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.193
TCR2MASK_EL2, Extended Translation Control Masking Register
(EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.194
TCR_EL1, Translation Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.194
TCR_EL1, Translation Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.195
TCR_EL2, Translation Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.195
TCR_EL2, Translation Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.196
TCR_EL3, Translation Control Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.196
TCR_EL3, Translation Control Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.197
TCRMASK_EL1, Translation Control Masking Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.197
TCRMASK_EL1, Translation Control Masking Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.198
TCRMASK_EL2, Translation Control Masking Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.198
TCRMASK_EL2, Translation Control Masking Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.199
TFSR_EL1, Tag Fault Status Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.199
TFSR_EL1, Tag Fault Status Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.200
TFSR_EL2, Tag Fault Status Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.200
TFSR_EL2, Tag Fault Status Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.201
TFSR_EL3, Tag Fault Status Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.201
TFSR_EL3, Tag Fault Status Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.202
TFSRE0_EL1, Tag Fault Status Register (EL0).

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.202
TFSRE0_EL1, Tag Fault Status Register (EL0).

# topic.topics[].topics[].topics[].topics[].label
​D24.2.203
TPIDR2_EL0, EL0 Read/Write Software Thread ID Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.203
TPIDR2_EL0, EL0 Read/Write Software Thread ID Register 2

# topic.topics[].topics[].topics[].topics[].label
​D24.2.204
TPIDR_EL0, EL0 Read/Write Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.204
TPIDR_EL0, EL0 Read/Write Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.205
TPIDR_EL1, EL1 Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.205
TPIDR_EL1, EL1 Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.206
TPIDR_EL2, EL2 Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.206
TPIDR_EL2, EL2 Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.207
TPIDR_EL3, EL3 Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.207
TPIDR_EL3, EL3 Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.208
TPIDRRO_EL0, EL0 Read-Only Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.208
TPIDRRO_EL0, EL0 Read-Only Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.209
TTBR0_EL1, Translation Table Base Register 0 (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.209
TTBR0_EL1, Translation Table Base Register 0 (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.210
TTBR0_EL2, Translation Table Base Register 0 (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.210
TTBR0_EL2, Translation Table Base Register 0 (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.211
TTBR0_EL3, Translation Table Base Register 0 (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.211
TTBR0_EL3, Translation Table Base Register 0 (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.212
TTBR1_EL1, Translation Table Base Register 1 (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.212
TTBR1_EL1, Translation Table Base Register 1 (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.213
TTBR1_EL2, Translation Table Base Register 1 (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.213
TTBR1_EL2, Translation Table Base Register 1 (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.214
VBAR_EL1, Vector Base Address Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.214
VBAR_EL1, Vector Base Address Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.215
VBAR_EL2, Vector Base Address Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.215
VBAR_EL2, Vector Base Address Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.216
VBAR_EL3, Vector Base Address Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.216
VBAR_EL3, Vector Base Address Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.217
VMECID_A_EL2, Alternate MECID for EL1&0 stage 2 translation
regime

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.217
VMECID_A_EL2, Alternate MECID for EL1&0 stage 2 translation
regime

# topic.topics[].topics[].topics[].topics[].label
​D24.2.218
VMECID_P_EL2, Primary MECID for EL1&0 stage 2 translation
regime

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.218
VMECID_P_EL2, Primary MECID for EL1&0 stage 2 translation
regime

# topic.topics[].topics[].topics[].topics[].label
​D24.2.220
VNCR_EL2, Virtual Nested Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.220
VNCR_EL2, Virtual Nested Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.221
VPIDR_EL2, Virtualization Processor ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.221
VPIDR_EL2, Virtualization Processor ID Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.222
VSTCR_EL2, Virtualization Secure Translation Control
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.222
VSTCR_EL2, Virtualization Secure Translation Control
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.223
VSTTBR_EL2, Virtualization Secure Translation Table Base
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.223
VSTTBR_EL2, Virtualization Secure Translation Table Base
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.225
VTTBR_EL2, Virtualization Translation Table Base
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.225
VTTBR_EL2, Virtualization Translation Table Base
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.2.226
ZCR_EL1, SVE Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.226
ZCR_EL1, SVE Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.227
ZCR_EL2, SVE Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.227
ZCR_EL2, SVE Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.2.228
ZCR_EL3, SVE Control Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.2.228
ZCR_EL3, SVE Control Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.3.2
DBGBCR<n>_EL1, Debug Breakpoint Control Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.2
DBGBCR<n>_EL1, Debug Breakpoint Control Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].label
​D24.3.3
DBGBVR<n>_EL1, Debug Breakpoint Value Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.3
DBGBVR<n>_EL1, Debug Breakpoint Value Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].label
​D24.3.4
DBGCLAIMCLR_EL1, Debug CLAIM Tag Clear Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.4
DBGCLAIMCLR_EL1, Debug CLAIM Tag Clear Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.5
DBGCLAIMSET_EL1, Debug CLAIM Tag Set Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.5
DBGCLAIMSET_EL1, Debug CLAIM Tag Set Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.6
DBGDTR_EL0, Debug Data Transfer Register, half-duplex

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.6
DBGDTR_EL0, Debug Data Transfer Register, half-duplex

# topic.topics[].topics[].topics[].topics[].label
​D24.3.7
DBGDTRRX_EL0, Debug Data Transfer Register, Receive

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.7
DBGDTRRX_EL0, Debug Data Transfer Register, Receive

# topic.topics[].topics[].topics[].topics[].label
​D24.3.8
DBGDTRTX_EL0, Debug Data Transfer Register, Transmit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.8
DBGDTRTX_EL0, Debug Data Transfer Register, Transmit

# topic.topics[].topics[].topics[].topics[].label
​D24.3.9
DBGPRCR_EL1, Debug Power Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.9
DBGPRCR_EL1, Debug Power Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.10
DBGVCR32_EL2, Debug Vector Catch Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.10
DBGVCR32_EL2, Debug Vector Catch Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.11
DBGWCR<n>_EL1, Debug Watchpoint Control Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.11
DBGWCR<n>_EL1, Debug Watchpoint Control Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].label
​D24.3.12
DBGWVR<n>_EL1, Debug Watchpoint Value Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.12
DBGWVR<n>_EL1, Debug Watchpoint Value Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].label
​D24.3.14
DSPSR_EL0, Debug Saved Program Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.14
DSPSR_EL0, Debug Saved Program Status Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.15
MDCCINT_EL1, Monitor DCC Interrupt Enable Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.15
MDCCINT_EL1, Monitor DCC Interrupt Enable Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.16
MDCCSR_EL0, Monitor DCC Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.16
MDCCSR_EL0, Monitor DCC Status Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.17
MDCR_EL2, Monitor Debug Configuration Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.17
MDCR_EL2, Monitor Debug Configuration Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.3.18
MDCR_EL3, Monitor Debug Configuration Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.18
MDCR_EL3, Monitor Debug Configuration Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.3.19
MDRAR_EL1, Monitor Debug ROM Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.19
MDRAR_EL1, Monitor Debug ROM Address Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.20
MDSCR_EL1, Monitor Debug System Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.20
MDSCR_EL1, Monitor Debug System Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.21
MDSELR_EL1, Breakpoint and Watchpoint Selection Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.21
MDSELR_EL1, Breakpoint and Watchpoint Selection Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.22
MDSTEPOP_EL1, Monitor Debug Step Opcode Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.22
MDSTEPOP_EL1, Monitor Debug Step Opcode Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.23
OSDLR_EL1, OS Double Lock Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.23
OSDLR_EL1, OS Double Lock Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.24
OSDTRRX_EL1, OS Lock Data Transfer Register, Receive

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.24
OSDTRRX_EL1, OS Lock Data Transfer Register, Receive

# topic.topics[].topics[].topics[].topics[].label
​D24.3.25
OSDTRTX_EL1, OS Lock Data Transfer Register, Transmit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.25
OSDTRTX_EL1, OS Lock Data Transfer Register, Transmit

# topic.topics[].topics[].topics[].topics[].label
​D24.3.26
OSECCR_EL1, OS Lock Exception Catch Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.26
OSECCR_EL1, OS Lock Exception Catch Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.27
OSLAR_EL1, OS Lock Access Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.27
OSLAR_EL1, OS Lock Access Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.28
OSLSR_EL1, OS Lock Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.28
OSLSR_EL1, OS Lock Status Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.29
SDER32_EL2, AArch32 Secure Debug Enable Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.29
SDER32_EL2, AArch32 Secure Debug Enable Register

# topic.topics[].topics[].topics[].topics[].label
​D24.3.30
SDER32_EL3, AArch32 Secure Debug Enable Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.3.30
SDER32_EL3, AArch32 Secure Debug Enable Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.1
TRBBASER_EL1, Trace Buffer Base Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.1
TRBBASER_EL1, Trace Buffer Base Address Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.2
TRBIDR_EL1, Trace Buffer ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.2
TRBIDR_EL1, Trace Buffer ID Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.3
TRBLIMITR_EL1, Trace Buffer Limit Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.3
TRBLIMITR_EL1, Trace Buffer Limit Address Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.4
TRBMAR_EL1, Trace Buffer Memory Attribute Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.4
TRBMAR_EL1, Trace Buffer Memory Attribute Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.5
TRBMPAM_EL1, Trace Buffer MPAM Configuration Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.5
TRBMPAM_EL1, Trace Buffer MPAM Configuration Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.6
TRBPTR_EL1, Trace Buffer Write Pointer Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.6
TRBPTR_EL1, Trace Buffer Write Pointer Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.7
TRBSR_EL1, Trace Buffer Status/syndrome Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.7
TRBSR_EL1, Trace Buffer Status/syndrome Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.4.8
TRBSR_EL2, Trace Buffer Syndrome Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.8
TRBSR_EL2, Trace Buffer Syndrome Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.4.9
TRBSR_EL3, Trace Buffer Syndrome Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.9
TRBSR_EL3, Trace Buffer Syndrome Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.4.10
TRBTRG_EL1, Trace Buffer Trigger Counter Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.10
TRBTRG_EL1, Trace Buffer Trigger Counter Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.11
TRCACATR<n>, Trace Address Comparator Access Type Register
<n>, n = 0 - 15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.11
TRCACATR<n>, Trace Address Comparator Access Type Register
<n>, n = 0 - 15

# topic.topics[].topics[].topics[].topics[].label
​D24.4.12
TRCACVR<n>, Trace Address Comparator Value Register
<n>, n = 0 - 15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.12
TRCACVR<n>, Trace Address Comparator Value Register
<n>, n = 0 - 15

# topic.topics[].topics[].topics[].topics[].label
​D24.4.14
TRCAUXCTLR, Trace Auxiliary Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.14
TRCAUXCTLR, Trace Auxiliary Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.15
TRCBBCTLR, Trace Branch Broadcast Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.15
TRCBBCTLR, Trace Branch Broadcast Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.16
TRCCCCTLR, Trace Cycle Count Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.16
TRCCCCTLR, Trace Cycle Count Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.17
TRCCIDCCTLR0, Trace Context Identifier Comparator Control
Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.17
TRCCIDCCTLR0, Trace Context Identifier Comparator Control
Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.4.18
TRCCIDCCTLR1, Trace Context Identifier Comparator Control
Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.18
TRCCIDCCTLR1, Trace Context Identifier Comparator Control
Register 1

# topic.topics[].topics[].topics[].topics[].label
​D24.4.19
TRCCIDCVR<n>, Trace Context Identifier Comparator Value
Registers <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.19
TRCCIDCVR<n>, Trace Context Identifier Comparator Value
Registers <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].label
​D24.4.20
TRCCLAIMCLR, Trace Claim Tag Clear Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.20
TRCCLAIMCLR, Trace Claim Tag Clear Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.21
TRCCLAIMSET, Trace Claim Tag Set Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.21
TRCCLAIMSET, Trace Claim Tag Set Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.22
TRCCNTCTLR<n>, Trace Counter Control Register <n>, n
= 0 - 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.22
TRCCNTCTLR<n>, Trace Counter Control Register <n>, n
= 0 - 3

# topic.topics[].topics[].topics[].topics[].label
​D24.4.23
TRCCNTRLDVR<n>, Trace Counter Reload Value Register
<n>, n = 0 - 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.23
TRCCNTRLDVR<n>, Trace Counter Reload Value Register
<n>, n = 0 - 3

# topic.topics[].topics[].topics[].topics[].label
​D24.4.24
TRCCNTVR<n>, Trace Counter Value Register <n>, n = 0
- 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.24
TRCCNTVR<n>, Trace Counter Value Register <n>, n = 0
- 3

# topic.topics[].topics[].topics[].topics[].label
​D24.4.26
TRCDEVARCH, Trace Device Architecture Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.26
TRCDEVARCH, Trace Device Architecture Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.27
TRCDEVID, Trace Device Configuration Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.27
TRCDEVID, Trace Device Configuration Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.28
TRCEVENTCTL0R, Trace Event Control 0 Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.28
TRCEVENTCTL0R, Trace Event Control 0 Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.29
TRCEVENTCTL1R, Trace Event Control 1 Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.29
TRCEVENTCTL1R, Trace Event Control 1 Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.30
TRCEXTINSELR<n>, Trace External Input Select Register
<n>, n = 0 - 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.30
TRCEXTINSELR<n>, Trace External Input Select Register
<n>, n = 0 - 3

# topic.topics[].topics[].topics[].topics[].label
​D24.4.33
TRCIDR10, Trace ID Register 10

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.33
TRCIDR10, Trace ID Register 10

# topic.topics[].topics[].topics[].topics[].label
​D24.4.34
TRCIDR11, Trace ID Register 11

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.34
TRCIDR11, Trace ID Register 11

# topic.topics[].topics[].topics[].topics[].label
​D24.4.35
TRCIDR12, Trace ID Register 12

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.35
TRCIDR12, Trace ID Register 12

# topic.topics[].topics[].topics[].topics[].label
​D24.4.36
TRCIDR13, Trace ID Register 13

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.36
TRCIDR13, Trace ID Register 13

# topic.topics[].topics[].topics[].topics[].label
​D24.4.45
TRCIMSPEC0, Trace IMP DEF Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.45
TRCIMSPEC0, Trace IMP DEF Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.4.46
TRCIMSPEC<n>, Trace IMP DEF Register <n>, n = 1 -
7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.46
TRCIMSPEC<n>, Trace IMP DEF Register <n>, n = 1 -
7

# topic.topics[].topics[].topics[].topics[].label
​D24.4.48
TRCITECR_EL1, Instrumentation Trace Control Register
(EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.48
TRCITECR_EL1, Instrumentation Trace Control Register
(EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.4.49
TRCITECR_EL2, Instrumentation Trace Control Register
(EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.49
TRCITECR_EL2, Instrumentation Trace Control Register
(EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.4.50
TRCITEEDCR, Instrumentation Trace Extension External Debug
Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.50
TRCITEEDCR, Instrumentation Trace Extension External Debug
Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.51
TRCOSLSR, Trace OS Lock Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.51
TRCOSLSR, Trace OS Lock Status Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.52
TRCPRGCTLR, Trace Programming Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.52
TRCPRGCTLR, Trace Programming Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.53
TRCQCTLR, Trace Q Element Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.53
TRCQCTLR, Trace Q Element Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.54
TRCRSCTLR<n>, Trace Resource Selection Control Register
<n>, n = 2 - 31

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.54
TRCRSCTLR<n>, Trace Resource Selection Control Register
<n>, n = 2 - 31

# topic.topics[].topics[].topics[].topics[].label
​D24.4.55
TRCRSR, Trace Resources Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.55
TRCRSR, Trace Resources Status Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.56
TRCSEQEVR<n>, Trace Sequencer State Transition Control
Register <n>, n = 0 - 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.56
TRCSEQEVR<n>, Trace Sequencer State Transition Control
Register <n>, n = 0 - 2

# topic.topics[].topics[].topics[].topics[].label
​D24.4.57
TRCSEQRSTEVR, Trace Sequencer Reset Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.57
TRCSEQRSTEVR, Trace Sequencer Reset Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.58
TRCSEQSTR, Trace Sequencer State Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.58
TRCSEQSTR, Trace Sequencer State Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.59
TRCSSCCR<n>, Trace Single-shot Comparator Control Register
<n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.59
TRCSSCCR<n>, Trace Single-shot Comparator Control Register
<n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].label
​D24.4.60
TRCSSCSR<n>, Trace Single-shot Comparator Control Status
Register <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.60
TRCSSCSR<n>, Trace Single-shot Comparator Control Status
Register <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].label
​D24.4.61
TRCSSPCICR<n>, Trace Single-shot Processing Element
Comparator Input Control Register <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.61
TRCSSPCICR<n>, Trace Single-shot Processing Element
Comparator Input Control Register <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].label
​D24.4.62
TRCSTALLCTLR, Trace Stall Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.62
TRCSTALLCTLR, Trace Stall Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.63
TRCSTATR, Trace Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.63
TRCSTATR, Trace Status Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.64
TRCSYNCPR, Trace Synchronization Period Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.64
TRCSYNCPR, Trace Synchronization Period Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.65
TRCTRACEIDR, Trace ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.65
TRCTRACEIDR, Trace ID Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.66
TRCTSCTLR, Trace Timestamp Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.66
TRCTSCTLR, Trace Timestamp Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.67
TRCVICTLR, Trace ViewInst Main Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.67
TRCVICTLR, Trace ViewInst Main Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.68
TRCVIIECTLR, Trace ViewInst Include/Exclude Control
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.68
TRCVIIECTLR, Trace ViewInst Include/Exclude Control
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.69
TRCVIPCSSCTLR, Trace ViewInst Start/Stop PE Comparator Control
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.69
TRCVIPCSSCTLR, Trace ViewInst Start/Stop PE Comparator Control
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.70
TRCVISSCTLR, Trace ViewInst Start/Stop Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.70
TRCVISSCTLR, Trace ViewInst Start/Stop Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.4.71
TRCVMIDCCTLR0, Trace Virtual Context Identifier Comparator
Control Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.71
TRCVMIDCCTLR0, Trace Virtual Context Identifier Comparator
Control Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.4.72
TRCVMIDCCTLR1, Trace Virtual Context Identifier Comparator
Control Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.72
TRCVMIDCCTLR1, Trace Virtual Context Identifier Comparator
Control Register 1

# topic.topics[].topics[].topics[].topics[].label
​D24.4.73
TRCVMIDCVR<n>, Trace Virtual Context Identifier Comparator
Value Register <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.73
TRCVMIDCVR<n>, Trace Virtual Context Identifier Comparator
Value Register <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].label
​D24.4.74
TRFCR_EL1, Trace Filter Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.74
TRFCR_EL1, Trace Filter Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.4.75
TRFCR_EL2, Trace Filter Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.4.75
TRFCR_EL2, Trace Filter Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.5.1
PMCCFILTR_EL0, Performance Monitors Cycle Count Filter
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.1
PMCCFILTR_EL0, Performance Monitors Cycle Count Filter
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.2
PMCCNTR_EL0, Performance Monitors Cycle Count Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.2
PMCCNTR_EL0, Performance Monitors Cycle Count Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.3
PMCCNTSVR_EL1, Performance Monitors Cycle Count Saved Value
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.3
PMCCNTSVR_EL1, Performance Monitors Cycle Count Saved Value
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.4
PMCEID0_EL0, Performance Monitors Common Event Identification
Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.4
PMCEID0_EL0, Performance Monitors Common Event Identification
Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.5.5
PMCEID1_EL0, Performance Monitors Common Event Identification
Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.5
PMCEID1_EL0, Performance Monitors Common Event Identification
Register 1

# topic.topics[].topics[].topics[].topics[].label
​D24.5.6
PMCNTENCLR_EL0, Performance Monitors Count Enable Clear
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.6
PMCNTENCLR_EL0, Performance Monitors Count Enable Clear
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.7
PMCNTENSET_EL0, Performance Monitors Count Enable Set
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.7
PMCNTENSET_EL0, Performance Monitors Count Enable Set
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.8
PMCR_EL0, Performance Monitors Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.8
PMCR_EL0, Performance Monitors Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.9
PMECR_EL1, Performance Monitors Extended Control Register
(EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.9
PMECR_EL1, Performance Monitors Extended Control Register
(EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.5.10
PMEVCNTR<n>_EL0, Performance Monitors Event Count
Registers, n = 0 - 30

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.10
PMEVCNTR<n>_EL0, Performance Monitors Event Count
Registers, n = 0 - 30

# topic.topics[].topics[].topics[].topics[].label
​D24.5.11 PMEVCNTSVR<n>_EL1,
Performance Monitors Event Count Saved Value Registers, n = 0 -
30

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.11 PMEVCNTSVR<n>_EL1,
Performance Monitors Event Count Saved Value Registers, n = 0 -
30

# topic.topics[].topics[].topics[].topics[].label
​D24.5.12
PMEVTYPER<n>_EL0, Performance Monitors Event Type
Registers, n = 0 - 30

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.12
PMEVTYPER<n>_EL0, Performance Monitors Event Type
Registers, n = 0 - 30

# topic.topics[].topics[].topics[].topics[].label
​D24.5.13
PMIAR_EL1, Performance Monitors Instruction Address
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.13
PMIAR_EL1, Performance Monitors Instruction Address
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.14
PMICFILTR_EL0, Performance Monitors Instruction Counter Filter
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.14
PMICFILTR_EL0, Performance Monitors Instruction Counter Filter
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.15
PMICNTR_EL0, Performance Monitors Instruction Counter
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.15
PMICNTR_EL0, Performance Monitors Instruction Counter
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.16
PMICNTSVR_EL1, Performance Monitors Instruction Count Saved Value
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.16
PMICNTSVR_EL1, Performance Monitors Instruction Count Saved Value
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.17
PMINTENCLR_EL1, Performance Monitors Interrupt Enable Clear
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.17
PMINTENCLR_EL1, Performance Monitors Interrupt Enable Clear
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.18
PMINTENSET_EL1, Performance Monitors Interrupt Enable Set
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.18
PMINTENSET_EL1, Performance Monitors Interrupt Enable Set
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.20
PMOVSCLR_EL0, Performance Monitors Overflow Flag Status Clear
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.20
PMOVSCLR_EL0, Performance Monitors Overflow Flag Status Clear
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.21
PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.21
PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.22
PMSELR_EL0, Performance Monitors Event Counter Selection
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.22
PMSELR_EL0, Performance Monitors Event Counter Selection
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.23
PMSSCR_EL1, Performance Monitors Snapshot Status and Capture
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.23
PMSSCR_EL1, Performance Monitors Snapshot Status and Capture
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.24
PMSWINC_EL0, Performance Monitors Software Increment
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.24
PMSWINC_EL0, Performance Monitors Software Increment
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.25
PMUACR_EL1, Performance Monitors User Access Control
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.25
PMUACR_EL1, Performance Monitors User Access Control
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.26
PMUSERENR_EL0, Performance Monitors User Enable Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.26
PMUSERENR_EL0, Performance Monitors User Enable Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.27
PMXEVCNTR_EL0, Performance Monitors Selected Event Count
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.27
PMXEVCNTR_EL0, Performance Monitors Selected Event Count
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.28
PMXEVTYPER_EL0, Performance Monitors Selected Event Type
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.28
PMXEVTYPER_EL0, Performance Monitors Selected Event Type
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.29
PMZR_EL0, Performance Monitors Zero with Mask

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.29
PMZR_EL0, Performance Monitors Zero with Mask

# topic.topics[].topics[].topics[].topics[].label
​D24.5.30
SPMACCESSR_EL1, System Performance Monitors Access Register
(EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.30
SPMACCESSR_EL1, System Performance Monitors Access Register
(EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.5.31
SPMACCESSR_EL2, System Performance Monitors Access Register
(EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.31
SPMACCESSR_EL2, System Performance Monitors Access Register
(EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.5.32
SPMACCESSR_EL3, System Performance Monitors Access Register
(EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.32
SPMACCESSR_EL3, System Performance Monitors Access Register
(EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.5.34
SPMCGCR<n>_EL1, System PMU Counter Group Configuration
Registers, n = 0 - 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.34
SPMCGCR<n>_EL1, System PMU Counter Group Configuration
Registers, n = 0 - 1

# topic.topics[].topics[].topics[].topics[].label
​D24.5.35 SPMCNTENCLR_EL0, System
Performance Monitors Count Enable Clear Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.35 SPMCNTENCLR_EL0, System
Performance Monitors Count Enable Clear Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.36 SPMCNTENSET_EL0, System
Performance Monitors Count Enable Set Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.36 SPMCNTENSET_EL0, System
Performance Monitors Count Enable Set Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.37
SPMCR_EL0, System Performance Monitor Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.37
SPMCR_EL0, System Performance Monitor Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.38
SPMDEVAFF_EL1, System Performance Monitors Device Affinity
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.38
SPMDEVAFF_EL1, System Performance Monitors Device Affinity
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.39
SPMDEVARCH_EL1, System Performance Monitors Device Architecture
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.39
SPMDEVARCH_EL1, System Performance Monitors Device Architecture
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.40
SPMEVCNTR<n>_EL0, System Performance Monitors Event Count
Register, n = 0 - 63

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.40
SPMEVCNTR<n>_EL0, System Performance Monitors Event Count
Register, n = 0 - 63

# topic.topics[].topics[].topics[].topics[].label
​D24.5.41 SPMEVFILT2R<n>_EL0, System
Performance Monitors Event Filter Control Register 2, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.41 SPMEVFILT2R<n>_EL0, System
Performance Monitors Event Filter Control Register 2, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].label
​D24.5.42 SPMEVFILTR<n>_EL0, System
Performance Monitors Event Filter Control Register, n = 0 - 63

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.42 SPMEVFILTR<n>_EL0, System
Performance Monitors Event Filter Control Register, n = 0 - 63

# topic.topics[].topics[].topics[].topics[].label
​D24.5.43 SPMEVTYPER<n>_EL0, System
Performance Monitors Event Type Register, n = 0 - 63

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.43 SPMEVTYPER<n>_EL0, System
Performance Monitors Event Type Register, n = 0 - 63

# topic.topics[].topics[].topics[].topics[].label
​D24.5.44
SPMIIDR_EL1, System PMU Implementation Identification
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.44
SPMIIDR_EL1, System PMU Implementation Identification
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.45 SPMINTENCLR_EL1, System
Performance Monitors Interrupt Enable Clear Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.45 SPMINTENCLR_EL1, System
Performance Monitors Interrupt Enable Clear Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.46 SPMINTENSET_EL1, System
Performance Monitors Interrupt Enable Set Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.46 SPMINTENSET_EL1, System
Performance Monitors Interrupt Enable Set Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.47
SPMOVSCLR_EL0, System Performance Monitors Overflow Flag Status
Clear Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.47
SPMOVSCLR_EL0, System Performance Monitors Overflow Flag Status
Clear Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.48
SPMOVSSET_EL0, System Performance Monitors Overflow Flag Status
Set Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.48
SPMOVSSET_EL0, System Performance Monitors Overflow Flag Status
Set Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.49
SPMROOTCR_EL3, System Performance Monitors Root and Realm Control
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.49
SPMROOTCR_EL3, System Performance Monitors Root and Realm Control
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.50
SPMSCR_EL1, System Performance Monitors Secure Control
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.50
SPMSCR_EL1, System Performance Monitors Secure Control
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.51
SPMSELR_EL0, System Performance Monitors Select Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.51
SPMSELR_EL0, System Performance Monitors Select Register

# topic.topics[].topics[].topics[].topics[].label
​D24.5.52
SPMZR_EL0, System Performance Monitors Zero with Mask

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.5.52
SPMZR_EL0, System Performance Monitors Zero with Mask

# topic.topics[].topics[].topics[].topics[].label
​D24.6.2
AMCG1IDR_EL0, Activity Monitors Counter Group 1 Identification
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.6.2
AMCG1IDR_EL0, Activity Monitors Counter Group 1 Identification
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.6.3
AMCGCR_EL0, Activity Monitors Counter Group Configuration
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.6.3
AMCGCR_EL0, Activity Monitors Counter Group Configuration
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.6.4
AMCNTENCLR0_EL0, Activity Monitors Count Enable Clear Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.6.4
AMCNTENCLR0_EL0, Activity Monitors Count Enable Clear Register
0

# topic.topics[].topics[].topics[].topics[].label
​D24.6.5
AMCNTENCLR1_EL0, Activity Monitors Count Enable Clear Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.6.5
AMCNTENCLR1_EL0, Activity Monitors Count Enable Clear Register
1

# topic.topics[].topics[].topics[].topics[].label
​D24.6.6
AMCNTENSET0_EL0, Activity Monitors Count Enable Set Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.6.6
AMCNTENSET0_EL0, Activity Monitors Count Enable Set Register
0

# topic.topics[].topics[].topics[].topics[].label
​D24.6.7
AMCNTENSET1_EL0, Activity Monitors Count Enable Set Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.6.7
AMCNTENSET1_EL0, Activity Monitors Count Enable Set Register
1

# topic.topics[].topics[].topics[].topics[].label
​D24.6.8
AMCR_EL0, Activity Monitors Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.6.8
AMCR_EL0, Activity Monitors Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.6.9
AMEVCNTR0<n>_EL0, Activity Monitors Event Counter Registers
0, n = 0 - 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.6.9
AMEVCNTR0<n>_EL0, Activity Monitors Event Counter Registers
0, n = 0 - 3

# topic.topics[].topics[].topics[].topics[].label
​D24.6.10
AMEVCNTR1<n>_EL0, Activity Monitors Event Counter Registers
1, n = 0 - 15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.6.10
AMEVCNTR1<n>_EL0, Activity Monitors Event Counter Registers
1, n = 0 - 15

# topic.topics[].topics[].topics[].topics[].label
​D24.6.11 AMEVCNTVOFF0<n>_EL2,
Activity Monitors Event Counter Virtual Offset Registers 0, n = 0 -
15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.6.11 AMEVCNTVOFF0<n>_EL2,
Activity Monitors Event Counter Virtual Offset Registers 0, n = 0 -
15

# topic.topics[].topics[].topics[].topics[].label
​D24.6.12 AMEVCNTVOFF1<n>_EL2,
Activity Monitors Event Counter Virtual Offset Registers 1, n = 0 -
15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.6.12 AMEVCNTVOFF1<n>_EL2,
Activity Monitors Event Counter Virtual Offset Registers 1, n = 0 -
15

# topic.topics[].topics[].topics[].topics[].label
​D24.6.13 AMEVTYPER0<n>_EL0, Activity
Monitors Event Type Registers 0, n = 0 - 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.6.13 AMEVTYPER0<n>_EL0, Activity
Monitors Event Type Registers 0, n = 0 - 3

# topic.topics[].topics[].topics[].topics[].label
​D24.6.14 AMEVTYPER1<n>_EL0, Activity
Monitors Event Type Registers 1, n = 0 - 15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.6.14 AMEVTYPER1<n>_EL0, Activity
Monitors Event Type Registers 1, n = 0 - 15

# topic.topics[].topics[].topics[].topics[].label
​D24.6.15
AMUSERENR_EL0, Activity Monitors User Enable Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.6.15
AMUSERENR_EL0, Activity Monitors User Enable Register

# topic.topics[].topics[].topics[].label
​D24.7 Statistical Profiling Extension
registers

# topic.topics[].topics[].topics[].topics[].label
​D24.7.1
PMBIDR_EL1, Profiling Buffer ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.1
PMBIDR_EL1, Profiling Buffer ID Register

# topic.topics[].topics[].topics[].topics[].label
​D24.7.2
PMBLIMITR_EL1, Profiling Buffer Limit Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.2
PMBLIMITR_EL1, Profiling Buffer Limit Address Register

# topic.topics[].topics[].topics[].topics[].label
​D24.7.3
PMBMAR_EL1, Profiling Buffer Memory Attribute Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.3
PMBMAR_EL1, Profiling Buffer Memory Attribute Register

# topic.topics[].topics[].topics[].topics[].label
​D24.7.4
PMBPTR_EL1, Profiling Buffer Write Pointer Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.4
PMBPTR_EL1, Profiling Buffer Write Pointer Register

# topic.topics[].topics[].topics[].topics[].label
​D24.7.5
PMBSR_EL1, Profiling Buffer Status/syndrome Register
(EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.5
PMBSR_EL1, Profiling Buffer Status/syndrome Register
(EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.7.6
PMBSR_EL2, Profiling Buffer Syndrome Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.6
PMBSR_EL2, Profiling Buffer Syndrome Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.7.7
PMBSR_EL3, Profiling Buffer Syndrome Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.7
PMBSR_EL3, Profiling Buffer Syndrome Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.7.8
PMSCR_EL1, Statistical Profiling Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.8
PMSCR_EL1, Statistical Profiling Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.7.9
PMSCR_EL2, Statistical Profiling Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.9
PMSCR_EL2, Statistical Profiling Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.7.10
PMSDSFR_EL1, Sampling Data Source Filter Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.10
PMSDSFR_EL1, Sampling Data Source Filter Register

# topic.topics[].topics[].topics[].topics[].label
​D24.7.11
PMSEVFR_EL1, Sampling Event Filter Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.11
PMSEVFR_EL1, Sampling Event Filter Register

# topic.topics[].topics[].topics[].topics[].label
​D24.7.12
PMSFCR_EL1, Sampling Filter Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.12
PMSFCR_EL1, Sampling Filter Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.7.13
PMSICR_EL1, Sampling Interval Counter Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.13
PMSICR_EL1, Sampling Interval Counter Register

# topic.topics[].topics[].topics[].topics[].label
​D24.7.14
PMSIDR_EL1, Sampling Profiling ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.14
PMSIDR_EL1, Sampling Profiling ID Register

# topic.topics[].topics[].topics[].topics[].label
​D24.7.15
PMSIRR_EL1, Sampling Interval Reload Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.15
PMSIRR_EL1, Sampling Interval Reload Register

# topic.topics[].topics[].topics[].topics[].label
​D24.7.16
PMSLATFR_EL1, Sampling Latency Filter Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.16
PMSLATFR_EL1, Sampling Latency Filter Register

# topic.topics[].topics[].topics[].topics[].label
​D24.7.17
PMSNEVFR_EL1, Sampling Inverted Event Filter Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.7.17
PMSNEVFR_EL1, Sampling Inverted Event Filter Register

# topic.topics[].topics[].topics[].anchors[].title
​D24.7 Statistical Profiling Extension
registers

# topic.topics[].topics[].topics[].label
​D24.8
Branch Record Buffer Extension registers

# topic.topics[].topics[].topics[].topics[].label
​D24.8.1
BRBCR_EL1, Branch Record Buffer Control Register (EL1)

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​D24.8.1
BRBCR_EL1, Branch Record Buffer Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.8.2
BRBCR_EL2, Branch Record Buffer Control Register (EL2)

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​D24.8.2
BRBCR_EL2, Branch Record Buffer Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.8.3
BRBFCR_EL1, Branch Record Buffer Function Control
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.8.3
BRBFCR_EL1, Branch Record Buffer Function Control
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.8.4
BRBIDR0_EL1, Branch Record Buffer ID0 Register

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​D24.8.4
BRBIDR0_EL1, Branch Record Buffer ID0 Register

# topic.topics[].topics[].topics[].topics[].label
​D24.8.5
BRBINFINJ_EL1, Branch Record Buffer Information Injection
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.8.5
BRBINFINJ_EL1, Branch Record Buffer Information Injection
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.8.6
BRBINF<n>_EL1, Branch Record Buffer Information Register
<n>, n = 0 - 31

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​D24.8.6
BRBINF<n>_EL1, Branch Record Buffer Information Register
<n>, n = 0 - 31

# topic.topics[].topics[].topics[].topics[].label
​D24.8.7
BRBSRCINJ_EL1, Branch Record Buffer Source Address Injection
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.8.7
BRBSRCINJ_EL1, Branch Record Buffer Source Address Injection
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.8.8
BRBSRC<n>_EL1, Branch Record Buffer Source Address Register
<n>, n = 0 - 31

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.8.8
BRBSRC<n>_EL1, Branch Record Buffer Source Address Register
<n>, n = 0 - 31

# topic.topics[].topics[].topics[].topics[].label
​D24.8.9
BRBTGTINJ_EL1, Branch Record Buffer Target Address Injection
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.8.9
BRBTGTINJ_EL1, Branch Record Buffer Target Address Injection
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.8.10
BRBTGT<n>_EL1, Branch Record Buffer Target Address Register
<n>, n = 0 - 31

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.8.10
BRBTGT<n>_EL1, Branch Record Buffer Target Address Register
<n>, n = 0 - 31

# topic.topics[].topics[].topics[].topics[].label
​D24.8.11
BRBTS_EL1, Branch Record Buffer Timestamp Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.8.11
BRBTS_EL1, Branch Record Buffer Timestamp Register

# topic.topics[].topics[].topics[].anchors[].title
​D24.8
Branch Record Buffer Extension registers

# topic.topics[].topics[].topics[].topics[].label
​D24.9.1
DISR_EL1, Deferred Interrupt Status Register

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​D24.9.1
DISR_EL1, Deferred Interrupt Status Register

# topic.topics[].topics[].topics[].topics[].label
​D24.9.2
ERRIDR_EL1, Error Record ID Register

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​D24.9.2
ERRIDR_EL1, Error Record ID Register

# topic.topics[].topics[].topics[].topics[].label
​D24.9.3
ERRSELR_EL1, Error Record Select Register

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​D24.9.3
ERRSELR_EL1, Error Record Select Register

# topic.topics[].topics[].topics[].topics[].label
​D24.9.4
ERXADDR_EL1, Selected Error Record Address Register

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​D24.9.4
ERXADDR_EL1, Selected Error Record Address Register

# topic.topics[].topics[].topics[].topics[].label
​D24.9.5
ERXCTLR_EL1, Selected Error Record Control Register

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​D24.9.5
ERXCTLR_EL1, Selected Error Record Control Register

# topic.topics[].topics[].topics[].topics[].label
​D24.9.6
ERXFR_EL1, Selected Error Record Feature Register

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​D24.9.6
ERXFR_EL1, Selected Error Record Feature Register

# topic.topics[].topics[].topics[].topics[].label
​D24.9.7
ERXGSR_EL1, Selected Error Record Group Status Register

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​D24.9.7
ERXGSR_EL1, Selected Error Record Group Status Register

# topic.topics[].topics[].topics[].topics[].label
​D24.9.8
ERXMISC0_EL1, Selected Error Record Miscellaneous Register
0

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​D24.9.8
ERXMISC0_EL1, Selected Error Record Miscellaneous Register
0

# topic.topics[].topics[].topics[].topics[].label
​D24.9.9
ERXMISC1_EL1, Selected Error Record Miscellaneous Register
1

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​D24.9.9
ERXMISC1_EL1, Selected Error Record Miscellaneous Register
1

# topic.topics[].topics[].topics[].topics[].label
​D24.9.10
ERXMISC2_EL1, Selected Error Record Miscellaneous Register
2

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​D24.9.10
ERXMISC2_EL1, Selected Error Record Miscellaneous Register
2

# topic.topics[].topics[].topics[].topics[].label
​D24.9.11
ERXMISC3_EL1, Selected Error Record Miscellaneous Register
3

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​D24.9.11
ERXMISC3_EL1, Selected Error Record Miscellaneous Register
3

# topic.topics[].topics[].topics[].topics[].label
​D24.9.14
ERXPFGF_EL1, Selected Pseudo-fault Generation Feature
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.9.14
ERXPFGF_EL1, Selected Pseudo-fault Generation Feature
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.9.15
ERXSTATUS_EL1, Selected Error Record Primary Status
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.9.15
ERXSTATUS_EL1, Selected Error Record Primary Status
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.9.16
VDISR_EL2, Virtual Deferred Interrupt Status Register
(EL2)

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​D24.9.16
VDISR_EL2, Virtual Deferred Interrupt Status Register
(EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.9.17
VDISR_EL3, Virtual Deferred Interrupt Status Register
(EL3)

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​D24.9.17
VDISR_EL3, Virtual Deferred Interrupt Status Register
(EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.9.18
VSESR_EL2, Virtual SError Exception Syndrome Register
(EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.9.18
VSESR_EL2, Virtual SError Exception Syndrome Register
(EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.9.19
VSESR_EL3, Virtual SError Exception Syndrome Register
(EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.9.19
VSESR_EL3, Virtual SError Exception Syndrome Register
(EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.10.3
CNTHP_CTL_EL2, Counter-timer Hypervisor Physical Timer Control
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.3
CNTHP_CTL_EL2, Counter-timer Hypervisor Physical Timer Control
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.10.4
CNTHP_CVAL_EL2, Counter-timer Physical Timer CompareValue
Register (EL2)

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​D24.10.4
CNTHP_CVAL_EL2, Counter-timer Physical Timer CompareValue
Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.10.5
CNTHP_TVAL_EL2, Counter-timer Physical Timer TimerValue Register
(EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.5
CNTHP_TVAL_EL2, Counter-timer Physical Timer TimerValue Register
(EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.10.6
CNTHPS_CTL_EL2, Counter-timer Secure Physical Timer Control
Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.6
CNTHPS_CTL_EL2, Counter-timer Secure Physical Timer Control
Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.10.7 CNTHPS_CVAL_EL2, Counter-timer
Secure Physical Timer CompareValue Register (EL2)

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​D24.10.7 CNTHPS_CVAL_EL2, Counter-timer
Secure Physical Timer CompareValue Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.10.8 CNTHPS_TVAL_EL2, Counter-timer
Secure Physical Timer TimerValue Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.8 CNTHPS_TVAL_EL2, Counter-timer
Secure Physical Timer TimerValue Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.10.9
CNTHV_CTL_EL2, Counter-timer Virtual Timer Control Register
(EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.9
CNTHV_CTL_EL2, Counter-timer Virtual Timer Control Register
(EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.10.10 CNTHV_CVAL_EL2, Counter-timer
Virtual Timer CompareValue Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.10 CNTHV_CVAL_EL2, Counter-timer
Virtual Timer CompareValue Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.10.11 CNTHV_TVAL_EL2, Counter-timer
Virtual Timer TimerValue Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.11 CNTHV_TVAL_EL2, Counter-timer
Virtual Timer TimerValue Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.10.12 CNTHVS_CTL_EL2, Counter-timer
Secure Virtual Timer Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.12 CNTHVS_CTL_EL2, Counter-timer
Secure Virtual Timer Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.10.13 CNTHVS_CVAL_EL2, Counter-timer
Secure Virtual Timer CompareValue Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.13 CNTHVS_CVAL_EL2, Counter-timer
Secure Virtual Timer CompareValue Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.10.14 CNTHVS_TVAL_EL2, Counter-timer
Secure Virtual Timer TimerValue Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.14 CNTHVS_TVAL_EL2, Counter-timer
Secure Virtual Timer TimerValue Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.10.16
CNTP_CTL_EL0, Counter-timer Physical Timer Control
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.16
CNTP_CTL_EL0, Counter-timer Physical Timer Control
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.10.19
CNTPCT_EL0, Counter-timer Physical Count Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.19
CNTPCT_EL0, Counter-timer Physical Count Register

# topic.topics[].topics[].topics[].topics[].label
​D24.10.22
CNTPS_CTL_EL1, Counter-timer Physical Secure Timer Control
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.22
CNTPS_CTL_EL1, Counter-timer Physical Secure Timer Control
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.10.23 CNTPS_CVAL_EL1, Counter-timer
Physical Secure Timer CompareValue Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.23 CNTPS_CVAL_EL1, Counter-timer
Physical Secure Timer CompareValue Register

# topic.topics[].topics[].topics[].topics[].label
​D24.10.24 CNTPS_TVAL_EL1, Counter-timer
Physical Secure Timer TimerValue Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.24 CNTPS_TVAL_EL1, Counter-timer
Physical Secure Timer TimerValue Register

# topic.topics[].topics[].topics[].topics[].label
​D24.10.25
CNTV_CTL_EL0, Counter-timer Virtual Timer Control
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.25
CNTV_CTL_EL0, Counter-timer Virtual Timer Control
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.10.28
CNTVCT_EL0, Counter-timer Virtual Count Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.10.28
CNTVCT_EL0, Counter-timer Virtual Count Register

# topic.topics[].topics[].topics[].topics[].label
​D24.11.1
GCSCR_EL1, Guarded Control Stack Control Register (EL1)

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​D24.11.1
GCSCR_EL1, Guarded Control Stack Control Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.11.2
GCSCR_EL2, Guarded Control Stack Control Register (EL2)

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​D24.11.2
GCSCR_EL2, Guarded Control Stack Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.11.3
GCSCR_EL3, Guarded Control Stack Control Register (EL3)

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​D24.11.3
GCSCR_EL3, Guarded Control Stack Control Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.11.4
GCSCRE0_EL1, Guarded Control Stack Control Register
(EL0)

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​D24.11.4
GCSCRE0_EL1, Guarded Control Stack Control Register
(EL0)

# topic.topics[].topics[].topics[].topics[].label
​D24.11.5
GCSPR_EL0, Guarded Control Stack Pointer Register (EL0)

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​D24.11.5
GCSPR_EL0, Guarded Control Stack Pointer Register (EL0)

# topic.topics[].topics[].topics[].topics[].label
​D24.11.6
GCSPR_EL1, Guarded Control Stack Pointer Register (EL1)

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​D24.11.6
GCSPR_EL1, Guarded Control Stack Pointer Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.11.7
GCSPR_EL2, Guarded Control Stack Pointer Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.11.7
GCSPR_EL2, Guarded Control Stack Pointer Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.11.8
GCSPR_EL3, Guarded Control Stack Pointer Register (EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.11.8
GCSPR_EL3, Guarded Control Stack Pointer Register (EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.12.5
MPAMBW0_EL1, MPAM PE-side Maximum-bandwidth Control Register
(EL0)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.5
MPAMBW0_EL1, MPAM PE-side Maximum-bandwidth Control Register
(EL0)

# topic.topics[].topics[].topics[].topics[].label
​D24.12.6
MPAMBW1_EL1, MPAM PE-side Maximum-bandwidth Control Register
(EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.6
MPAMBW1_EL1, MPAM PE-side Maximum-bandwidth Control Register
(EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.12.7
MPAMBW2_EL2, MPAM PE-side Maximum-bandwidth Control Register
(EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.7
MPAMBW2_EL2, MPAM PE-side Maximum-bandwidth Control Register
(EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.12.8
MPAMBW3_EL3, MPAM PE-side Maximum-bandwidth Control Register
(EL3)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.8
MPAMBW3_EL3, MPAM PE-side Maximum-bandwidth Control Register
(EL3)

# topic.topics[].topics[].topics[].topics[].label
​D24.12.10
MPAMBWIDR_EL1, MPAM PE-side Bandwidth Controls ID
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.10
MPAMBWIDR_EL1, MPAM PE-side Bandwidth Controls ID
Register

# topic.topics[].topics[].topics[].topics[].label
​D24.12.11
MPAMBWSM_EL1, MPAM Streaming Mode Bandwidth Control Register
(EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.11
MPAMBWSM_EL1, MPAM Streaming Mode Bandwidth Control Register
(EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.12.12
MPAMHCR_EL2, MPAM Hypervisor Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.12
MPAMHCR_EL2, MPAM Hypervisor Control Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​D24.12.13
MPAMIDR_EL1, MPAM ID Register (EL1)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.13
MPAMIDR_EL1, MPAM ID Register (EL1)

# topic.topics[].topics[].topics[].topics[].label
​D24.12.14
MPAMSM_EL1, MPAM Streaming Mode Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.14
MPAMSM_EL1, MPAM Streaming Mode Register

# topic.topics[].topics[].topics[].topics[].label
​D24.12.15
MPAMVPM0_EL2, MPAM Virtual PARTID Mapping Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.15
MPAMVPM0_EL2, MPAM Virtual PARTID Mapping Register 0

# topic.topics[].topics[].topics[].topics[].label
​D24.12.16
MPAMVPM1_EL2, MPAM Virtual PARTID Mapping Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.16
MPAMVPM1_EL2, MPAM Virtual PARTID Mapping Register 1

# topic.topics[].topics[].topics[].topics[].label
​D24.12.17
MPAMVPM2_EL2, MPAM Virtual PARTID Mapping Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.17
MPAMVPM2_EL2, MPAM Virtual PARTID Mapping Register 2

# topic.topics[].topics[].topics[].topics[].label
​D24.12.18
MPAMVPM3_EL2, MPAM Virtual PARTID Mapping Register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.18
MPAMVPM3_EL2, MPAM Virtual PARTID Mapping Register 3

# topic.topics[].topics[].topics[].topics[].label
​D24.12.19
MPAMVPM4_EL2, MPAM Virtual PARTID Mapping Register 4

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.19
MPAMVPM4_EL2, MPAM Virtual PARTID Mapping Register 4

# topic.topics[].topics[].topics[].topics[].label
​D24.12.20
MPAMVPM5_EL2, MPAM Virtual PARTID Mapping Register 5

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.20
MPAMVPM5_EL2, MPAM Virtual PARTID Mapping Register 5

# topic.topics[].topics[].topics[].topics[].label
​D24.12.21
MPAMVPM6_EL2, MPAM Virtual PARTID Mapping Register 6

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.21
MPAMVPM6_EL2, MPAM Virtual PARTID Mapping Register 6

# topic.topics[].topics[].topics[].topics[].label
​D24.12.22
MPAMVPM7_EL2, MPAM Virtual PARTID Mapping Register 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.22
MPAMVPM7_EL2, MPAM Virtual PARTID Mapping Register 7

# topic.topics[].topics[].topics[].topics[].label
​D24.12.23
MPAMVPMV_EL2, MPAM Virtual Partition Mapping Valid
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​D24.12.23
MPAMVPMV_EL2, MPAM Virtual Partition Mapping Valid
Register

# topic.topics[].topics[].anchors[].title
​Chapter
D24 AArch64 System Register Descriptions

# topic.topics[].anchors[].title
​Part D The AArch64 System Level
Architecture

# topic.topics[].label
​Part E The AArch32 Application Level
Architecture

# topic.topics[].topics[].label
​Chapter E1 The AArch32 Application Level
Programmers’ Model

# topic.topics[].topics[].topics[].label
​E1.1 About the Application level
programmers’ model

# topic.topics[].topics[].topics[].anchors[].title
​E1.1 About the Application level
programmers’ model

# topic.topics[].topics[].topics[].label
​E1.2 The Application level programmers’
model in AArch32 state

# topic.topics[].topics[].topics[].topics[].label
​E1.2.1 Instruction sets, arithmetic
operations, and register files

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E1.2.1 Instruction sets, arithmetic
operations, and register files

# topic.topics[].topics[].topics[].topics[].label
​E1.2.2 Core data types and arithmetic in
AArch32 state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E1.2.2 Core data types and arithmetic in
AArch32 state

# topic.topics[].topics[].topics[].topics[].label
​E1.2.3 The general-purpose registers, and
the PC, in AArch32 state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E1.2.3 The general-purpose registers, and
the PC, in AArch32 state

# topic.topics[].topics[].topics[].anchors[].title
​E1.2 The Application level programmers’
model in AArch32 state

# topic.topics[].topics[].topics[].label
​E1.3 Advanced SIMD and floating-point
instructions

# topic.topics[].topics[].topics[].topics[].label
​E1.3.1 The SIMD and floating-point register
file

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E1.3.1 The SIMD and floating-point register
file

# topic.topics[].topics[].topics[].topics[].label
​E1.3.2 Data types supported by the Advanced
SIMD implementation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E1.3.2 Data types supported by the Advanced
SIMD implementation

# topic.topics[].topics[].topics[].topics[].label
​E1.3.3 Advanced SIMD and floating-point
System registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E1.3.3 Advanced SIMD and floating-point
System registers

# topic.topics[].topics[].topics[].topics[].label
​E1.3.4 Floating-point data types and
arithmetic

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E1.3.4 Floating-point data types and
arithmetic

# topic.topics[].topics[].topics[].topics[].label
​E1.3.5 Flushing denormalized numbers to
zero

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E1.3.5 Flushing denormalized numbers to
zero

# topic.topics[].topics[].topics[].topics[].label
​E1.3.6 NaN
handling and the Default NaN

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E1.3.6 NaN
handling and the Default NaN

# topic.topics[].topics[].topics[].topics[].label
​E1.3.8 Floating-point exceptions and
exception traps

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E1.3.8 Floating-point exceptions and
exception traps

# topic.topics[].topics[].topics[].topics[].label
​E1.3.9 Controls of Advanced SIMD operation
that do not apply to floating-point operation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E1.3.9 Controls of Advanced SIMD operation
that do not apply to floating-point operation

# topic.topics[].topics[].topics[].topics[].label
​E1.3.10 Implications of not including
Advanced SIMD and floating-point support

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E1.3.10 Implications of not including
Advanced SIMD and floating-point support

# topic.topics[].topics[].topics[].topics[].label
​E1.3.11 Pseudocode description of
floating-point operations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E1.3.11 Pseudocode description of
floating-point operations

# topic.topics[].topics[].topics[].anchors[].title
​E1.3 Advanced SIMD and floating-point
instructions

# topic.topics[].topics[].topics[].label
​E1.4 About the AArch32 System register
interface

# topic.topics[].topics[].topics[].anchors[].title
​E1.4 About the AArch32 System register
interface

# topic.topics[].topics[].anchors[].title
​Chapter E1 The AArch32 Application Level
Programmers’ Model

# topic.topics[].topics[].label
​Chapter E2 The AArch32 Application Level
Memory Model

# topic.topics[].topics[].topics[].topics[].label
​E2.2.1 Requirements for single-copy
atomicity

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.2.1 Requirements for single-copy
atomicity

# topic.topics[].topics[].topics[].topics[].label
​E2.2.2
Properties of single-copy atomic accesses

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.2.2
Properties of single-copy atomic accesses

# topic.topics[].topics[].topics[].topics[].label
​E2.2.4 Requirements for multi-copy
atomicity

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.2.4 Requirements for multi-copy
atomicity

# topic.topics[].topics[].topics[].topics[].label
​E2.2.5
Concurrent modification and execution of instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.2.5
Concurrent modification and execution of instructions

# topic.topics[].topics[].topics[].topics[].label
​E2.3.1 Basic and dependency
definitions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.3.1 Basic and dependency
definitions

# topic.topics[].topics[].topics[].topics[].label
​E2.3.2 Ordering relations and
constraints

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.3.2 Ordering relations and
constraints

# topic.topics[].topics[].topics[].topics[].label
​E2.3.4 AArch32 restrictions on the effects
of speculation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.3.4 AArch32 restrictions on the effects
of speculation

# topic.topics[].topics[].topics[].label
​E2.4 Ordering of translation table
walks

# topic.topics[].topics[].topics[].anchors[].title
​E2.4 Ordering of translation table
walks

# topic.topics[].topics[].topics[].topics[].label
​E2.5.3 Implication of caches for the
application programmer

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.5.3 Implication of caches for the
application programmer

# topic.topics[].topics[].topics[].topics[].label
​E2.6.3 Cases where unaligned accesses are
CONSTRAINED UNPREDICTABLE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.6.3 Cases where unaligned accesses are
CONSTRAINED UNPREDICTABLE

# topic.topics[].topics[].topics[].topics[].label
​E2.6.4
Unaligned data access restrictions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.6.4
Unaligned data access restrictions

# topic.topics[].topics[].topics[].topics[].label
​E2.6.5 Generation of Alignment faults by
load/store multiple accesses to Device memory

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.6.5 Generation of Alignment faults by
load/store multiple accesses to Device memory

# topic.topics[].topics[].topics[].topics[].label
​E2.7.1 General description of endianness in
the Arm architecture

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.7.1 General description of endianness in
the Arm architecture

# topic.topics[].topics[].topics[].topics[].label
​E2.7.4 Endianness of memory-mapped
peripherals

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.7.4 Endianness of memory-mapped
peripherals

# topic.topics[].topics[].topics[].topics[].label
​E2.10.1 Exclusive access instructions and
Non-shareable memory locations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.10.1 Exclusive access instructions and
Non-shareable memory locations

# topic.topics[].topics[].topics[].topics[].label
​E2.10.2 Exclusive access instructions and
shareable memory locations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.10.2 Exclusive access instructions and
shareable memory locations

# topic.topics[].topics[].topics[].topics[].label
​E2.10.3 Marking and the size of the marked
memory block

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.10.3 Marking and the size of the marked
memory block

# topic.topics[].topics[].topics[].topics[].label
​E2.10.6 Use of WFE and SEV instructions by
spin-locks

# topic.topics[].topics[].topics[].topics[].anchors[].title
​E2.10.6 Use of WFE and SEV instructions by
spin-locks

# topic.topics[].topics[].anchors[].title
​Chapter E2 The AArch32 Application Level
Memory Model

# topic.topics[].anchors[].title
​Part E The AArch32 Application Level
Architecture

# topic.topics[].topics[].label
​Chapter F1 About the T32 and A32
Instruction Descriptions

# topic.topics[].topics[].topics[].label
​F1.1 Format of instruction descriptions

# topic.topics[].topics[].topics[].topics[].label
​F1.1.5 Pseudocode describing how the
instruction operates

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.1.5 Pseudocode describing how the
instruction operates

# topic.topics[].topics[].topics[].anchors[].title
​F1.1 Format of instruction descriptions

# topic.topics[].topics[].topics[].topics[].label
​F1.3.1 The Condition code field in A32
instruction encodings

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.3.1 The Condition code field in A32
instruction encodings

# topic.topics[].topics[].topics[].topics[].label
​F1.3.2 Pseudocode description of
conditional execution

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.3.2 Pseudocode description of
conditional execution

# topic.topics[].topics[].topics[].topics[].label
​F1.4.3 Pseudocode description of
instruction-specified shifts and rotates

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.4.3 Pseudocode description of
instruction-specified shifts and rotates

# topic.topics[].topics[].topics[].label
​F1.6 Encoding of lists of general-purpose
registers and the PC

# topic.topics[].topics[].topics[].anchors[].title
​F1.6 Encoding of lists of general-purpose
registers and the PC

# topic.topics[].topics[].topics[].label
​F1.7 General information about the T32 and
A32 instruction descriptions

# topic.topics[].topics[].topics[].topics[].label
​F1.7.1 Execution of instructions in debug
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.7.1 Execution of instructions in debug
state

# topic.topics[].topics[].topics[].topics[].label
​F1.7.2 Fixed values in AArch32 instruction
and System register descriptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.7.2 Fixed values in AArch32 instruction
and System register descriptions

# topic.topics[].topics[].topics[].topics[].label
​F1.7.3 UNDEFINED, UNPREDICTABLE, and
CONSTRAINED UNPREDICTABLE instruction set space

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.7.3 UNDEFINED, UNPREDICTABLE, and
CONSTRAINED UNPREDICTABLE instruction set space

# topic.topics[].topics[].topics[].topics[].label
​F1.7.4 T32 and A32 Advanced SIMD and
floating-point instruction encodings

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.7.4 T32 and A32 Advanced SIMD and
floating-point instruction encodings

# topic.topics[].topics[].topics[].topics[].label
​F1.7.5 The PC and the use of
0b1111 as a register specifier in T32 and A32
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.7.5 The PC and the use of
0b1111 as a register specifier in T32 and A32
instructions

# topic.topics[].topics[].topics[].topics[].label
​F1.7.6 The SP and the use of
0b1101 as a register specifier in T32 and A32
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.7.6 The SP and the use of
0b1101 as a register specifier in T32 and A32
instructions

# topic.topics[].topics[].topics[].topics[].label
​F1.7.7 Modified immediate constants in T32
and A32 instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.7.7 Modified immediate constants in T32
and A32 instructions

# topic.topics[].topics[].topics[].anchors[].title
​F1.7 General information about the T32 and
A32 instruction descriptions

# topic.topics[].topics[].topics[].label
​F1.8 Additional pseudocode support for
instruction descriptions

# topic.topics[].topics[].topics[].topics[].label
​F1.8.1 Pseudocode description of operations
for System register access instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.8.1 Pseudocode description of operations
for System register access instructions

# topic.topics[].topics[].topics[].topics[].label
​F1.8.2 Pseudocode details of system
calls

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.8.2 Pseudocode details of system
calls

# topic.topics[].topics[].topics[].anchors[].title
​F1.8 Additional pseudocode support for
instruction descriptions

# topic.topics[].topics[].topics[].label
​F1.9 Additional information about Advanced
SIMD and floating-point instructions

# topic.topics[].topics[].topics[].topics[].label
​F1.9.1 Advanced SIMD and floating-point
instruction syntax

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.9.1 Advanced SIMD and floating-point
instruction syntax

# topic.topics[].topics[].topics[].topics[].label
​F1.9.2 The Advanced SIMD addressing
mode

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.9.2 The Advanced SIMD addressing
mode

# topic.topics[].topics[].topics[].topics[].label
​F1.9.3 Advanced SIMD instruction
modifiers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F1.9.3 Advanced SIMD instruction
modifiers

# topic.topics[].topics[].topics[].anchors[].title
​F1.9 Additional information about Advanced
SIMD and floating-point instructions

# topic.topics[].topics[].anchors[].title
​Chapter F1 About the T32 and A32
Instruction Descriptions

# topic.topics[].topics[].label
​Chapter F2 The AArch32 Instruction Sets
Overview

# topic.topics[].topics[].topics[].label
​F2.1 Support for instructions in different
versions of the Arm architecture

# topic.topics[].topics[].topics[].anchors[].title
​F2.1 Support for instructions in different
versions of the Arm architecture

# topic.topics[].topics[].topics[].topics[].label
​F2.2.2 Use of labels in UAL instruction
syntax

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.2.2 Use of labels in UAL instruction
syntax

# topic.topics[].topics[].topics[].topics[].label
​F2.4.5 Saturating addition and subtraction
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.4.5 Saturating addition and subtraction
instructions

# topic.topics[].topics[].topics[].topics[].label
​F2.4.6 Packing and unpacking
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.4.6 Packing and unpacking
instructions

# topic.topics[].topics[].topics[].topics[].label
​F2.4.7 Parallel addition and subtraction
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.4.7 Parallel addition and subtraction
instructions

# topic.topics[].topics[].topics[].label
​F2.5 PSTATE and banked register access
instructions

# topic.topics[].topics[].topics[].topics[].label
​F2.5.2 Banked register access
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.5.2 Banked register access
instructions

# topic.topics[].topics[].topics[].anchors[].title
​F2.5 PSTATE and banked register access
instructions

# topic.topics[].topics[].topics[].topics[].label
​F2.6.2 Halfword and byte loads and
stores

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.6.2 Halfword and byte loads and
stores

# topic.topics[].topics[].topics[].topics[].label
​F2.6.3 Load unprivileged and Store
unprivileged

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.6.3 Load unprivileged and Store
unprivileged

# topic.topics[].topics[].topics[].label
​F2.10 System register access
instructions

# topic.topics[].topics[].topics[].anchors[].title
​F2.10 System register access
instructions

# topic.topics[].topics[].topics[].label
​F2.11 Advanced SIMD and floating-point
load/store instructions

# topic.topics[].topics[].topics[].topics[].label
​F2.11.1 Element and structure load/store
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.11.1 Element and structure load/store
instructions

# topic.topics[].topics[].topics[].anchors[].title
​F2.11 Advanced SIMD and floating-point
load/store instructions

# topic.topics[].topics[].topics[].label
​F2.12 Advanced SIMD and floating-point
register transfer instructions

# topic.topics[].topics[].topics[].anchors[].title
​F2.12 Advanced SIMD and floating-point
register transfer instructions

# topic.topics[].topics[].topics[].topics[].label
​F2.13.1 Advanced SIMD parallel addition and
subtraction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.13.1 Advanced SIMD parallel addition and
subtraction

# topic.topics[].topics[].topics[].topics[].label
​F2.13.2 Bitwise Advanced SIMD
data-processing instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.13.2 Bitwise Advanced SIMD
data-processing instructions

# topic.topics[].topics[].topics[].topics[].label
​F2.13.3 Advanced SIMD comparison
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.13.3 Advanced SIMD comparison
instructions

# topic.topics[].topics[].topics[].topics[].label
​F2.13.4 Advanced SIMD shift
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.13.4 Advanced SIMD shift
instructions

# topic.topics[].topics[].topics[].topics[].label
​F2.13.5 Advanced SIMD multiply
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.13.5 Advanced SIMD multiply
instructions

# topic.topics[].topics[].topics[].topics[].label
​F2.13.6 Advanced SIMD dot product
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.13.6 Advanced SIMD dot product
instructions

# topic.topics[].topics[].topics[].topics[].label
​F2.13.7 AArch32 Advanced SIMD complex
number arithmetic instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.13.7 AArch32 Advanced SIMD complex
number arithmetic instructions

# topic.topics[].topics[].topics[].topics[].label
​F2.13.8 Advanced SIMD BFloat16
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.13.8 Advanced SIMD BFloat16
instructions

# topic.topics[].topics[].topics[].topics[].label
​F2.13.9 Advanced SIMD matrix multiply
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.13.9 Advanced SIMD matrix multiply
instructions

# topic.topics[].topics[].topics[].topics[].label
​F2.13.11
The Cryptographic Extension in AArch32 state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F2.13.11
The Cryptographic Extension in AArch32 state

# topic.topics[].topics[].anchors[].title
​Chapter F2 The AArch32 Instruction Sets
Overview

# topic.topics[].topics[].label
​Chapter F3
T32 Instruction Set Encoding

# topic.topics[].topics[].topics[].topics[].label
​F3.1.2
Shift (immediate), add, subtract, move, and compare

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F3.1.2
Shift (immediate), add, subtract, move, and compare

# topic.topics[].topics[].topics[].topics[].label
​F3.1.3
Special data instructions and branch and exchange

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F3.1.3
Special data instructions and branch and exchange

# topic.topics[].topics[].topics[].topics[].label
​F3.1.5
Conditional branch, and Supervisor Call

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F3.1.5
Conditional branch, and Supervisor Call

# topic.topics[].topics[].topics[].topics[].label
​F3.1.7
System register access, Advanced SIMD, and
floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F3.1.7
System register access, Advanced SIMD, and
floating-point

# topic.topics[].topics[].topics[].topics[].label
​F3.1.9 Advanced SIMD two registers, or
three registers of different lengths

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F3.1.9 Advanced SIMD two registers, or
three registers of different lengths

# topic.topics[].topics[].topics[].topics[].label
​F3.1.10 Advanced SIMD shifts and immediate
generation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F3.1.10 Advanced SIMD shifts and immediate
generation

# topic.topics[].topics[].topics[].topics[].label
​F3.1.11 Advanced SIMD and System register
load/store and 64-bit move

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F3.1.11 Advanced SIMD and System register
load/store and 64-bit move

# topic.topics[].topics[].topics[].topics[].label
​F3.1.12 Advanced SIMD and System register
32-bit move

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F3.1.12 Advanced SIMD and System register
32-bit move

# topic.topics[].topics[].topics[].topics[].label
​F3.1.14 Additional Advanced SIMD and
floating-point instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F3.1.14 Additional Advanced SIMD and
floating-point instructions

# topic.topics[].topics[].topics[].topics[].label
​F3.1.15
Load/store dual, load/store exclusive,
load-acquire/store-release, and table branch

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F3.1.15
Load/store dual, load/store exclusive,
load-acquire/store-release, and table branch

# topic.topics[].topics[].topics[].topics[].label
​F3.1.16
Branches and miscellaneous control

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F3.1.16
Branches and miscellaneous control

# topic.topics[].topics[].topics[].topics[].label
​F3.1.18
Advanced SIMD element or structure load/store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F3.1.18
Advanced SIMD element or structure load/store

# topic.topics[].topics[].topics[].topics[].label
​F3.1.21
Multiply, multiply accumulate, and absolute difference

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F3.1.21
Multiply, multiply accumulate, and absolute difference

# topic.topics[].topics[].topics[].label
​F3.2
About the T32 Advanced SIMD and floating-point instructions and
their encoding

# topic.topics[].topics[].topics[].anchors[].title
​F3.2
About the T32 Advanced SIMD and floating-point instructions and
their encoding

# topic.topics[].topics[].anchors[].title
​Chapter F3
T32 Instruction Set Encoding

# topic.topics[].topics[].label
​Chapter F4
A32 Instruction Set Encoding

# topic.topics[].topics[].topics[].topics[].label
​F4.1.8
Load/Store Word, Unsigned Byte (immediate, literal)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F4.1.8
Load/Store Word, Unsigned Byte (immediate, literal)

# topic.topics[].topics[].topics[].topics[].label
​F4.1.9
Load/Store Word, Unsigned Byte (register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F4.1.9
Load/Store Word, Unsigned Byte (register)

# topic.topics[].topics[].topics[].topics[].label
​F4.1.11
Branch, branch with link, and block data transfer

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F4.1.11
Branch, branch with link, and block data transfer

# topic.topics[].topics[].topics[].topics[].label
​F4.1.12
System register access, Advanced SIMD, floating-point, and
Supervisor call

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F4.1.12
System register access, Advanced SIMD, floating-point, and
Supervisor call

# topic.topics[].topics[].topics[].topics[].label
​F4.1.14 Unconditional Advanced SIMD and
floating-point instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F4.1.14 Unconditional Advanced SIMD and
floating-point instructions

# topic.topics[].topics[].topics[].topics[].label
​F4.1.15 Advanced SIMD and System register
load/store and 64-bit move

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F4.1.15 Advanced SIMD and System register
load/store and 64-bit move

# topic.topics[].topics[].topics[].topics[].label
​F4.1.16 Advanced SIMD and System register
32-bit move

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F4.1.16 Advanced SIMD and System register
32-bit move

# topic.topics[].topics[].topics[].topics[].label
​F4.1.21 Advanced SIMD two registers, or
three registers of different lengths

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F4.1.21 Advanced SIMD two registers, or
three registers of different lengths

# topic.topics[].topics[].topics[].topics[].label
​F4.1.22 Advanced SIMD shifts and immediate
generation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F4.1.22 Advanced SIMD shifts and immediate
generation

# topic.topics[].topics[].topics[].topics[].label
​F4.1.24 Advanced SIMD element or structure
load/store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F4.1.24 Advanced SIMD element or structure
load/store

# topic.topics[].topics[].topics[].label
​F4.2
About the A32 Advanced SIMD and floating-point instructions and
their encoding

# topic.topics[].topics[].topics[].anchors[].title
​F4.2
About the A32 Advanced SIMD and floating-point instructions and
their encoding

# topic.topics[].topics[].anchors[].title
​Chapter F4
A32 Instruction Set Encoding

# topic.topics[].topics[].label
​Chapter F5 T32 and A32 Base Instruction Set
Instruction Descriptions

# topic.topics[].topics[].topics[].label
​F5.1 Alphabetical list of T32 and A32 base
instruction set instructions

# topic.topics[].topics[].topics[].topics[].label
​F5.1.3 ADC, ADCS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.3 ADC, ADCS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].label
​F5.1.7 ADD, ADDS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.7 ADD, ADDS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].label
​F5.1.13 AND, ANDS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.13 AND, ANDS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].label
​F5.1.23 BIC, BICS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.23 BIC, BICS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].label
​F5.1.51 EOR, EORS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.51 EOR, EORS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].label
​F5.1.114 MOV, MOVS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.114 MOV, MOVS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].label
​F5.1.126 MVN, MVNS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.126 MVN, MVNS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].label
​F5.1.132 ORR, ORRS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.132 ORR, ORRS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].label
​F5.1.160 RFE, RFEDA, RFEDB, RFEIA,
RFEIB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.160 RFE, RFEDA, RFEDB, RFEIA,
RFEIB

# topic.topics[].topics[].topics[].topics[].label
​F5.1.169 RSB, RSBS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.169 RSB, RSBS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].label
​F5.1.172 RSC, RSCS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.172 RSC, RSCS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].label
​F5.1.179 SBC, SBCS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.179 SBC, SBCS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].label
​F5.1.194 SMLABB, SMLABT, SMLATB,
SMLATT

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.194 SMLABB, SMLABT, SMLATB,
SMLATT

# topic.topics[].topics[].topics[].topics[].label
​F5.1.197
SMLALBB, SMLALBT, SMLALTB, SMLALTT

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.197
SMLALBB, SMLALBT, SMLALTB, SMLALTT

# topic.topics[].topics[].topics[].topics[].label
​F5.1.206 SMULBB, SMULBT, SMULTB,
SMULTT

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.206 SMULBB, SMULBT, SMULTB,
SMULTT

# topic.topics[].topics[].topics[].topics[].label
​F5.1.210 SRS, SRSDA, SRSDB, SRSIA,
SRSIB

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.210 SRS, SRSDA, SRSDB, SRSIA,
SRSIB

# topic.topics[].topics[].topics[].topics[].label
​F5.1.248 SUB, SUBS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.248 SUB, SUBS (register-shifted
register)

# topic.topics[].topics[].topics[].topics[].label
​F5.1.249 SUB,
SUBS (SP minus immediate)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.1.249 SUB,
SUBS (SP minus immediate)

# topic.topics[].topics[].topics[].anchors[].title
​F5.1 Alphabetical list of T32 and A32 base
instruction set instructions

# topic.topics[].topics[].topics[].label
​F5.2 Encoding and use of banked register
transfer instructions

# topic.topics[].topics[].topics[].topics[].label
​F5.2.1 Register arguments in the banked
register transfer instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.2.1 Register arguments in the banked
register transfer instructions

# topic.topics[].topics[].topics[].topics[].label
​F5.2.2 Usage restrictions on the banked
register transfer instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.2.2 Usage restrictions on the banked
register transfer instructions

# topic.topics[].topics[].topics[].topics[].label
​F5.2.3 Encoding the register argument in
the banked register transfer instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.2.3 Encoding the register argument in
the banked register transfer instructions

# topic.topics[].topics[].topics[].topics[].label
​F5.2.4 Pseudocode support for the banked
register transfer instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F5.2.4 Pseudocode support for the banked
register transfer instructions

# topic.topics[].topics[].topics[].anchors[].title
​F5.2 Encoding and use of banked register
transfer instructions

# topic.topics[].topics[].anchors[].title
​Chapter F5 T32 and A32 Base Instruction Set
Instruction Descriptions

# topic.topics[].topics[].label
​Chapter F6 T32 and A32 Advanced SIMD and
Floating-point Instruction Descriptions

# topic.topics[].topics[].topics[].label
​F6.1 Alphabetical list of Advanced SIMD and
floating-point instructions

# topic.topics[].topics[].topics[].topics[].label
​F6.1.57 VCVT
(from single-precision to BFloat16, Advanced SIMD)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.57 VCVT
(from single-precision to BFloat16, Advanced SIMD)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.59 VCVT
(between half-precision and single-precision, Advanced SIMD)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.59 VCVT
(between half-precision and single-precision, Advanced SIMD)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.60 VCVT
(between floating-point and integer, Advanced SIMD)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.60 VCVT
(between floating-point and integer, Advanced SIMD)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.61 VCVT
(floating-point to integer, floating-point)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.61 VCVT
(floating-point to integer, floating-point)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.62 VCVT
(integer to floating-point, floating-point)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.62 VCVT
(integer to floating-point, floating-point)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.63 VCVT
(between floating-point and fixed-point, Advanced SIMD)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.63 VCVT
(between floating-point and fixed-point, Advanced SIMD)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.64 VCVT
(between floating-point and fixed-point, floating-point)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.64 VCVT
(between floating-point and fixed-point, floating-point)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.87 VFMAB,
VFMAT (BFloat16, vector)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.87 VFMAB,
VFMAT (BFloat16, vector)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.88 VFMAB,
VFMAT (BFloat16, by scalar)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.88 VFMAB,
VFMAT (BFloat16, by scalar)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.100 VLD1 (single element to one
lane)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.100 VLD1 (single element to one
lane)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.101 VLD1 (single element to all
lanes)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.101 VLD1 (single element to all
lanes)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.102 VLD1 (multiple single
elements)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.102 VLD1 (multiple single
elements)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.103 VLD2 (single 2-element structure
to one lane)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.103 VLD2 (single 2-element structure
to one lane)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.104 VLD2 (single 2-element structure
to all lanes)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.104 VLD2 (single 2-element structure
to all lanes)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.105 VLD2 (multiple 2-element
structures)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.105 VLD2 (multiple 2-element
structures)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.106 VLD3 (single 3-element structure
to one lane)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.106 VLD3 (single 3-element structure
to one lane)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.107 VLD3 (single 3-element structure
to all lanes)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.107 VLD3 (single 3-element structure
to all lanes)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.108 VLD3 (multiple 3-element
structures)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.108 VLD3 (multiple 3-element
structures)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.109 VLD4 (single 4-element structure
to one lane)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.109 VLD4 (single 4-element structure
to one lane)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.110 VLD4 (single 4-element structure
to all lanes)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.110 VLD4 (single 4-element structure
to all lanes)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.111 VLD4 (multiple 4-element
structures)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.111 VLD4 (multiple 4-element
structures)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.132 VMOV (between two general-purpose
registers and a doubleword floating-point register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.132 VMOV (between two general-purpose
registers and a doubleword floating-point register)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.133 VMOV (between general-purpose
register and half-precision)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.133 VMOV (between general-purpose
register and half-precision)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.136 VMOV
(general-purpose register to scalar)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.136 VMOV
(general-purpose register to scalar)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.137 VMOV (between general-purpose
register and single-precision)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.137 VMOV (between general-purpose
register and single-precision)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.138 VMOV
(scalar to general-purpose register)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.138 VMOV
(scalar to general-purpose register)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.139 VMOV
(between two general-purpose registers and two single-precision
registers)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.139 VMOV
(between two general-purpose registers and two single-precision
registers)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.149 VMULL
(integer and polynomial)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.149 VMULL
(integer and polynomial)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.223 VSELEQ, VSELGE, VSELGT,
VSELVS

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.223 VSELEQ, VSELGE, VSELGT,
VSELVS

# topic.topics[].topics[].topics[].topics[].label
​F6.1.236 VST1 (single element from one
lane)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.236 VST1 (single element from one
lane)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.237 VST1 (multiple single
elements)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.237 VST1 (multiple single
elements)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.238 VST2 (single 2-element structure
from one lane)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.238 VST2 (single 2-element structure
from one lane)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.239 VST2 (multiple 2-element
structures)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.239 VST2 (multiple 2-element
structures)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.240 VST3 (single 3-element structure
from one lane)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.240 VST3 (single 3-element structure
from one lane)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.241 VST3 (multiple 3-element
structures)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.241 VST3 (multiple 3-element
structures)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.242 VST4 (single 4-element structure
from one lane)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.242 VST4 (single 4-element structure
from one lane)

# topic.topics[].topics[].topics[].topics[].label
​F6.1.243 VST4 (multiple 4-element
structures)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​F6.1.243 VST4 (multiple 4-element
structures)

# topic.topics[].topics[].topics[].anchors[].title
​F6.1 Alphabetical list of Advanced SIMD and
floating-point instructions

# topic.topics[].topics[].anchors[].title
​Chapter F6 T32 and A32 Advanced SIMD and
Floating-point Instruction Descriptions

# topic.topics[].label
​Part G The AArch32 System Level
Architecture

# topic.topics[].topics[].label
​Chapter G1 The AArch32 System Level
Programmers’ Model

# topic.topics[].topics[].topics[].label
​G1.1 About the AArch32 System level
programmers’ model

# topic.topics[].topics[].topics[].anchors[].title
​G1.1 About the AArch32 System level
programmers’ model

# topic.topics[].topics[].topics[].topics[].label
​G1.2.1 Typical Exception level usage
model

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.2.1 Typical Exception level usage
model

# topic.topics[].topics[].topics[].topics[].label
​G1.3.1 Terminology for taking an
exception

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.3.1 Terminology for taking an
exception

# topic.topics[].topics[].topics[].topics[].label
​G1.3.2 Terminology for returning from an
exception

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.3.2 Terminology for returning from an
exception

# topic.topics[].topics[].topics[].topics[].label
​G1.3.4 Definition of a precise
exception

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.3.4 Definition of a precise
exception

# topic.topics[].topics[].topics[].topics[].label
​G1.3.5 Definitions of synchronous and
asynchronous exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.3.5 Definitions of synchronous and
asynchronous exceptions

# topic.topics[].topics[].topics[].label
​G1.7 Security state, Exception levels, and
AArch32 execution privilege

# topic.topics[].topics[].topics[].topics[].label
​G1.7.1 Limited use of Privilege level in
AArch32 state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.7.1 Limited use of Privilege level in
AArch32 state

# topic.topics[].topics[].topics[].anchors[].title
​G1.7 Security state, Exception levels, and
AArch32 execution privilege

# topic.topics[].topics[].topics[].topics[].label
​G1.8.1 The effect of implementing EL2 on
the Exception model

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.8.1 The effect of implementing EL2 on
the Exception model

# topic.topics[].topics[].topics[].topics[].label
​G1.9.3 Pseudocode description of mode
operations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.9.3 Pseudocode description of mode
operations

# topic.topics[].topics[].topics[].label
​G1.10 AArch32 general-purpose registers,
the PC, and the Special-purpose registers

# topic.topics[].topics[].topics[].topics[].label
​G1.10.1 Pseudocode description of
general-purpose register and PC operations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.10.1 Pseudocode description of
general-purpose register and PC operations

# topic.topics[].topics[].topics[].topics[].label
​G1.10.2 Saved Program Status Registers
(SPSRs)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.10.2 Saved Program Status Registers
(SPSRs)

# topic.topics[].topics[].topics[].anchors[].title
​G1.10 AArch32 general-purpose registers,
the PC, and the Special-purpose registers

# topic.topics[].topics[].topics[].topics[].label
​G1.11.2 The Saved Program Status Registers
(SPSRs)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.11.2 The Saved Program Status Registers
(SPSRs)

# topic.topics[].topics[].topics[].topics[].label
​G1.11.4 Pseudocode description of PSTATE
operations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.11.4 Pseudocode description of PSTATE
operations

# topic.topics[].topics[].topics[].topics[].label
​G1.12.1 Exceptions and instruction set
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.12.1 Exceptions and instruction set
state

# topic.topics[].topics[].topics[].label
​G1.13 Handling exceptions that are taken to
an Exception level using AArch32

# topic.topics[].topics[].topics[].topics[].label
​G1.13.1 Exception vectors and the exception
base address

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.13.1 Exception vectors and the exception
base address

# topic.topics[].topics[].topics[].topics[].label
​G1.13.2 Exception prioritization for
exceptions taken to AArch32 state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.13.2 Exception prioritization for
exceptions taken to AArch32 state

# topic.topics[].topics[].topics[].topics[].label
​G1.13.6 Routing exceptions from Non-secure
EL0 to EL2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.13.6 Routing exceptions from Non-secure
EL0 to EL2

# topic.topics[].topics[].topics[].topics[].label
​G1.13.7 Routing debug exceptions to EL2
using AArch32

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.13.7 Routing debug exceptions to EL2
using AArch32

# topic.topics[].topics[].topics[].anchors[].title
​G1.13 Handling exceptions that are taken to
an Exception level using AArch32

# topic.topics[].topics[].topics[].label
​G1.14 Routing of aborts taken to AArch32
state

# topic.topics[].topics[].topics[].anchors[].title
​G1.14 Routing of aborts taken to AArch32
state

# topic.topics[].topics[].topics[].label
​G1.15 Exception return to an Exception
level using AArch32

# topic.topics[].topics[].topics[].topics[].label
​G1.15.3 Illegal return events from AArch32
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.15.3 Illegal return events from AArch32
state

# topic.topics[].topics[].topics[].topics[].label
​G1.15.4 Legal returns that set PSTATE.IL to
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.15.4 Legal returns that set PSTATE.IL to
1

# topic.topics[].topics[].topics[].topics[].label
​G1.15.5 The Illegal Execution state
exception

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.15.5 The Illegal Execution state
exception

# topic.topics[].topics[].topics[].anchors[].title
​G1.15 Exception return to an Exception
level using AArch32

# topic.topics[].topics[].topics[].label
​G1.16 Asynchronous exception behavior for
exceptions taken from AArch32 state

# topic.topics[].topics[].topics[].topics[].label
​G1.16.1 Virtual exceptions when an
implementation includes EL2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.16.1 Virtual exceptions when an
implementation includes EL2

# topic.topics[].topics[].topics[].topics[].label
​G1.16.2 Asynchronous exception routing
controls

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.16.2 Asynchronous exception routing
controls

# topic.topics[].topics[].topics[].topics[].label
​G1.16.3 Asynchronous exception masking
controls

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.16.3 Asynchronous exception masking
controls

# topic.topics[].topics[].topics[].topics[].label
​G1.16.4 Asynchronous exception routing and
masking with higher Exception levels using AArch64

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.16.4 Asynchronous exception routing and
masking with higher Exception levels using AArch64

# topic.topics[].topics[].topics[].topics[].label
​G1.16.5 Taking an interrupt or other
exception during a multiple-register load or store

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.16.5 Taking an interrupt or other
exception during a multiple-register load or store

# topic.topics[].topics[].topics[].anchors[].title
​G1.16 Asynchronous exception behavior for
exceptions taken from AArch32 state

# topic.topics[].topics[].topics[].label
​G1.17 AArch32 state exception
descriptions

# topic.topics[].topics[].topics[].topics[].label
​G1.17.4 Supervisor Call (SVC)
exception

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.17.4 Supervisor Call (SVC)
exception

# topic.topics[].topics[].topics[].topics[].label
​G1.17.5 Secure Monitor Call (SMC)
exception

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.17.5 Secure Monitor Call (SMC)
exception

# topic.topics[].topics[].topics[].topics[].label
​G1.17.6 Hypervisor Call (HVC)
exception

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.17.6 Hypervisor Call (HVC)
exception

# topic.topics[].topics[].topics[].topics[].label
​G1.17.9 Virtual SError interrupt
exception

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.17.9 Virtual SError interrupt
exception

# topic.topics[].topics[].topics[].topics[].label
​G1.17.14 Additional pseudocode functions
for exception handling

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.17.14 Additional pseudocode functions
for exception handling

# topic.topics[].topics[].topics[].anchors[].title
​G1.17 AArch32 state exception
descriptions

# topic.topics[].topics[].topics[].topics[].label
​G1.18.1 PE state on reset into AArch32
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.18.1 PE state on reset into AArch32
state

# topic.topics[].topics[].topics[].topics[].label
​G1.18.2 Pseudocode descriptions of
reset

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.18.2 Pseudocode descriptions of
reset

# topic.topics[].topics[].topics[].label
​G1.19 Mechanisms for entering a low-power
state

# topic.topics[].topics[].topics[].anchors[].title
​G1.19 Mechanisms for entering a low-power
state

# topic.topics[].topics[].topics[].label
​G1.20 The AArch32 System register
interface

# topic.topics[].topics[].topics[].topics[].label
​G1.20.1 System registers in the
coproc == 0b111x encoding space

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.20.1 System registers in the
coproc == 0b111x encoding space

# topic.topics[].topics[].topics[].topics[].label
​G1.20.3 Access controls for Advanced SIMD
and floating-point functionality

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.20.3 Access controls for Advanced SIMD
and floating-point functionality

# topic.topics[].topics[].topics[].topics[].label
​G1.20.4 Background to the System register
interface

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.20.4 Background to the System register
interface

# topic.topics[].topics[].topics[].anchors[].title
​G1.20 The AArch32 System register
interface

# topic.topics[].topics[].topics[].label
​G1.21 Advanced SIMD and floating-point
support

# topic.topics[].topics[].topics[].topics[].label
​G1.21.1 AArch32 implications of not
including support for Advanced SIMD and floating-point

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.21.1 AArch32 implications of not
including support for Advanced SIMD and floating-point

# topic.topics[].topics[].topics[].topics[].label
​G1.21.2 Enabling Advanced SIMD and
floating-point support

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.21.2 Enabling Advanced SIMD and
floating-point support

# topic.topics[].topics[].topics[].topics[].label
​G1.21.3 Advanced SIMD and floating-point
System registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.21.3 Advanced SIMD and floating-point
System registers

# topic.topics[].topics[].topics[].topics[].label
​G1.21.4 Context switching when using
Advanced SIMD and floating-point functionality

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.21.4 Context switching when using
Advanced SIMD and floating-point functionality

# topic.topics[].topics[].topics[].anchors[].title
​G1.21 Advanced SIMD and floating-point
support

# topic.topics[].topics[].topics[].topics[].label
​G1.22.1 Instructions that fail their
Condition code check

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.22.1 Instructions that fail their
Condition code check

# topic.topics[].topics[].topics[].topics[].label
​G1.22.2 Instructions that are
UNPREDICTABLE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.22.2 Instructions that are
UNPREDICTABLE

# topic.topics[].topics[].topics[].topics[].label
​G1.22.7 Pseudocode description of
configurable instruction enables, disables, and traps

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G1.22.7 Pseudocode description of
configurable instruction enables, disables, and traps

# topic.topics[].topics[].anchors[].title
​Chapter G1 The AArch32 System Level
Programmers’ Model

# topic.topics[].topics[].topics[].topics[].label
​G2.1.1 Definition of a debugger in the
context of self-hosted debug

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.1.1 Definition of a debugger in the
context of self-hosted debug

# topic.topics[].topics[].topics[].topics[].label
​G2.2.1 Pseudocode description of routing
debug exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.2.1 Pseudocode description of routing
debug exceptions

# topic.topics[].topics[].topics[].label
​G2.3 The debug exception enable
controls

# topic.topics[].topics[].topics[].topics[].label
​G2.3.2 Disabling debug exceptions from
Secure state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.3.2 Disabling debug exceptions from
Secure state

# topic.topics[].topics[].topics[].topics[].label
​G2.3.3 Pseudocode description of enabling
debug exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.3.3 Pseudocode description of enabling
debug exceptions

# topic.topics[].topics[].topics[].anchors[].title
​G2.3 The debug exception enable
controls

# topic.topics[].topics[].topics[].label
​G2.4 The effect of powerdown on debug
exceptions

# topic.topics[].topics[].topics[].anchors[].title
​G2.4 The effect of powerdown on debug
exceptions

# topic.topics[].topics[].topics[].label
​G2.5 Summary of permitted routing and
enabling of debug exceptions

# topic.topics[].topics[].topics[].anchors[].title
​G2.5 Summary of permitted routing and
enabling of debug exceptions

# topic.topics[].topics[].topics[].label
​G2.6 Pseudocode description of debug
exceptions

# topic.topics[].topics[].topics[].anchors[].title
​G2.6 Pseudocode description of debug
exceptions

# topic.topics[].topics[].topics[].topics[].label
​G2.7.1 About Breakpoint Instruction
exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.7.1 About Breakpoint Instruction
exceptions

# topic.topics[].topics[].topics[].topics[].label
​G2.7.2 Breakpoint instruction in the T32
and A32 instruction sets

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.7.2 Breakpoint instruction in the T32
and A32 instruction sets

# topic.topics[].topics[].topics[].topics[].label
​G2.7.3 BKPT instructions as the first
instruction in an IT block

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.7.3 BKPT instructions as the first
instruction in an IT block

# topic.topics[].topics[].topics[].topics[].label
​G2.7.4 Exception syndrome information and
preferred return address for a BKPT instruction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.7.4 Exception syndrome information and
preferred return address for a BKPT instruction

# topic.topics[].topics[].topics[].topics[].label
​G2.7.5 Pseudocode description of Breakpoint
Instruction exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.7.5 Pseudocode description of Breakpoint
Instruction exceptions

# topic.topics[].topics[].topics[].topics[].label
​G2.8.2 Breakpoint types and linking of
breakpoints

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.8.2 Breakpoint types and linking of
breakpoints

# topic.topics[].topics[].topics[].topics[].label
​G2.8.3 Execution conditions for which a
breakpoint generates Breakpoint exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.8.3 Execution conditions for which a
breakpoint generates Breakpoint exceptions

# topic.topics[].topics[].topics[].topics[].label
​G2.8.7 Exception syndrome information and
preferred return address for a Breakpoint exception

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.8.7 Exception syndrome information and
preferred return address for a Breakpoint exception

# topic.topics[].topics[].topics[].topics[].label
​G2.8.8 Pseudocode description of Breakpoint
exceptions taken from AArch32 state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.8.8 Pseudocode description of Breakpoint
exceptions taken from AArch32 state

# topic.topics[].topics[].topics[].topics[].label
​G2.9.2 Watchpoint types and linking of
watchpoints

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.9.2 Watchpoint types and linking of
watchpoints

# topic.topics[].topics[].topics[].topics[].label
​G2.9.3 Execution conditions for which a
watchpoint generates Watchpoint exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.9.3 Execution conditions for which a
watchpoint generates Watchpoint exceptions

# topic.topics[].topics[].topics[].topics[].label
​G2.9.4 Watchpoint data address
comparisons

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.9.4 Watchpoint data address
comparisons

# topic.topics[].topics[].topics[].topics[].label
​G2.9.5 Watchpoint behavior for certain
instruction classes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.9.5 Watchpoint behavior for certain
instruction classes

# topic.topics[].topics[].topics[].topics[].label
​G2.9.7 Exception syndrome information,
fault address information, and preferred return address

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.9.7 Exception syndrome information,
fault address information, and preferred return address

# topic.topics[].topics[].topics[].topics[].label
​G2.9.8 Pseudocode description of Watchpoint
exceptions taken from AArch32 state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.9.8 Pseudocode description of Watchpoint
exceptions taken from AArch32 state

# topic.topics[].topics[].topics[].topics[].label
​G2.10.2 Exception vectors that Vector Catch
exceptions can be enabled for

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.10.2 Exception vectors that Vector Catch
exceptions can be enabled for

# topic.topics[].topics[].topics[].topics[].label
​G2.10.3 Generation of Vector Catch
exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.10.3 Generation of Vector Catch
exceptions

# topic.topics[].topics[].topics[].topics[].label
​G2.10.5 Exception syndrome information and
preferred return address for a Vector Catch exception

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.10.5 Exception syndrome information and
preferred return address for a Vector Catch exception

# topic.topics[].topics[].topics[].topics[].label
​G2.10.6 Pseudocode description of Vector
Catch exceptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.10.6 Pseudocode description of Vector
Catch exceptions

# topic.topics[].topics[].topics[].label
​G2.11 Synchronization and debug
exceptions

# topic.topics[].topics[].topics[].topics[].label
​G2.11.1 State and mode changes without
explicit Context Synchronization events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G2.11.1 State and mode changes without
explicit Context Synchronization events

# topic.topics[].topics[].topics[].anchors[].title
​G2.11 Synchronization and debug
exceptions

# topic.topics[].topics[].topics[].topics[].label
​G3.1.2 Register controls to enable
self-hosted trace

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G3.1.2 Register controls to enable
self-hosted trace

# topic.topics[].topics[].topics[].label
​G3.2 Prohibited regions in self-hosted
trace

# topic.topics[].topics[].topics[].topics[].label
​G3.2.1 Controls to prohibit trace at
Exception levels

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G3.2.1 Controls to prohibit trace at
Exception levels

# topic.topics[].topics[].topics[].topics[].label
​G3.2.2 Self-hosted trace and address
translation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G3.2.2 Self-hosted trace and address
translation

# topic.topics[].topics[].topics[].anchors[].title
​G3.2 Prohibited regions in self-hosted
trace

# topic.topics[].topics[].topics[].label
​G3.4 Synchronization in self-hosted
trace

# topic.topics[].topics[].topics[].anchors[].title
​G3.4 Synchronization in self-hosted
trace

# topic.topics[].topics[].label
​Chapter G4 The AArch32 System Level Memory
Model

# topic.topics[].topics[].topics[].label
​G4.1 About the memory system
architecture

# topic.topics[].topics[].topics[].topics[].label
​G4.1.1 Form of the memory system
architecture

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G4.1.1 Form of the memory system
architecture

# topic.topics[].topics[].topics[].anchors[].title
​G4.1 About the memory system
architecture

# topic.topics[].topics[].topics[].topics[].label
​G4.2.1 Address space overflow or
underflow

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G4.2.1 Address space overflow or
underflow

# topic.topics[].topics[].topics[].label
​G4.4 AArch32 cache and branch predictor
support

# topic.topics[].topics[].topics[].topics[].label
​G4.4.3 Cacheability, cache allocation
hints, and cache transient hints

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G4.4.3 Cacheability, cache allocation
hints, and cache transient hints

# topic.topics[].topics[].topics[].topics[].label
​G4.4.4 Enabling and disabling the caching
of memory accesses in AArch32 state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G4.4.4 Enabling and disabling the caching
of memory accesses in AArch32 state

# topic.topics[].topics[].topics[].topics[].label
​G4.4.6 About cache maintenance in AArch32
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G4.4.6 About cache maintenance in AArch32
state

# topic.topics[].topics[].topics[].topics[].label
​G4.4.7 AArch32 cache and branch predictor
maintenance instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G4.4.7 AArch32 cache and branch predictor
maintenance instructions

# topic.topics[].topics[].topics[].topics[].label
​G4.4.8 Execution, prefetching and data
prediction restriction System instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G4.4.8 Execution, prefetching and data
prediction restriction System instructions

# topic.topics[].topics[].topics[].anchors[].title
​G4.4 AArch32 cache and branch predictor
support

# topic.topics[].topics[].topics[].label
​G4.5 System register support for
IMPLEMENTATION DEFINED memory features

# topic.topics[].topics[].topics[].anchors[].title
​G4.5 System register support for
IMPLEMENTATION DEFINED memory features

# topic.topics[].topics[].topics[].topics[].label
​G4.6.1 Provision for classification of
External aborts

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G4.6.1 Provision for classification of
External aborts

# topic.topics[].topics[].topics[].topics[].label
​G4.6.2 Parity or ECC error reporting,
FEAT_RAS not implemented

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G4.6.2 Parity or ECC error reporting,
FEAT_RAS not implemented

# topic.topics[].topics[].topics[].topics[].label
​G4.7.1 EL2 control of the Shareability of
data barrier instructions executed at EL0 or EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G4.7.1 EL2 control of the Shareability of
data barrier instructions executed at EL0 or EL1

# topic.topics[].topics[].topics[].label
​G4.8 Pseudocode description of general
memory System instructions

# topic.topics[].topics[].topics[].anchors[].title
​G4.8 Pseudocode description of general
memory System instructions

# topic.topics[].topics[].anchors[].title
​Chapter G4 The AArch32 System Level Memory
Model

# topic.topics[].topics[].label
​Chapter G5 The AArch32 Virtual Memory
System Architecture

# topic.topics[].topics[].topics[].topics[].label
​G5.1.1 The VMSAv8-32 translation
regimes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.1.1 The VMSAv8-32 translation
regimes

# topic.topics[].topics[].topics[].topics[].label
​G5.1.2 Address types used in a VMSAv8-32
description

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.1.2 Address types used in a VMSAv8-32
description

# topic.topics[].topics[].topics[].topics[].label
​G5.1.4 About address translation for
VMSAv8-32

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.1.4 About address translation for
VMSAv8-32

# topic.topics[].topics[].topics[].topics[].label
​G5.1.5 Organization of the remainder of
this chapter

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.1.5 Organization of the remainder of
this chapter

# topic.topics[].topics[].topics[].label
​G5.2 The effects of disabling address
translation stages on VMSAv8-32 behavior

# topic.topics[].topics[].topics[].topics[].label
​G5.2.1 VMSAv8-32 behavior when stage 1
address translation is disabled

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.2.1 VMSAv8-32 behavior when stage 1
address translation is disabled

# topic.topics[].topics[].topics[].topics[].label
​G5.2.2 VMSAv8-32 behavior when stage 2
address translation is disabled

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.2.2 VMSAv8-32 behavior when stage 2
address translation is disabled

# topic.topics[].topics[].topics[].topics[].label
​G5.2.3 Behavior of instruction fetches when
all associated address translations are disabled

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.2.3 Behavior of instruction fetches when
all associated address translations are disabled

# topic.topics[].topics[].topics[].topics[].label
​G5.2.4 Enabling stages of address
translation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.2.4 Enabling stages of address
translation

# topic.topics[].topics[].topics[].anchors[].title
​G5.2 The effects of disabling address
translation stages on VMSAv8-32 behavior

# topic.topics[].topics[].topics[].topics[].label
​G5.3.1 Translation table walks for memory
accesses using VMSAv8-32 translation regimes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.3.1 Translation table walks for memory
accesses using VMSAv8-32 translation regimes

# topic.topics[].topics[].topics[].topics[].label
​G5.3.2 Information returned by a
translation table lookup

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.3.2 Information returned by a
translation table lookup

# topic.topics[].topics[].topics[].topics[].label
​G5.3.3 Determining the translation table
base address in the VMSAv8-32 translation regimes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.3.3 Determining the translation table
base address in the VMSAv8-32 translation regimes

# topic.topics[].topics[].topics[].topics[].label
​G5.3.4 Control of translation table walks
on a TLB miss

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.3.4 Control of translation table walks
on a TLB miss

# topic.topics[].topics[].topics[].topics[].label
​G5.3.5 Access to the Secure or Non-secure
PA map

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.3.5 Access to the Secure or Non-secure
PA map

# topic.topics[].topics[].topics[].label
​G5.4 The VMSAv8-32 Short-descriptor
translation table format

# topic.topics[].topics[].topics[].topics[].label
​G5.4.1 VMSAv8-32 Short-descriptor
Translation Table format descriptors

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.4.1 VMSAv8-32 Short-descriptor
Translation Table format descriptors

# topic.topics[].topics[].topics[].topics[].label
​G5.4.2 Memory attributes in the VMSAv8-32
Short-descriptor Translation Table format descriptors

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.4.2 Memory attributes in the VMSAv8-32
Short-descriptor Translation Table format descriptors

# topic.topics[].topics[].topics[].topics[].label
​G5.4.3 Control of Secure or Non-secure
memory access, VMSAv8-32 Short-descriptor format

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.4.3 Control of Secure or Non-secure
memory access, VMSAv8-32 Short-descriptor format

# topic.topics[].topics[].topics[].topics[].label
​G5.4.4 Selecting between TTBR0 and TTBR1,
VMSAv8-32 Short-descriptor translation table format

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.4.4 Selecting between TTBR0 and TTBR1,
VMSAv8-32 Short-descriptor translation table format

# topic.topics[].topics[].topics[].topics[].label
​G5.4.5 Translation table walks, when using
the VMSAv8-32 Short-descriptor translation table format

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.4.5 Translation table walks, when using
the VMSAv8-32 Short-descriptor translation table format

# topic.topics[].topics[].topics[].anchors[].title
​G5.4 The VMSAv8-32 Short-descriptor
translation table format

# topic.topics[].topics[].topics[].label
​G5.5 The VMSAv8-32 Long-descriptor
translation table format

# topic.topics[].topics[].topics[].topics[].label
​G5.5.1 Overview of VMSAv8-32 address
translation using Long-descriptor translation tables

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.5.1 Overview of VMSAv8-32 address
translation using Long-descriptor translation tables

# topic.topics[].topics[].topics[].topics[].label
​G5.5.2 VMSAv8-32 Long-descriptor
Translation Table format descriptors

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.5.2 VMSAv8-32 Long-descriptor
Translation Table format descriptors

# topic.topics[].topics[].topics[].topics[].label
​G5.5.3 Attribute fields in VMSAv8-32
Long-descriptor translation table format descriptors

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.5.3 Attribute fields in VMSAv8-32
Long-descriptor translation table format descriptors

# topic.topics[].topics[].topics[].topics[].label
​G5.5.4 Control of Secure or Non-secure
memory access, VMSAv8-32 Long-descriptor format

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.5.4 Control of Secure or Non-secure
memory access, VMSAv8-32 Long-descriptor format

# topic.topics[].topics[].topics[].topics[].label
​G5.5.5 Selecting between TTBR0 and TTBR1,
VMSAv8-32 Long-descriptor translation table format

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.5.5 Selecting between TTBR0 and TTBR1,
VMSAv8-32 Long-descriptor translation table format

# topic.topics[].topics[].topics[].topics[].label
​G5.5.6 VMSAv8-32 Long-descriptor
translation table format address lookup levels

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.5.6 VMSAv8-32 Long-descriptor
translation table format address lookup levels

# topic.topics[].topics[].topics[].topics[].label
​G5.5.7 Translation table walks, when using
the VMSAv8-32 Long-descriptor translation table format

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.5.7 Translation table walks, when using
the VMSAv8-32 Long-descriptor translation table format

# topic.topics[].topics[].topics[].topics[].label
​G5.5.8 The algorithm for finding the
translation table entries, VMSAv8-32 Long-descriptor format

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.5.8 The algorithm for finding the
translation table entries, VMSAv8-32 Long-descriptor format

# topic.topics[].topics[].topics[].anchors[].title
​G5.5 The VMSAv8-32 Long-descriptor
translation table format

# topic.topics[].topics[].topics[].topics[].label
​G5.6.3 Access permissions for instruction
execution

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.6.3 Access permissions for instruction
execution

# topic.topics[].topics[].topics[].topics[].label
​G5.6.4 Domains, Short-descriptor format
only

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.6.4 Domains, Short-descriptor format
only

# topic.topics[].topics[].topics[].topics[].label
​G5.6.6 Hyp mode control of Non-secure
access permissions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.6.6 Hyp mode control of Non-secure
access permissions

# topic.topics[].topics[].topics[].topics[].label
​G5.7.1 Overview of memory region attributes
for stage 1 translations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.7.1 Overview of memory region attributes
for stage 1 translations

# topic.topics[].topics[].topics[].topics[].label
​G5.7.2 Short-descriptor format memory
region attributes, without TEX remap

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.7.2 Short-descriptor format memory
region attributes, without TEX remap

# topic.topics[].topics[].topics[].topics[].label
​G5.7.3 Short-descriptor format memory
region attributes, with TEX remap

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.7.3 Short-descriptor format memory
region attributes, with TEX remap

# topic.topics[].topics[].topics[].topics[].label
​G5.7.4 VMSAv8-32 Long-descriptor format
memory region attributes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.7.4 VMSAv8-32 Long-descriptor format
memory region attributes

# topic.topics[].topics[].topics[].topics[].label
​G5.7.5 EL2 control of Non-secure memory
region attributes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.7.5 EL2 control of Non-secure memory
region attributes

# topic.topics[].topics[].topics[].topics[].label
​G5.8.1 Global and process-specific
translation table entries

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.8.1 Global and process-specific
translation table entries

# topic.topics[].topics[].topics[].topics[].label
​G5.9.1 General TLB maintenance
requirements

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.9.1 General TLB maintenance
requirements

# topic.topics[].topics[].topics[].topics[].label
​G5.9.2 Maintenance requirements on changing
System register values

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.9.2 Maintenance requirements on changing
System register values

# topic.topics[].topics[].topics[].topics[].label
​G5.9.3 Atomicity of register changes on
changing virtual machine

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.9.3 Atomicity of register changes on
changing virtual machine

# topic.topics[].topics[].topics[].topics[].label
​G5.9.4 Synchronization of changes of ASID
and TTBR

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.9.4 Synchronization of changes of ASID
and TTBR

# topic.topics[].topics[].topics[].topics[].label
​G5.9.5 The scope of TLB maintenance
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.9.5 The scope of TLB maintenance
instructions

# topic.topics[].topics[].topics[].topics[].label
​G5.10.3 Cache maintenance requirement
created by changing translation table attributes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.10.3 Cache maintenance requirement
created by changing translation table attributes

# topic.topics[].topics[].topics[].topics[].label
​G5.11.2 VMSAv8-32 MMU fault
terminology

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.11.2 VMSAv8-32 MMU fault
terminology

# topic.topics[].topics[].topics[].topics[].label
​G5.11.3 The MMU fault-checking
sequence

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.11.3 The MMU fault-checking
sequence

# topic.topics[].topics[].topics[].topics[].label
​G5.11.5 External abort on a translation
table walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.11.5 External abort on a translation
table walk

# topic.topics[].topics[].topics[].topics[].label
​G5.11.6 AArch32 state prioritization of
synchronous aborts from a single stage of address translation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.11.6 AArch32 state prioritization of
synchronous aborts from a single stage of address translation

# topic.topics[].topics[].topics[].label
​G5.12 Exception reporting in a VMSAv8-32
implementation

# topic.topics[].topics[].topics[].topics[].label
​G5.12.2 Reporting exceptions taken to PL1
modes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.12.2 Reporting exceptions taken to PL1
modes

# topic.topics[].topics[].topics[].topics[].label
​G5.12.4 Summary of register updates on
faults taken to PL1 modes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.12.4 Summary of register updates on
faults taken to PL1 modes

# topic.topics[].topics[].topics[].topics[].label
​G5.12.5 Reporting exceptions taken to Hyp
mode

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.12.5 Reporting exceptions taken to Hyp
mode

# topic.topics[].topics[].topics[].topics[].label
​G5.12.6 Summary of register updates on
exceptions taken to Hyp mode

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.12.6 Summary of register updates on
exceptions taken to Hyp mode

# topic.topics[].topics[].topics[].anchors[].title
​G5.12 Exception reporting in a VMSAv8-32
implementation

# topic.topics[].topics[].topics[].topics[].label
​G5.13.1 Address translation instruction
naming and operation summary

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.13.1 Address translation instruction
naming and operation summary

# topic.topics[].topics[].topics[].topics[].label
​G5.13.2 Encoding and availability of the
address translation instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.13.2 Encoding and availability of the
address translation instructions

# topic.topics[].topics[].topics[].topics[].label
​G5.13.4 Handling of faults and aborts
during an address translation instruction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.13.4 Handling of faults and aborts
during an address translation instruction

# topic.topics[].topics[].topics[].label
​G5.14 Pseudocode description of VMSAv8-32
memory system operations

# topic.topics[].topics[].topics[].topics[].label
​G5.14.4 Long-descriptor Translation table
walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.14.4 Long-descriptor Translation table
walk

# topic.topics[].topics[].topics[].topics[].label
​G5.14.5 Short-descriptor Translation table
walk

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.14.5 Short-descriptor Translation table
walk

# topic.topics[].topics[].topics[].anchors[].title
​G5.14 Pseudocode description of VMSAv8-32
memory system operations

# topic.topics[].topics[].topics[].label
​G5.15 About the System registers for
VMSAv8-32

# topic.topics[].topics[].topics[].topics[].label
​G5.15.1 Classification of System
registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G5.15.1 Classification of System
registers

# topic.topics[].topics[].topics[].anchors[].title
​G5.15 About the System registers for
VMSAv8-32

# topic.topics[].topics[].topics[].label
​G5.16 Functional grouping of VMSAv8-32
System registers

# topic.topics[].topics[].topics[].anchors[].title
​G5.16 Functional grouping of VMSAv8-32
System registers

# topic.topics[].topics[].anchors[].title
​Chapter G5 The AArch32 Virtual Memory
System Architecture

# topic.topics[].topics[].label
​Chapter G6 The Generic Timer in AArch32
state

# topic.topics[].topics[].topics[].label
​G6.1 About the Generic Timer in AArch32
state

# topic.topics[].topics[].topics[].topics[].label
​G6.1.1 The full set of Generic Timer
components

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G6.1.1 The full set of Generic Timer
components

# topic.topics[].topics[].topics[].anchors[].title
​G6.1 About the Generic Timer in AArch32
state

# topic.topics[].topics[].topics[].label
​G6.2 The AArch32 view of the Generic
Timer

# topic.topics[].topics[].topics[].anchors[].title
​G6.2 The AArch32 view of the Generic
Timer

# topic.topics[].topics[].anchors[].title
​Chapter G6 The Generic Timer in AArch32
state

# topic.topics[].topics[].label
​Chapter G7 AArch32 System Register
Encoding

# topic.topics[].topics[].topics[].label
​G7.1 The AArch32 System register encoding
space

# topic.topics[].topics[].topics[].anchors[].title
​G7.1 The AArch32 System register encoding
space

# topic.topics[].topics[].topics[].label
​G7.2 Organization of registers in the (
coproc == 0b1110) encoding space

# topic.topics[].topics[].topics[].topics[].label
​G7.2.1 Register access instruction
arguments, ( coproc == 0b1110)
registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G7.2.1 Register access instruction
arguments, ( coproc == 0b1110)
registers

# topic.topics[].topics[].topics[].anchors[].title
​G7.2 Organization of registers in the (
coproc == 0b1110) encoding space

# topic.topics[].topics[].topics[].label
​G7.3 Organization of registers in the (
coproc == 0b1111) encoding space

# topic.topics[].topics[].topics[].topics[].label
​G7.3.1 System register summary for (
coproc == 0b1111) encodings by CRn
value

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G7.3.1 System register summary for (
coproc == 0b1111) encodings by CRn
value

# topic.topics[].topics[].topics[].topics[].label
​G7.3.2 Full list of AArch32 VMSA System
registers in the ( coproc == 0b1111) encoding
space

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G7.3.2 Full list of AArch32 VMSA System
registers in the ( coproc == 0b1111) encoding
space

# topic.topics[].topics[].topics[].anchors[].title
​G7.3 Organization of registers in the (
coproc == 0b1111) encoding space

# topic.topics[].topics[].anchors[].title
​Chapter G7 AArch32 System Register
Encoding

# topic.topics[].topics[].label
​Chapter
G8 AArch32 System Register Descriptions

# topic.topics[].topics[].topics[].label
​G8.1 About the AArch32 System registers

# topic.topics[].topics[].topics[].topics[].label
​G8.1.1 Fixed values in the System register
descriptions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.1.1 Fixed values in the System register
descriptions

# topic.topics[].topics[].topics[].topics[].label
​G8.1.2 General behavior of System
registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.1.2 General behavior of System
registers

# topic.topics[].topics[].topics[].topics[].label
​G8.1.3 Principles of the ID scheme for
fields in ID registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.1.3 Principles of the ID scheme for
fields in ID registers

# topic.topics[].topics[].topics[].topics[].label
​G8.1.4 About AArch32 System register
accesses

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.1.4 About AArch32 System register
accesses

# topic.topics[].topics[].topics[].anchors[].title
​G8.1 About the AArch32 System registers

# topic.topics[].topics[].topics[].topics[].label
​G8.2.1
ACTLR, Auxiliary Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.1
ACTLR, Auxiliary Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.2
ACTLR2, Auxiliary Control Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.2
ACTLR2, Auxiliary Control Register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.2.3
ADFSR, Auxiliary Data Fault Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.3
ADFSR, Auxiliary Data Fault Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.5
AIFSR, Auxiliary Instruction Fault Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.5
AIFSR, Auxiliary Instruction Fault Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.6
AMAIR0, Auxiliary Memory Attribute Indirection Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.6
AMAIR0, Auxiliary Memory Attribute Indirection Register
0

# topic.topics[].topics[].topics[].topics[].label
​G8.2.7
AMAIR1, Auxiliary Memory Attribute Indirection Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.7
AMAIR1, Auxiliary Memory Attribute Indirection Register
1

# topic.topics[].topics[].topics[].topics[].label
​G8.2.8
APSR, Application Program Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.8
APSR, Application Program Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.9
ATS12NSOPR, Address Translate Stages 1 and 2 Non-secure Only PL1
Read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.9
ATS12NSOPR, Address Translate Stages 1 and 2 Non-secure Only PL1
Read

# topic.topics[].topics[].topics[].topics[].label
​G8.2.10
ATS12NSOPW, Address Translate Stages 1 and 2 Non-secure Only PL1
Write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.10
ATS12NSOPW, Address Translate Stages 1 and 2 Non-secure Only PL1
Write

# topic.topics[].topics[].topics[].topics[].label
​G8.2.11
ATS12NSOUR, Address Translate Stages 1 and 2 Non-secure Only
Unprivileged Read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.11
ATS12NSOUR, Address Translate Stages 1 and 2 Non-secure Only
Unprivileged Read

# topic.topics[].topics[].topics[].topics[].label
​G8.2.12
ATS12NSOUW, Address Translate Stages 1 and 2 Non-secure Only
Unprivileged Write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.12
ATS12NSOUW, Address Translate Stages 1 and 2 Non-secure Only
Unprivileged Write

# topic.topics[].topics[].topics[].topics[].label
​G8.2.13
ATS1CPR, Address Translate Stage 1 Current state PL1
Read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.13
ATS1CPR, Address Translate Stage 1 Current state PL1
Read

# topic.topics[].topics[].topics[].topics[].label
​G8.2.14
ATS1CPRP, Address Translate Stage 1 Current state PL1 Read
PAN

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.14
ATS1CPRP, Address Translate Stage 1 Current state PL1 Read
PAN

# topic.topics[].topics[].topics[].topics[].label
​G8.2.15
ATS1CPW, Address Translate Stage 1 Current state PL1
Write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.15
ATS1CPW, Address Translate Stage 1 Current state PL1
Write

# topic.topics[].topics[].topics[].topics[].label
​G8.2.16
ATS1CPWP, Address Translate Stage 1 Current state PL1 Write
PAN

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.16
ATS1CPWP, Address Translate Stage 1 Current state PL1 Write
PAN

# topic.topics[].topics[].topics[].topics[].label
​G8.2.17
ATS1CUR, Address Translate Stage 1 Current state Unprivileged
Read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.17
ATS1CUR, Address Translate Stage 1 Current state Unprivileged
Read

# topic.topics[].topics[].topics[].topics[].label
​G8.2.18
ATS1CUW, Address Translate Stage 1 Current state Unprivileged
Write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.18
ATS1CUW, Address Translate Stage 1 Current state Unprivileged
Write

# topic.topics[].topics[].topics[].topics[].label
​G8.2.19
ATS1HR, Address Translate Stage 1 Hyp mode Read

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.19
ATS1HR, Address Translate Stage 1 Hyp mode Read

# topic.topics[].topics[].topics[].topics[].label
​G8.2.20
ATS1HW, Address Translate Stage 1 Hyp mode Write

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.20
ATS1HW, Address Translate Stage 1 Hyp mode Write

# topic.topics[].topics[].topics[].topics[].label
​G8.2.21
BPIALL, Branch Predictor Invalidate All

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.21
BPIALL, Branch Predictor Invalidate All

# topic.topics[].topics[].topics[].topics[].label
​G8.2.22
BPIALLIS, Branch Predictor Invalidate All, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.22
BPIALLIS, Branch Predictor Invalidate All, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​G8.2.23
BPIMVA, Branch Predictor Invalidate by VA

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.23
BPIMVA, Branch Predictor Invalidate by VA

# topic.topics[].topics[].topics[].topics[].label
​G8.2.24
CCSIDR, Current Cache Size ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.24
CCSIDR, Current Cache Size ID Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.25
CCSIDR2, Current Cache Size ID Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.25
CCSIDR2, Current Cache Size ID Register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.2.26
CFPRCTX, Control Flow Prediction Restriction by Context

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.26
CFPRCTX, Control Flow Prediction Restriction by Context

# topic.topics[].topics[].topics[].topics[].label
​G8.2.28
CONTEXTIDR, Context ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.28
CONTEXTIDR, Context ID Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.29
COSPRCTX, Clear Other Speculative Prediction Restriction by
Context

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.29
COSPRCTX, Clear Other Speculative Prediction Restriction by
Context

# topic.topics[].topics[].topics[].topics[].label
​G8.2.30
CP15DMB, Data Memory Barrier System instruction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.30
CP15DMB, Data Memory Barrier System instruction

# topic.topics[].topics[].topics[].topics[].label
​G8.2.31
CP15DSB, Data Synchronization Barrier System instruction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.31
CP15DSB, Data Synchronization Barrier System instruction

# topic.topics[].topics[].topics[].topics[].label
​G8.2.32
CP15ISB, Instruction Synchronization Barrier System
instruction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.32
CP15ISB, Instruction Synchronization Barrier System
instruction

# topic.topics[].topics[].topics[].topics[].label
​G8.2.33
CPACR, Architectural Feature Access Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.33
CPACR, Architectural Feature Access Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.34
CPPRCTX, Cache Prefetch Prediction Restriction by
Context

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.34
CPPRCTX, Cache Prefetch Prediction Restriction by
Context

# topic.topics[].topics[].topics[].topics[].label
​G8.2.35
CPSR, Current Program Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.35
CPSR, Current Program Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.36
CSSELR, Cache Size Selection Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.36
CSSELR, Cache Size Selection Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.38
DACR, Domain Access Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.38
DACR, Domain Access Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.39
DCCIMVAC, Data Cache line Clean and Invalidate by VA to
PoC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.39
DCCIMVAC, Data Cache line Clean and Invalidate by VA to
PoC

# topic.topics[].topics[].topics[].topics[].label
​G8.2.40
DCCISW, Data Cache line Clean and Invalidate by Set/Way

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.40
DCCISW, Data Cache line Clean and Invalidate by Set/Way

# topic.topics[].topics[].topics[].topics[].label
​G8.2.41
DCCMVAC, Data Cache line Clean by VA to PoC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.41
DCCMVAC, Data Cache line Clean by VA to PoC

# topic.topics[].topics[].topics[].topics[].label
​G8.2.42
DCCMVAU, Data Cache line Clean by VA to PoU

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.42
DCCMVAU, Data Cache line Clean by VA to PoU

# topic.topics[].topics[].topics[].topics[].label
​G8.2.43
DCCSW, Data Cache line Clean by Set/Way

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.43
DCCSW, Data Cache line Clean by Set/Way

# topic.topics[].topics[].topics[].topics[].label
​G8.2.44
DCIMVAC, Data Cache line Invalidate by VA to PoC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.44
DCIMVAC, Data Cache line Invalidate by VA to PoC

# topic.topics[].topics[].topics[].topics[].label
​G8.2.45
DCISW, Data Cache line Invalidate by Set/Way

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.45
DCISW, Data Cache line Invalidate by Set/Way

# topic.topics[].topics[].topics[].topics[].label
​G8.2.46
DFAR, Data Fault Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.46
DFAR, Data Fault Address Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.47
DFSR, Data Fault Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.47
DFSR, Data Fault Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.48
DTLBIALL, Data TLB Invalidate All

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.48
DTLBIALL, Data TLB Invalidate All

# topic.topics[].topics[].topics[].topics[].label
​G8.2.49
DTLBIASID, Data TLB Invalidate by ASID match

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.49
DTLBIASID, Data TLB Invalidate by ASID match

# topic.topics[].topics[].topics[].topics[].label
​G8.2.50
DTLBIMVA, Data TLB Invalidate by VA

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.50
DTLBIMVA, Data TLB Invalidate by VA

# topic.topics[].topics[].topics[].topics[].label
​G8.2.51
DVPRCTX, Data Value Prediction Restriction by Context

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.51
DVPRCTX, Data Value Prediction Restriction by Context

# topic.topics[].topics[].topics[].topics[].label
​G8.2.52
ELR_hyp, Exception Link Register (Hyp mode)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.52
ELR_hyp, Exception Link Register (Hyp mode)

# topic.topics[].topics[].topics[].topics[].label
​G8.2.53
FCSEIDR, FCSE Process ID register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.53
FCSEIDR, FCSE Process ID register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.54
FPEXC, Floating-Point Exception Control register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.54
FPEXC, Floating-Point Exception Control register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.55
FPSCR, Floating-Point Status and Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.55
FPSCR, Floating-Point Status and Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.56
FPSID, Floating-Point System ID register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.56
FPSID, Floating-Point System ID register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.57
HACR, Hyp Auxiliary Configuration Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.57
HACR, Hyp Auxiliary Configuration Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.58
HACTLR, Hyp Auxiliary Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.58
HACTLR, Hyp Auxiliary Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.59
HACTLR2, Hyp Auxiliary Control Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.59
HACTLR2, Hyp Auxiliary Control Register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.2.60
HADFSR, Hyp Auxiliary Data Fault Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.60
HADFSR, Hyp Auxiliary Data Fault Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.61
HAIFSR, Hyp Auxiliary Instruction Fault Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.61
HAIFSR, Hyp Auxiliary Instruction Fault Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.62
HAMAIR0, Hyp Auxiliary Memory Attribute Indirection Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.62
HAMAIR0, Hyp Auxiliary Memory Attribute Indirection Register
0

# topic.topics[].topics[].topics[].topics[].label
​G8.2.63
HAMAIR1, Hyp Auxiliary Memory Attribute Indirection Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.63
HAMAIR1, Hyp Auxiliary Memory Attribute Indirection Register
1

# topic.topics[].topics[].topics[].topics[].label
​G8.2.64
HCPTR, Hyp Architectural Feature Trap Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.64
HCPTR, Hyp Architectural Feature Trap Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.65 HCR,
Hyp Configuration Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.65 HCR,
Hyp Configuration Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.66
HCR2, Hyp Configuration Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.66
HCR2, Hyp Configuration Register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.2.67
HDFAR, Hyp Data Fault Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.67
HDFAR, Hyp Data Fault Address Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.68
HIFAR, Hyp Instruction Fault Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.68
HIFAR, Hyp Instruction Fault Address Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.69
HMAIR0, Hyp Memory Attribute Indirection Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.69
HMAIR0, Hyp Memory Attribute Indirection Register 0

# topic.topics[].topics[].topics[].topics[].label
​G8.2.70
HMAIR1, Hyp Memory Attribute Indirection Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.70
HMAIR1, Hyp Memory Attribute Indirection Register 1

# topic.topics[].topics[].topics[].topics[].label
​G8.2.71
HPFAR, Hyp IPA Fault Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.71
HPFAR, Hyp IPA Fault Address Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.72
HRMR, Hyp Reset Management Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.72
HRMR, Hyp Reset Management Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.73
HSCTLR, Hyp System Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.73
HSCTLR, Hyp System Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.76
HTCR, Hyp Translation Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.76
HTCR, Hyp Translation Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.77
HTPIDR, Hyp Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.77
HTPIDR, Hyp Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.78
HTTBR, Hyp Translation Table Base Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.78
HTTBR, Hyp Translation Table Base Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.79
HVBAR, Hyp Vector Base Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.79
HVBAR, Hyp Vector Base Address Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.80
ICIALLU, Instruction Cache Invalidate All to PoU

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.80
ICIALLU, Instruction Cache Invalidate All to PoU

# topic.topics[].topics[].topics[].topics[].label
​G8.2.81
ICIALLUIS, Instruction Cache Invalidate All to PoU, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.81
ICIALLUIS, Instruction Cache Invalidate All to PoU, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​G8.2.82
ICIMVAU, Instruction Cache line Invalidate by VA to PoU

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.82
ICIMVAU, Instruction Cache line Invalidate by VA to PoU

# topic.topics[].topics[].topics[].topics[].label
​G8.2.83
ID_AFR0, Auxiliary Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.83
ID_AFR0, Auxiliary Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​G8.2.84
ID_DFR0, Debug Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.84
ID_DFR0, Debug Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​G8.2.85
ID_DFR1, Debug Feature Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.85
ID_DFR1, Debug Feature Register 1

# topic.topics[].topics[].topics[].topics[].label
​G8.2.86
ID_ISAR0, Instruction Set Attribute Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.86
ID_ISAR0, Instruction Set Attribute Register 0

# topic.topics[].topics[].topics[].topics[].label
​G8.2.87
ID_ISAR1, Instruction Set Attribute Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.87
ID_ISAR1, Instruction Set Attribute Register 1

# topic.topics[].topics[].topics[].topics[].label
​G8.2.88
ID_ISAR2, Instruction Set Attribute Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.88
ID_ISAR2, Instruction Set Attribute Register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.2.89
ID_ISAR3, Instruction Set Attribute Register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.89
ID_ISAR3, Instruction Set Attribute Register 3

# topic.topics[].topics[].topics[].topics[].label
​G8.2.90
ID_ISAR4, Instruction Set Attribute Register 4

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.90
ID_ISAR4, Instruction Set Attribute Register 4

# topic.topics[].topics[].topics[].topics[].label
​G8.2.91
ID_ISAR5, Instruction Set Attribute Register 5

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.91
ID_ISAR5, Instruction Set Attribute Register 5

# topic.topics[].topics[].topics[].topics[].label
​G8.2.92
ID_ISAR6, Instruction Set Attribute Register 6

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.92
ID_ISAR6, Instruction Set Attribute Register 6

# topic.topics[].topics[].topics[].topics[].label
​G8.2.93
ID_MMFR0, Memory Model Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.93
ID_MMFR0, Memory Model Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​G8.2.94
ID_MMFR1, Memory Model Feature Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.94
ID_MMFR1, Memory Model Feature Register 1

# topic.topics[].topics[].topics[].topics[].label
​G8.2.95
ID_MMFR2, Memory Model Feature Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.95
ID_MMFR2, Memory Model Feature Register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.2.96
ID_MMFR3, Memory Model Feature Register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.96
ID_MMFR3, Memory Model Feature Register 3

# topic.topics[].topics[].topics[].topics[].label
​G8.2.97
ID_MMFR4, Memory Model Feature Register 4

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.97
ID_MMFR4, Memory Model Feature Register 4

# topic.topics[].topics[].topics[].topics[].label
​G8.2.98
ID_MMFR5, Memory Model Feature Register 5

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.98
ID_MMFR5, Memory Model Feature Register 5

# topic.topics[].topics[].topics[].topics[].label
​G8.2.99
ID_PFR0, Processor Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.99
ID_PFR0, Processor Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​G8.2.100
ID_PFR1, Processor Feature Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.100
ID_PFR1, Processor Feature Register 1

# topic.topics[].topics[].topics[].topics[].label
​G8.2.101
ID_PFR2, Processor Feature Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.101
ID_PFR2, Processor Feature Register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.2.102
IFAR, Instruction Fault Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.102
IFAR, Instruction Fault Address Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.103
IFSR, Instruction Fault Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.103
IFSR, Instruction Fault Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.104
ISR, Interrupt Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.104
ISR, Interrupt Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.105
ITLBIALL, Instruction TLB Invalidate All

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.105
ITLBIALL, Instruction TLB Invalidate All

# topic.topics[].topics[].topics[].topics[].label
​G8.2.106
ITLBIASID, Instruction TLB Invalidate by ASID match

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.106
ITLBIASID, Instruction TLB Invalidate by ASID match

# topic.topics[].topics[].topics[].topics[].label
​G8.2.107
ITLBIMVA, Instruction TLB Invalidate by VA

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.107
ITLBIMVA, Instruction TLB Invalidate by VA

# topic.topics[].topics[].topics[].topics[].label
​G8.2.109
JMCR, Jazelle Main Configuration Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.109
JMCR, Jazelle Main Configuration Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.110
JOSCR, Jazelle OS Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.110
JOSCR, Jazelle OS Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.111
MAIR0, Memory Attribute Indirection Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.111
MAIR0, Memory Attribute Indirection Register 0

# topic.topics[].topics[].topics[].topics[].label
​G8.2.112
MAIR1, Memory Attribute Indirection Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.112
MAIR1, Memory Attribute Indirection Register 1

# topic.topics[].topics[].topics[].topics[].label
​G8.2.115
MVBAR, Monitor Vector Base Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.115
MVBAR, Monitor Vector Base Address Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.116
MVFR0, Media and VFP Feature Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.116
MVFR0, Media and VFP Feature Register 0

# topic.topics[].topics[].topics[].topics[].label
​G8.2.117
MVFR1, Media and VFP Feature Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.117
MVFR1, Media and VFP Feature Register 1

# topic.topics[].topics[].topics[].topics[].label
​G8.2.118
MVFR2, Media and VFP Feature Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.118
MVFR2, Media and VFP Feature Register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.2.119
NMRR, Normal Memory Remap Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.119
NMRR, Normal Memory Remap Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.120
NSACR, Non-Secure Access Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.120
NSACR, Non-Secure Access Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.121
PAR, Physical Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.121
PAR, Physical Address Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.122
PRRR, Primary Region Remap Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.122
PRRR, Primary Region Remap Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.124
RMR, Reset Management Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.124
RMR, Reset Management Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.125
RVBAR, Reset Vector Base Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.125
RVBAR, Reset Vector Base Address Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.126
SCR, Secure Configuration Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.126
SCR, Secure Configuration Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.127
SCTLR, System Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.127
SCTLR, System Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.128
SPSR, Saved Program Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.128
SPSR, Saved Program Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.129
SPSR_abt, Saved Program Status Register (Abort mode)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.129
SPSR_abt, Saved Program Status Register (Abort mode)

# topic.topics[].topics[].topics[].topics[].label
​G8.2.130
SPSR_fiq, Saved Program Status Register (FIQ mode)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.130
SPSR_fiq, Saved Program Status Register (FIQ mode)

# topic.topics[].topics[].topics[].topics[].label
​G8.2.131
SPSR_hyp, Saved Program Status Register (Hyp mode)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.131
SPSR_hyp, Saved Program Status Register (Hyp mode)

# topic.topics[].topics[].topics[].topics[].label
​G8.2.132
SPSR_irq, Saved Program Status Register (IRQ mode)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.132
SPSR_irq, Saved Program Status Register (IRQ mode)

# topic.topics[].topics[].topics[].topics[].label
​G8.2.133
SPSR_mon, Saved Program Status Register (Monitor mode)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.133
SPSR_mon, Saved Program Status Register (Monitor mode)

# topic.topics[].topics[].topics[].topics[].label
​G8.2.134
SPSR_svc, Saved Program Status Register (Supervisor
mode)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.134
SPSR_svc, Saved Program Status Register (Supervisor
mode)

# topic.topics[].topics[].topics[].topics[].label
​G8.2.135
SPSR_und, Saved Program Status Register (Undefined mode)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.135
SPSR_und, Saved Program Status Register (Undefined mode)

# topic.topics[].topics[].topics[].topics[].label
​G8.2.138
TLBIALLH, TLB Invalidate All, Hyp mode

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.138
TLBIALLH, TLB Invalidate All, Hyp mode

# topic.topics[].topics[].topics[].topics[].label
​G8.2.139
TLBIALLHIS, TLB Invalidate All, Hyp mode, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.139
TLBIALLHIS, TLB Invalidate All, Hyp mode, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​G8.2.140
TLBIALLIS, TLB Invalidate All, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.140
TLBIALLIS, TLB Invalidate All, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​G8.2.141
TLBIALLNSNH, TLB Invalidate All, Non-Secure Non-Hyp

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.141
TLBIALLNSNH, TLB Invalidate All, Non-Secure Non-Hyp

# topic.topics[].topics[].topics[].topics[].label
​G8.2.142
TLBIALLNSNHIS, TLB Invalidate All, Non-Secure Non-Hyp, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.142
TLBIALLNSNHIS, TLB Invalidate All, Non-Secure Non-Hyp, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​G8.2.143
TLBIASID, TLB Invalidate by ASID match

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.143
TLBIASID, TLB Invalidate by ASID match

# topic.topics[].topics[].topics[].topics[].label
​G8.2.144
TLBIASIDIS, TLB Invalidate by ASID match, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.144
TLBIASIDIS, TLB Invalidate by ASID match, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​G8.2.145
TLBIIPAS2, TLB Invalidate by Intermediate Physical Address, Stage
2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.145
TLBIIPAS2, TLB Invalidate by Intermediate Physical Address, Stage
2

# topic.topics[].topics[].topics[].topics[].label
​G8.2.146
TLBIIPAS2IS, TLB Invalidate by Intermediate Physical Address,
Stage 2, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.146
TLBIIPAS2IS, TLB Invalidate by Intermediate Physical Address,
Stage 2, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​G8.2.147
TLBIIPAS2L, TLB Invalidate by Intermediate Physical Address,
Stage 2, Last level

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.147
TLBIIPAS2L, TLB Invalidate by Intermediate Physical Address,
Stage 2, Last level

# topic.topics[].topics[].topics[].topics[].label
​G8.2.148
TLBIIPAS2LIS, TLB Invalidate by Intermediate Physical Address,
Stage 2, Last level, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.148
TLBIIPAS2LIS, TLB Invalidate by Intermediate Physical Address,
Stage 2, Last level, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​G8.2.150
TLBIMVAA, TLB Invalidate by VA, All ASID

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.150
TLBIMVAA, TLB Invalidate by VA, All ASID

# topic.topics[].topics[].topics[].topics[].label
​G8.2.151
TLBIMVAAIS, TLB Invalidate by VA, All ASID, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.151
TLBIMVAAIS, TLB Invalidate by VA, All ASID, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​G8.2.152
TLBIMVAAL, TLB Invalidate by VA, All ASID, Last level

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.152
TLBIMVAAL, TLB Invalidate by VA, All ASID, Last level

# topic.topics[].topics[].topics[].topics[].label
​G8.2.153
TLBIMVAALIS, TLB Invalidate by VA, All ASID, Last level, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.153
TLBIMVAALIS, TLB Invalidate by VA, All ASID, Last level, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​G8.2.154
TLBIMVAH, TLB Invalidate by VA, Hyp mode

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.154
TLBIMVAH, TLB Invalidate by VA, Hyp mode

# topic.topics[].topics[].topics[].topics[].label
​G8.2.155
TLBIMVAHIS, TLB Invalidate by VA, Hyp mode, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.155
TLBIMVAHIS, TLB Invalidate by VA, Hyp mode, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​G8.2.156
TLBIMVAIS, TLB Invalidate by VA, Inner Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.156
TLBIMVAIS, TLB Invalidate by VA, Inner Shareable

# topic.topics[].topics[].topics[].topics[].label
​G8.2.157
TLBIMVAL, TLB Invalidate by VA, Last level

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.157
TLBIMVAL, TLB Invalidate by VA, Last level

# topic.topics[].topics[].topics[].topics[].label
​G8.2.158
TLBIMVALH, TLB Invalidate by VA, Last level, Hyp mode

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.158
TLBIMVALH, TLB Invalidate by VA, Last level, Hyp mode

# topic.topics[].topics[].topics[].topics[].label
​G8.2.159
TLBIMVALHIS, TLB Invalidate by VA, Last level, Hyp mode, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.159
TLBIMVALHIS, TLB Invalidate by VA, Last level, Hyp mode, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​G8.2.160
TLBIMVALIS, TLB Invalidate by VA, Last level, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.160
TLBIMVALIS, TLB Invalidate by VA, Last level, Inner
Shareable

# topic.topics[].topics[].topics[].topics[].label
​G8.2.162
TPIDRPRW, PL1 Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.162
TPIDRPRW, PL1 Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.163
TPIDRURO, PL0 Read-Only Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.163
TPIDRURO, PL0 Read-Only Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.164
TPIDRURW, PL0 Read/Write Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.164
TPIDRURW, PL0 Read/Write Software Thread ID Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.165
TTBCR, Translation Table Base Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.165
TTBCR, Translation Table Base Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.166
TTBCR2, Translation Table Base Control Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.166
TTBCR2, Translation Table Base Control Register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.2.167
TTBR0, Translation Table Base Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.167
TTBR0, Translation Table Base Register 0

# topic.topics[].topics[].topics[].topics[].label
​G8.2.168
TTBR1, Translation Table Base Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.168
TTBR1, Translation Table Base Register 1

# topic.topics[].topics[].topics[].topics[].label
​G8.2.169
VBAR, Vector Base Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.169
VBAR, Vector Base Address Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.170
VMPIDR, Virtualization Multiprocessor ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.170
VMPIDR, Virtualization Multiprocessor ID Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.171
VPIDR, Virtualization Processor ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.171
VPIDR, Virtualization Processor ID Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.172
VTCR, Virtualization Translation Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.172
VTCR, Virtualization Translation Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.2.173
VTTBR, Virtualization Translation Table Base Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.2.173
VTTBR, Virtualization Translation Table Base Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.1
DBGAUTHSTATUS, Debug Authentication Status register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.1
DBGAUTHSTATUS, Debug Authentication Status register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.2
DBGBCR<n>, Debug Breakpoint Control Registers, n = 0 -
15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.2
DBGBCR<n>, Debug Breakpoint Control Registers, n = 0 -
15

# topic.topics[].topics[].topics[].topics[].label
​G8.3.3
DBGBVR<n>, Debug Breakpoint Value Registers, n = 0 -
15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.3
DBGBVR<n>, Debug Breakpoint Value Registers, n = 0 -
15

# topic.topics[].topics[].topics[].topics[].label
​G8.3.4
DBGBXVR<n>, Debug Breakpoint Extended Value Registers, n =
0 - 15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.4
DBGBXVR<n>, Debug Breakpoint Extended Value Registers, n =
0 - 15

# topic.topics[].topics[].topics[].topics[].label
​G8.3.5
DBGCLAIMCLR, Debug CLAIM Tag Clear register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.5
DBGCLAIMCLR, Debug CLAIM Tag Clear register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.6
DBGCLAIMSET, Debug CLAIM Tag Set register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.6
DBGCLAIMSET, Debug CLAIM Tag Set register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.7
DBGDCCINT, DCC Interrupt Enable Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.7
DBGDCCINT, DCC Interrupt Enable Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.8
DBGDEVID, Debug Device ID register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.8
DBGDEVID, Debug Device ID register 0

# topic.topics[].topics[].topics[].topics[].label
​G8.3.9
DBGDEVID1, Debug Device ID register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.9
DBGDEVID1, Debug Device ID register 1

# topic.topics[].topics[].topics[].topics[].label
​G8.3.10
DBGDEVID2, Debug Device ID register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.10
DBGDEVID2, Debug Device ID register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.3.12
DBGDRAR, Debug ROM Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.12
DBGDRAR, Debug ROM Address Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.13
DBGDSAR, Debug Self Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.13
DBGDSAR, Debug Self Address Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.14
DBGDSCRext, Debug Status and Control Register, External
View

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.14
DBGDSCRext, Debug Status and Control Register, External
View

# topic.topics[].topics[].topics[].topics[].label
​G8.3.15
DBGDSCRint, Debug Status and Control Register, Internal
View

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.15
DBGDSCRint, Debug Status and Control Register, Internal
View

# topic.topics[].topics[].topics[].topics[].label
​G8.3.16
DBGDTRRXext, Debug OS Lock Data Transfer Register, Receive,
External View

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.16
DBGDTRRXext, Debug OS Lock Data Transfer Register, Receive,
External View

# topic.topics[].topics[].topics[].topics[].label
​G8.3.17
DBGDTRRXint, Debug Data Transfer Register, Receive

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.17
DBGDTRRXint, Debug Data Transfer Register, Receive

# topic.topics[].topics[].topics[].topics[].label
​G8.3.18
DBGDTRTXext, Debug OS Lock Data Transfer Register,
Transmit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.18
DBGDTRTXext, Debug OS Lock Data Transfer Register,
Transmit

# topic.topics[].topics[].topics[].topics[].label
​G8.3.19
DBGDTRTXint, Debug Data Transfer Register, Transmit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.19
DBGDTRTXint, Debug Data Transfer Register, Transmit

# topic.topics[].topics[].topics[].topics[].label
​G8.3.20
DBGOSDLR, Debug OS Double Lock Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.20
DBGOSDLR, Debug OS Double Lock Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.21
DBGOSECCR, Debug OS Lock Exception Catch Control
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.21
DBGOSECCR, Debug OS Lock Exception Catch Control
Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.22
DBGOSLAR, Debug OS Lock Access Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.22
DBGOSLAR, Debug OS Lock Access Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.23
DBGOSLSR, Debug OS Lock Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.23
DBGOSLSR, Debug OS Lock Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.24
DBGPRCR, Debug Power Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.24
DBGPRCR, Debug Power Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.25
DBGVCR, Debug Vector Catch Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.25
DBGVCR, Debug Vector Catch Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.26
DBGWCR<n>, Debug Watchpoint Control Registers, n = 0 -
15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.26
DBGWCR<n>, Debug Watchpoint Control Registers, n = 0 -
15

# topic.topics[].topics[].topics[].topics[].label
​G8.3.27
DBGWFAR, Debug Watchpoint Fault Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.27
DBGWFAR, Debug Watchpoint Fault Address Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.28
DBGWVR<n>, Debug Watchpoint Value Registers, n = 0 -
15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.28
DBGWVR<n>, Debug Watchpoint Value Registers, n = 0 -
15

# topic.topics[].topics[].topics[].topics[].label
​G8.3.30
DSPSR, Debug Saved Program Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.30
DSPSR, Debug Saved Program Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.31
DSPSR2, Debug Saved Process State Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.31
DSPSR2, Debug Saved Process State Register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.3.32
HDCR, Hyp Debug Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.32
HDCR, Hyp Debug Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.33
HTRFCR, Hyp Trace Filter Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.33
HTRFCR, Hyp Trace Filter Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.34
PMMIR, Performance Monitors Machine Identification
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.34
PMMIR, Performance Monitors Machine Identification
Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.35
SDCR, Secure Debug Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.35
SDCR, Secure Debug Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.36
SDER, Secure Debug Enable Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.36
SDER, Secure Debug Enable Register

# topic.topics[].topics[].topics[].topics[].label
​G8.3.37
TRFCR, Trace Filter Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.3.37
TRFCR, Trace Filter Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.4.1
PMCCFILTR, Performance Monitors Cycle Count Filter
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.1
PMCCFILTR, Performance Monitors Cycle Count Filter
Register

# topic.topics[].topics[].topics[].topics[].label
​G8.4.2
PMCCNTR, Performance Monitors Cycle Count Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.2
PMCCNTR, Performance Monitors Cycle Count Register

# topic.topics[].topics[].topics[].topics[].label
​G8.4.3
PMCEID0, Performance Monitors Common Event Identification
register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.3
PMCEID0, Performance Monitors Common Event Identification
register 0

# topic.topics[].topics[].topics[].topics[].label
​G8.4.4
PMCEID1, Performance Monitors Common Event Identification
register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.4
PMCEID1, Performance Monitors Common Event Identification
register 1

# topic.topics[].topics[].topics[].topics[].label
​G8.4.5
PMCEID2, Performance Monitors Common Event Identification
register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.5
PMCEID2, Performance Monitors Common Event Identification
register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.4.6
PMCEID3, Performance Monitors Common Event Identification
register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.6
PMCEID3, Performance Monitors Common Event Identification
register 3

# topic.topics[].topics[].topics[].topics[].label
​G8.4.7
PMCNTENCLR, Performance Monitors Count Enable Clear
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.7
PMCNTENCLR, Performance Monitors Count Enable Clear
register

# topic.topics[].topics[].topics[].topics[].label
​G8.4.8
PMCNTENSET, Performance Monitors Count Enable Set
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.8
PMCNTENSET, Performance Monitors Count Enable Set
register

# topic.topics[].topics[].topics[].topics[].label
​G8.4.9
PMCR, Performance Monitors Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.9
PMCR, Performance Monitors Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.4.10
PMEVCNTR<n>, Performance Monitors Event Count Registers, n
= 0 - 30

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.10
PMEVCNTR<n>, Performance Monitors Event Count Registers, n
= 0 - 30

# topic.topics[].topics[].topics[].topics[].label
​G8.4.11
PMEVTYPER<n>, Performance Monitors Event Type Registers, n
= 0 - 30

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.11
PMEVTYPER<n>, Performance Monitors Event Type Registers, n
= 0 - 30

# topic.topics[].topics[].topics[].topics[].label
​G8.4.12
PMINTENCLR, Performance Monitors Interrupt Enable Clear
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.12
PMINTENCLR, Performance Monitors Interrupt Enable Clear
register

# topic.topics[].topics[].topics[].topics[].label
​G8.4.13
PMINTENSET, Performance Monitors Interrupt Enable Set
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.13
PMINTENSET, Performance Monitors Interrupt Enable Set
register

# topic.topics[].topics[].topics[].topics[].label
​G8.4.14
PMOVSR, Performance Monitors Overflow Flag Status
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.14
PMOVSR, Performance Monitors Overflow Flag Status
Register

# topic.topics[].topics[].topics[].topics[].label
​G8.4.15
PMOVSSET, Performance Monitors Overflow Flag Status Set
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.15
PMOVSSET, Performance Monitors Overflow Flag Status Set
register

# topic.topics[].topics[].topics[].topics[].label
​G8.4.16
PMSELR, Performance Monitors Event Counter Selection
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.16
PMSELR, Performance Monitors Event Counter Selection
Register

# topic.topics[].topics[].topics[].topics[].label
​G8.4.17
PMSWINC, Performance Monitors Software Increment
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.17
PMSWINC, Performance Monitors Software Increment
register

# topic.topics[].topics[].topics[].topics[].label
​G8.4.18
PMUSERENR, Performance Monitors User Enable Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.18
PMUSERENR, Performance Monitors User Enable Register

# topic.topics[].topics[].topics[].topics[].label
​G8.4.19
PMXEVCNTR, Performance Monitors Selected Event Count
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.19
PMXEVCNTR, Performance Monitors Selected Event Count
Register

# topic.topics[].topics[].topics[].topics[].label
​G8.4.20
PMXEVTYPER, Performance Monitors Selected Event Type
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.4.20
PMXEVTYPER, Performance Monitors Selected Event Type
Register

# topic.topics[].topics[].topics[].topics[].label
​G8.5.1
AMCFGR, Activity Monitors Configuration Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.5.1
AMCFGR, Activity Monitors Configuration Register

# topic.topics[].topics[].topics[].topics[].label
​G8.5.2
AMCGCR, Activity Monitors Counter Group Configuration
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.5.2
AMCGCR, Activity Monitors Counter Group Configuration
Register

# topic.topics[].topics[].topics[].topics[].label
​G8.5.3
AMCNTENCLR0, Activity Monitors Count Enable Clear Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.5.3
AMCNTENCLR0, Activity Monitors Count Enable Clear Register
0

# topic.topics[].topics[].topics[].topics[].label
​G8.5.4
AMCNTENCLR1, Activity Monitors Count Enable Clear Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.5.4
AMCNTENCLR1, Activity Monitors Count Enable Clear Register
1

# topic.topics[].topics[].topics[].topics[].label
​G8.5.5
AMCNTENSET0, Activity Monitors Count Enable Set Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.5.5
AMCNTENSET0, Activity Monitors Count Enable Set Register
0

# topic.topics[].topics[].topics[].topics[].label
​G8.5.6
AMCNTENSET1, Activity Monitors Count Enable Set Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.5.6
AMCNTENSET1, Activity Monitors Count Enable Set Register
1

# topic.topics[].topics[].topics[].topics[].label
​G8.5.7
AMCR, Activity Monitors Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.5.7
AMCR, Activity Monitors Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.5.8
AMEVCNTR0<n>, Activity Monitors Event Counter Registers 0,
n = 0 - 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.5.8
AMEVCNTR0<n>, Activity Monitors Event Counter Registers 0,
n = 0 - 3

# topic.topics[].topics[].topics[].topics[].label
​G8.5.9
AMEVCNTR1<n>, Activity Monitors Event Counter Registers 1,
n = 0 - 15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.5.9
AMEVCNTR1<n>, Activity Monitors Event Counter Registers 1,
n = 0 - 15

# topic.topics[].topics[].topics[].topics[].label
​G8.5.10
AMEVTYPER0<n>, Activity Monitors Event Type Registers 0, n
= 0 - 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.5.10
AMEVTYPER0<n>, Activity Monitors Event Type Registers 0, n
= 0 - 3

# topic.topics[].topics[].topics[].topics[].label
​G8.5.11
AMEVTYPER1<n>, Activity Monitors Event Type Registers 1, n
= 0 - 15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.5.11
AMEVTYPER1<n>, Activity Monitors Event Type Registers 1, n
= 0 - 15

# topic.topics[].topics[].topics[].topics[].label
​G8.5.12
AMUSERENR, Activity Monitors User Enable Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.5.12
AMUSERENR, Activity Monitors User Enable Register

# topic.topics[].topics[].topics[].topics[].label
​G8.6.1
DISR, Deferred Interrupt Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.1
DISR, Deferred Interrupt Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.6.2
ERRIDR, Error Record ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.2
ERRIDR, Error Record ID Register

# topic.topics[].topics[].topics[].topics[].label
​G8.6.3
ERRSELR, Error Record Select Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.3
ERRSELR, Error Record Select Register

# topic.topics[].topics[].topics[].topics[].label
​G8.6.4
ERXADDR, Selected Error Record Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.4
ERXADDR, Selected Error Record Address Register

# topic.topics[].topics[].topics[].topics[].label
​G8.6.5
ERXADDR2, Selected Error Record Address Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.5
ERXADDR2, Selected Error Record Address Register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.6.6
ERXCTLR, Selected Error Record Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.6
ERXCTLR, Selected Error Record Control Register

# topic.topics[].topics[].topics[].topics[].label
​G8.6.7
ERXCTLR2, Selected Error Record Control Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.7
ERXCTLR2, Selected Error Record Control Register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.6.8
ERXFR, Selected Error Record Feature Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.8
ERXFR, Selected Error Record Feature Register

# topic.topics[].topics[].topics[].topics[].label
​G8.6.9
ERXFR2, Selected Error Record Feature Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.9
ERXFR2, Selected Error Record Feature Register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.6.10
ERXMISC0, Selected Error Record Miscellaneous Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.10
ERXMISC0, Selected Error Record Miscellaneous Register 0

# topic.topics[].topics[].topics[].topics[].label
​G8.6.11
ERXMISC1, Selected Error Record Miscellaneous Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.11
ERXMISC1, Selected Error Record Miscellaneous Register 1

# topic.topics[].topics[].topics[].topics[].label
​G8.6.12
ERXMISC2, Selected Error Record Miscellaneous Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.12
ERXMISC2, Selected Error Record Miscellaneous Register 2

# topic.topics[].topics[].topics[].topics[].label
​G8.6.13
ERXMISC3, Selected Error Record Miscellaneous Register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.13
ERXMISC3, Selected Error Record Miscellaneous Register 3

# topic.topics[].topics[].topics[].topics[].label
​G8.6.14
ERXMISC4, Selected Error Record Miscellaneous Register 4

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.14
ERXMISC4, Selected Error Record Miscellaneous Register 4

# topic.topics[].topics[].topics[].topics[].label
​G8.6.15
ERXMISC5, Selected Error Record Miscellaneous Register 5

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.15
ERXMISC5, Selected Error Record Miscellaneous Register 5

# topic.topics[].topics[].topics[].topics[].label
​G8.6.16
ERXMISC6, Selected Error Record Miscellaneous Register 6

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.16
ERXMISC6, Selected Error Record Miscellaneous Register 6

# topic.topics[].topics[].topics[].topics[].label
​G8.6.17
ERXMISC7, Selected Error Record Miscellaneous Register 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.17
ERXMISC7, Selected Error Record Miscellaneous Register 7

# topic.topics[].topics[].topics[].topics[].label
​G8.6.18
ERXSTATUS, Selected Error Record Primary Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.18
ERXSTATUS, Selected Error Record Primary Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.6.19
VDFSR, Virtual SError Exception Syndrome Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.19
VDFSR, Virtual SError Exception Syndrome Register

# topic.topics[].topics[].topics[].topics[].label
​G8.6.20
VDISR, Virtual Deferred Interrupt Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.6.20
VDISR, Virtual Deferred Interrupt Status Register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.1
CNTFRQ, Counter-timer Frequency register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.1
CNTFRQ, Counter-timer Frequency register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.2
CNTHCTL, Counter-timer Hyp Control register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.2
CNTHCTL, Counter-timer Hyp Control register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.3
CNTHP_CTL, Counter-timer Hyp Physical Timer Control
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.3
CNTHP_CTL, Counter-timer Hyp Physical Timer Control
register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.4
CNTHP_CVAL, Counter-timer Hyp Physical CompareValue
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.4
CNTHP_CVAL, Counter-timer Hyp Physical CompareValue
register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.5
CNTHP_TVAL, Counter-timer Hyp Physical Timer TimerValue
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.5
CNTHP_TVAL, Counter-timer Hyp Physical Timer TimerValue
register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.6
CNTHPS_CTL, Counter-timer Secure Physical Timer Control Register
(EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.6
CNTHPS_CTL, Counter-timer Secure Physical Timer Control Register
(EL2)

# topic.topics[].topics[].topics[].topics[].label
​G8.7.7
CNTHPS_CVAL, Counter-timer Secure Physical Timer CompareValue
Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.7
CNTHPS_CVAL, Counter-timer Secure Physical Timer CompareValue
Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​G8.7.8
CNTHPS_TVAL, Counter-timer Secure Physical Timer TimerValue
Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.8
CNTHPS_TVAL, Counter-timer Secure Physical Timer TimerValue
Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​G8.7.9
CNTHV_CTL, Counter-timer Virtual Timer Control register
(EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.9
CNTHV_CTL, Counter-timer Virtual Timer Control register
(EL2)

# topic.topics[].topics[].topics[].topics[].label
​G8.7.10
CNTHV_CVAL, Counter-timer Virtual Timer CompareValue register
(EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.10
CNTHV_CVAL, Counter-timer Virtual Timer CompareValue register
(EL2)

# topic.topics[].topics[].topics[].topics[].label
​G8.7.11
CNTHV_TVAL, Counter-timer Virtual Timer TimerValue register
(EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.11
CNTHV_TVAL, Counter-timer Virtual Timer TimerValue register
(EL2)

# topic.topics[].topics[].topics[].topics[].label
​G8.7.12
CNTHVS_CTL, Counter-timer Secure Virtual Timer Control Register
(EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.12
CNTHVS_CTL, Counter-timer Secure Virtual Timer Control Register
(EL2)

# topic.topics[].topics[].topics[].topics[].label
​G8.7.13
CNTHVS_CVAL, Counter-timer Secure Virtual Timer CompareValue
Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.13
CNTHVS_CVAL, Counter-timer Secure Virtual Timer CompareValue
Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​G8.7.14
CNTHVS_TVAL, Counter-timer Secure Virtual Timer TimerValue
Register (EL2)

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.14
CNTHVS_TVAL, Counter-timer Secure Virtual Timer TimerValue
Register (EL2)

# topic.topics[].topics[].topics[].topics[].label
​G8.7.15
CNTKCTL, Counter-timer Kernel Control register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.15
CNTKCTL, Counter-timer Kernel Control register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.16
CNTP_CTL, Counter-timer Physical Timer Control register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.16
CNTP_CTL, Counter-timer Physical Timer Control register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.17
CNTP_CVAL, Counter-timer Physical Timer CompareValue
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.17
CNTP_CVAL, Counter-timer Physical Timer CompareValue
register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.18
CNTP_TVAL, Counter-timer Physical Timer TimerValue
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.18
CNTP_TVAL, Counter-timer Physical Timer TimerValue
register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.19
CNTPCT, Counter-timer Physical Count register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.19
CNTPCT, Counter-timer Physical Count register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.21
CNTV_CTL, Counter-timer Virtual Timer Control register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.21
CNTV_CTL, Counter-timer Virtual Timer Control register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.22
CNTV_CVAL, Counter-timer Virtual Timer CompareValue
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.22
CNTV_CVAL, Counter-timer Virtual Timer CompareValue
register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.23
CNTV_TVAL, Counter-timer Virtual Timer TimerValue
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.23
CNTV_TVAL, Counter-timer Virtual Timer TimerValue
register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.24
CNTVCT, Counter-timer Virtual Count register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.24
CNTVCT, Counter-timer Virtual Count register

# topic.topics[].topics[].topics[].topics[].label
​G8.7.26
CNTVOFF, Counter-timer Virtual Offset register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​G8.7.26
CNTVOFF, Counter-timer Virtual Offset register

# topic.topics[].topics[].anchors[].title
​Chapter
G8 AArch32 System Register Descriptions

# topic.topics[].anchors[].title
​Part G The AArch32 System Level
Architecture

# topic.topics[].topics[].topics[].topics[].label
​H1.1.1 Definition and constraints of a
debugger in the context of external debug

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H1.1.1 Definition and constraints of a
debugger in the context of external debug

# topic.topics[].topics[].topics[].topics[].label
​H2.2.1 Halting allowed and halting
prohibited

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.2.1 Halting allowed and halting
prohibited

# topic.topics[].topics[].topics[].topics[].label
​H2.2.3 Breakpoint and Watchpoint debug
events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.2.3 Breakpoint and Watchpoint debug
events

# topic.topics[].topics[].topics[].topics[].label
​H2.2.5 Debug state entry and debug event
prioritization

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.2.5 Debug state entry and debug event
prioritization

# topic.topics[].topics[].topics[].topics[].label
​H2.2.7 Summary of actions from debug
events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.2.7 Summary of actions from debug
events

# topic.topics[].topics[].topics[].topics[].label
​H2.2.8 Pseudocode description of Halting on
debug events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.2.8 Pseudocode description of Halting on
debug events

# topic.topics[].topics[].topics[].topics[].label
​H2.3.1 Entering Debug state from AArch32
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.3.1 Entering Debug state from AArch32
state

# topic.topics[].topics[].topics[].topics[].label
​H2.3.2 Effect of Debug state entry on DLR
and DSPSR

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.3.2 Effect of Debug state entry on DLR
and DSPSR

# topic.topics[].topics[].topics[].topics[].label
​H2.3.3 Effect of Debug state entry on
System registers, the Event register, and Exclusives monitors

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.3.3 Effect of Debug state entry on
System registers, the Event register, and Exclusives monitors

# topic.topics[].topics[].topics[].topics[].label
​H2.3.4 Effect of entering Debug state on
PSTATE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.3.4 Effect of entering Debug state on
PSTATE

# topic.topics[].topics[].topics[].topics[].label
​H2.3.5 Entering Debug state during loads
and stores

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.3.5 Entering Debug state during loads
and stores

# topic.topics[].topics[].topics[].topics[].label
​H2.3.6 Entering Debug state and Software
Step

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.3.6 Entering Debug state and Software
Step

# topic.topics[].topics[].topics[].topics[].label
​H2.3.7 Pseudocode description of entering
Debug state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.3.7 Pseudocode description of entering
Debug state

# topic.topics[].topics[].topics[].topics[].label
​H2.4.2 Executing instructions in Debug
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.4.2 Executing instructions in Debug
state

# topic.topics[].topics[].topics[].topics[].label
​H2.4.6 Debug state operations, DCPS, DRPS,
MRS, MSR

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.4.6 Debug state operations, DCPS, DRPS,
MRS, MSR

# topic.topics[].topics[].topics[].topics[].label
​H2.4.8 Accessing registers in Debug
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H2.4.8 Accessing registers in Debug
state

# topic.topics[].topics[].topics[].label
​H3.1 Introduction to Halting debug
events

# topic.topics[].topics[].topics[].anchors[].title
​H3.1 Introduction to Halting debug
events

# topic.topics[].topics[].topics[].topics[].label
​H3.2.1 Overview of a Halting Step debug
event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.2.1 Overview of a Halting Step debug
event

# topic.topics[].topics[].topics[].topics[].label
​H3.2.4 Detailed Halting Step state machine
behavior

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.2.4 Detailed Halting Step state machine
behavior

# topic.topics[].topics[].topics[].topics[].label
​H3.2.5 Synchronization and the Halting Step
state machine

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.2.5 Synchronization and the Halting Step
state machine

# topic.topics[].topics[].topics[].topics[].label
​H3.2.7 Disabling interrupts while
stepping

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.2.7 Disabling interrupts while
stepping

# topic.topics[].topics[].topics[].topics[].label
​H3.2.8 Syndrome information on Halting
Step

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.2.8 Syndrome information on Halting
Step

# topic.topics[].topics[].topics[].topics[].label
​H3.2.9 Pseudocode description of Halting
Step debug events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.2.9 Pseudocode description of Halting
Step debug events

# topic.topics[].topics[].topics[].topics[].label
​H3.3.1 HLT instructions as the first
instruction in a T32 IT block

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.3.1 HLT instructions as the first
instruction in a T32 IT block

# topic.topics[].topics[].topics[].topics[].label
​H3.4.1 Prioritization of Exception Catch
debug events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.4.1 Prioritization of Exception Catch
debug events

# topic.topics[].topics[].topics[].topics[].label
​H3.4.2 Generating Exception Catch debug
events when FEAT_Debugv8p2 is not implemented

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.4.2 Generating Exception Catch debug
events when FEAT_Debugv8p2 is not implemented

# topic.topics[].topics[].topics[].topics[].label
​H3.4.3 Generating Exception Catch debug
events when FEAT_Debugv8p2 is implemented and FEAT_Debugv8p8 is not
implemented

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.4.3 Generating Exception Catch debug
events when FEAT_Debugv8p2 is implemented and FEAT_Debugv8p8 is not
implemented

# topic.topics[].topics[].topics[].topics[].label
​H3.4.4 Generating Exception Catch debug
events when FEAT_Debugv8p8 is implemented

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.4.4 Generating Exception Catch debug
events when FEAT_Debugv8p8 is implemented

# topic.topics[].topics[].topics[].topics[].label
​H3.4.5 Controlling Exception Catch debug
events when FEAT_RME is implemented

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.4.5 Controlling Exception Catch debug
events when FEAT_RME is implemented

# topic.topics[].topics[].topics[].topics[].label
​H3.4.6 Controlling Exception Catch debug
events when FEAT_Debugv8p2 is implemented

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.4.6 Controlling Exception Catch debug
events when FEAT_Debugv8p2 is implemented

# topic.topics[].topics[].topics[].topics[].label
​H3.4.7 Controlling Exception Catch debug
events when FEAT_Debugv8p2 is not implemented

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.4.7 Controlling Exception Catch debug
events when FEAT_Debugv8p2 is not implemented

# topic.topics[].topics[].topics[].topics[].label
​H3.4.8 Examples of Exception Catch debug
events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.4.8 Examples of Exception Catch debug
events

# topic.topics[].topics[].topics[].topics[].label
​H3.4.9 Pseudocode description of Exception
Catch debug events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.4.9 Pseudocode description of Exception
Catch debug events

# topic.topics[].topics[].topics[].label
​H3.5 External Debug Request debug event

# topic.topics[].topics[].topics[].topics[].label
​H3.5.1 Synchronization and External Debug
Request debug events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.5.1 Synchronization and External Debug
Request debug events

# topic.topics[].topics[].topics[].topics[].label
​H3.5.3 Trace Buffer Unit external debug
request

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.5.3 Trace Buffer Unit external debug
request

# topic.topics[].topics[].topics[].topics[].label
​H3.5.4 PMU Overflow external debug
request

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.5.4 PMU Overflow external debug
request

# topic.topics[].topics[].topics[].topics[].label
​H3.5.5 Pseudocode description of External
Debug Request debug events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.5.5 Pseudocode description of External
Debug Request debug events

# topic.topics[].topics[].topics[].anchors[].title
​H3.5 External Debug Request debug event

# topic.topics[].topics[].topics[].topics[].label
​H3.6.1 Using the OS Unlock Catch debug
event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.6.1 Using the OS Unlock Catch debug
event

# topic.topics[].topics[].topics[].topics[].label
​H3.6.2 Pseudocode description of OS Unlock
Catch debug event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.6.2 Pseudocode description of OS Unlock
Catch debug event

# topic.topics[].topics[].topics[].topics[].label
​H3.7.1 Pseudocode description of Reset
Catch debug event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.7.1 Pseudocode description of Reset
Catch debug event

# topic.topics[].topics[].topics[].topics[].label
​H3.8.1 Pseudocode description of Software
Access debug event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H3.8.1 Pseudocode description of Software
Access debug event

# topic.topics[].topics[].topics[].label
​H3.9 Synchronization and Halting debug
events

# topic.topics[].topics[].topics[].anchors[].title
​H3.9 Synchronization and Halting debug
events

# topic.topics[].topics[].label
​Chapter H4 The Debug Communication Channel
and Instruction Transfer Register

# topic.topics[].topics[].topics[].topics[].label
​H4.3.3 Memory-mapped accesses to the DCC
and ITR

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H4.3.3 Memory-mapped accesses to the DCC
and ITR

# topic.topics[].topics[].topics[].label
​H4.4 Flow control of the DCC and ITR
registers

# topic.topics[].topics[].topics[].anchors[].title
​H4.4 Flow control of the DCC and ITR
registers

# topic.topics[].topics[].topics[].label
​H4.5 Synchronization of DCC and ITR
accesses

# topic.topics[].topics[].topics[].topics[].label
​H4.5.1 Summary of System register accesses
to the DCC

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H4.5.1 Summary of System register accesses
to the DCC

# topic.topics[].topics[].topics[].topics[].label
​H4.5.3 Synchronization of DCC interrupt
request signals

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H4.5.3 Synchronization of DCC interrupt
request signals

# topic.topics[].topics[].topics[].topics[].label
​H4.5.4 DCC and ITR access in Debug
state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H4.5.4 DCC and ITR access in Debug
state

# topic.topics[].topics[].topics[].anchors[].title
​H4.5 Synchronization of DCC and ITR
accesses

# topic.topics[].topics[].topics[].label
​H4.7 Pseudocode description of the
operation of the DCC and ITR registers

# topic.topics[].topics[].topics[].anchors[].title
​H4.7 Pseudocode description of the
operation of the DCC and ITR registers

# topic.topics[].topics[].anchors[].title
​Chapter H4 The Debug Communication Channel
and Instruction Transfer Register

# topic.topics[].topics[].label
​Chapter H5 The Embedded Cross-Trigger
Interface

# topic.topics[].topics[].topics[].topics[].label
​H5.1.1 Implementation with a CoreSight
CTI

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H5.1.1 Implementation with a CoreSight
CTI

# topic.topics[].topics[].topics[].label
​H5.3 Cross-triggers on a PE in an Arm
A-profile implementation

# topic.topics[].topics[].topics[].anchors[].title
​H5.3 Cross-triggers on a PE in an Arm
A-profile implementation

# topic.topics[].topics[].topics[].label
​H5.4 Description and allocation of CTI
triggers

# topic.topics[].topics[].topics[].topics[].label
​H5.4.4 Performance Monitors overflow
trigger event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H5.4.4 Performance Monitors overflow
trigger event

# topic.topics[].topics[].topics[].topics[].label
​H5.4.5 Statistical Profiling Extension
sample trigger event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H5.4.5 Statistical Profiling Extension
sample trigger event

# topic.topics[].topics[].topics[].topics[].label
​H5.4.6 Generic trace external input trigger
events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H5.4.6 Generic trace external input trigger
events

# topic.topics[].topics[].topics[].topics[].label
​H5.4.7 Generic trace external output
trigger events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H5.4.7 Generic trace external output
trigger events

# topic.topics[].topics[].topics[].topics[].label
​H5.4.8 Generic CTI interrupt trigger
event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H5.4.8 Generic CTI interrupt trigger
event

# topic.topics[].topics[].topics[].topics[].label
​H5.4.9 Trace buffer stopped trigger
event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H5.4.9 Trace buffer stopped trigger
event

# topic.topics[].topics[].topics[].topics[].label
​H5.4.10 Trace buffer management trigger
event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H5.4.10 Trace buffer management trigger
event

# topic.topics[].topics[].topics[].topics[].label
​H5.4.11 Trace buffer wrap trigger
event

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H5.4.11 Trace buffer wrap trigger
event

# topic.topics[].topics[].topics[].anchors[].title
​H5.4 Description and allocation of CTI
triggers

# topic.topics[].topics[].anchors[].title
​Chapter H5 The Embedded Cross-Trigger
Interface

# topic.topics[].topics[].label
​Chapter H6 Debug Reset and Powerdown
Support

# topic.topics[].topics[].topics[].topics[].label
​H6.4.1 Powerup request mechanism if
FEAT_DoPD is implemented

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H6.4.1 Powerup request mechanism if
FEAT_DoPD is implemented

# topic.topics[].topics[].topics[].topics[].label
​H6.4.2 Powerup request mechanism if
FEAT_DoPD is not implemented

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H6.4.2 Powerup request mechanism if
FEAT_DoPD is not implemented

# topic.topics[].topics[].topics[].label
​H6.6 Debug OS Save and Restore
sequences

# topic.topics[].topics[].topics[].topics[].label
​H6.6.1 EDPRSR.{DLK, SPD, PU} and the Core
power domain

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H6.6.1 EDPRSR.{DLK, SPD, PU} and the Core
power domain

# topic.topics[].topics[].topics[].topics[].label
​H6.6.2 EDPRSR.SPD when the Core domain is
in either retention or powerdown state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H6.6.2 EDPRSR.SPD when the Core domain is
in either retention or powerdown state

# topic.topics[].topics[].topics[].topics[].label
​H6.6.4 Debug registers to save over
powerdown

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H6.6.4 Debug registers to save over
powerdown

# topic.topics[].topics[].topics[].topics[].label
​H6.6.7 Debug behavior when the OS Lock is
locked

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H6.6.7 Debug behavior when the OS Lock is
locked

# topic.topics[].topics[].topics[].topics[].label
​H6.6.8 Debug behavior when the OS Lock is
unlocked

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H6.6.8 Debug behavior when the OS Lock is
unlocked

# topic.topics[].topics[].topics[].topics[].label
​H6.6.9 Debug behavior when the OS Double
Lock is locked

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H6.6.9 Debug behavior when the OS Double
Lock is locked

# topic.topics[].topics[].topics[].anchors[].title
​H6.6 Debug OS Save and Restore
sequences

# topic.topics[].topics[].topics[].topics[].label
​H6.7.1 External debug interface accesses to
registers in reset

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H6.7.1 External debug interface accesses to
registers in reset

# topic.topics[].topics[].anchors[].title
​Chapter H6 Debug Reset and Powerdown
Support

# topic.topics[].topics[].label
​Chapter H7 The PC Sample-based Profiling
Extension

# topic.topics[].topics[].topics[].label
​H7.1 About the PC Sample-based Profiling
Extension

# topic.topics[].topics[].topics[].topics[].label
​H7.1.1 Controlling the PC Sample-based
Profiling Extension

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H7.1.1 Controlling the PC Sample-based
Profiling Extension

# topic.topics[].topics[].topics[].topics[].label
​H7.1.2 Registers implemented by the PC
Sample-based Profiling Extension

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H7.1.2 Registers implemented by the PC
Sample-based Profiling Extension

# topic.topics[].topics[].topics[].topics[].label
​H7.1.3 Permitted behavior that might make
the PC Sample-based profiling registers UNKNOWN

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H7.1.3 Permitted behavior that might make
the PC Sample-based profiling registers UNKNOWN

# topic.topics[].topics[].topics[].topics[].label
​H7.1.4 Pseudocode description of PC
Sample-based Profiling

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H7.1.4 Pseudocode description of PC
Sample-based Profiling

# topic.topics[].topics[].topics[].anchors[].title
​H7.1 About the PC Sample-based Profiling
Extension

# topic.topics[].topics[].anchors[].title
​Chapter H7 The PC Sample-based Profiling
Extension

# topic.topics[].topics[].label
​Chapter H8 About the External Debug
Registers

# topic.topics[].topics[].topics[].label
​H8.1 Relationship between external debug
and System registers

# topic.topics[].topics[].topics[].anchors[].title
​H8.1 Relationship between external debug
and System registers

# topic.topics[].topics[].topics[].label
​H8.2 Endianness and supported access
sizes

# topic.topics[].topics[].topics[].anchors[].title
​H8.2 Endianness and supported access
sizes

# topic.topics[].topics[].topics[].label
​H8.3 Synchronization of changes to the
external debug registers

# topic.topics[].topics[].topics[].topics[].label
​H8.3.1 Synchronization and the
authentication interface

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H8.3.1 Synchronization and the
authentication interface

# topic.topics[].topics[].topics[].topics[].label
​H8.3.2 Examples of the synchronization of
changes to the external debug registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H8.3.2 Examples of the synchronization of
changes to the external debug registers

# topic.topics[].topics[].topics[].anchors[].title
​H8.3 Synchronization of changes to the
external debug registers

# topic.topics[].topics[].topics[].label
​H8.4 Memory-mapped accesses to the external
debug interface

# topic.topics[].topics[].topics[].topics[].label
​H8.4.1 Register access permissions for
memory-mapped accesses

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H8.4.1 Register access permissions for
memory-mapped accesses

# topic.topics[].topics[].topics[].topics[].label
​H8.4.2 Synchronization of memory-mapped
accesses to external debug registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H8.4.2 Synchronization of memory-mapped
accesses to external debug registers

# topic.topics[].topics[].topics[].anchors[].title
​H8.4 Memory-mapped accesses to the external
debug interface

# topic.topics[].topics[].topics[].label
​H8.5 External debug interface register
access permissions

# topic.topics[].topics[].topics[].topics[].label
​H8.5.1 External debug over powerdown and
locks

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H8.5.1 External debug over powerdown and
locks

# topic.topics[].topics[].topics[].topics[].label
​H8.5.3 Behavior of a not permitted
access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H8.5.3 Behavior of a not permitted
access

# topic.topics[].topics[].topics[].topics[].label
​H8.5.4 External debug interface register
access permissions summary

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H8.5.4 External debug interface register
access permissions summary

# topic.topics[].topics[].topics[].topics[].label
​H8.5.6 Reserved and unallocated
registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H8.5.6 Reserved and unallocated
registers

# topic.topics[].topics[].topics[].anchors[].title
​H8.5 External debug interface register
access permissions

# topic.topics[].topics[].topics[].label
​H8.6 External debug interface registers

# topic.topics[].topics[].topics[].topics[].label
​H8.6.1 Access permissions for the External
debug interface registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H8.6.1 Access permissions for the External
debug interface registers

# topic.topics[].topics[].topics[].anchors[].title
​H8.6 External debug interface registers

# topic.topics[].topics[].anchors[].title
​Chapter H8 About the External Debug
Registers

# topic.topics[].topics[].label
​Chapter H9
External Debug Register Descriptions

# topic.topics[].topics[].topics[].label
​H9.1 About the external debug
registers

# topic.topics[].topics[].topics[].anchors[].title
​H9.1 About the external debug
registers

# topic.topics[].topics[].topics[].topics[].label
​H9.2.2
DBGBCR<n>_EL1, Debug Breakpoint Control Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.2
DBGBCR<n>_EL1, Debug Breakpoint Control Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].label
​H9.2.3
DBGBVR<n>_EL1, Debug Breakpoint Value Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.3
DBGBVR<n>_EL1, Debug Breakpoint Value Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].label
​H9.2.4
DBGCLAIMCLR_EL1, Debug CLAIM Tag Clear Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.4
DBGCLAIMCLR_EL1, Debug CLAIM Tag Clear Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.5
DBGCLAIMSET_EL1, Debug CLAIM Tag Set Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.5
DBGCLAIMSET_EL1, Debug CLAIM Tag Set Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.6
DBGDTRRX_EL0, Debug Data Transfer Register, Receive

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.6
DBGDTRRX_EL0, Debug Data Transfer Register, Receive

# topic.topics[].topics[].topics[].topics[].label
​H9.2.7
DBGDTRTX_EL0, Debug Data Transfer Register, Transmit

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.7
DBGDTRTX_EL0, Debug Data Transfer Register, Transmit

# topic.topics[].topics[].topics[].topics[].label
​H9.2.8
DBGWCR<n>_EL1, Debug Watchpoint Control Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.8
DBGWCR<n>_EL1, Debug Watchpoint Control Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].label
​H9.2.9
DBGWVR<n>_EL1, Debug Watchpoint Value Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.9
DBGWVR<n>_EL1, Debug Watchpoint Value Registers, n = 0 -
63

# topic.topics[].topics[].topics[].topics[].label
​H9.2.10
EDAA32PFR, External Debug Auxiliary Processor Feature
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.10
EDAA32PFR, External Debug Auxiliary Processor Feature
Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.11 EDACR,
External Debug Auxiliary Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.11 EDACR,
External Debug Auxiliary Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.12
EDCIDR0, External Debug Component Identification Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.12
EDCIDR0, External Debug Component Identification Register
0

# topic.topics[].topics[].topics[].topics[].label
​H9.2.13
EDCIDR1, External Debug Component Identification Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.13
EDCIDR1, External Debug Component Identification Register
1

# topic.topics[].topics[].topics[].topics[].label
​H9.2.14
EDCIDR2, External Debug Component Identification Register
2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.14
EDCIDR2, External Debug Component Identification Register
2

# topic.topics[].topics[].topics[].topics[].label
​H9.2.15
EDCIDR3, External Debug Component Identification Register
3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.15
EDCIDR3, External Debug Component Identification Register
3

# topic.topics[].topics[].topics[].topics[].label
​H9.2.16
EDCIDSR, External Debug Context ID Sample Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.16
EDCIDSR, External Debug Context ID Sample Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.17
EDDEVAFF0, External Debug Device Affinity register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.17
EDDEVAFF0, External Debug Device Affinity register 0

# topic.topics[].topics[].topics[].topics[].label
​H9.2.18
EDDEVAFF1, External Debug Device Affinity register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.18
EDDEVAFF1, External Debug Device Affinity register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.2.19
EDDEVARCH, External Debug Device Architecture Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.19
EDDEVARCH, External Debug Device Architecture Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.20
EDDEVID, External Debug Device ID register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.20
EDDEVID, External Debug Device ID register 0

# topic.topics[].topics[].topics[].topics[].label
​H9.2.21
EDDEVID1, External Debug Device ID Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.21
EDDEVID1, External Debug Device ID Register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.2.22
EDDEVID2, External Debug Device ID register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.22
EDDEVID2, External Debug Device ID register 2

# topic.topics[].topics[].topics[].topics[].label
​H9.2.23
EDDEVTYPE, External Debug Device Type register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.23
EDDEVTYPE, External Debug Device Type register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.24 EDDFR,
External Debug Feature Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.24 EDDFR,
External Debug Feature Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.25
EDDFR1, External Debug Feature Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.25
EDDFR1, External Debug Feature Register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.2.26
EDDFR2, External Debug Feature Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.26
EDDFR2, External Debug Feature Register 2

# topic.topics[].topics[].topics[].topics[].label
​H9.2.27
EDECCR, External Debug Exception Catch Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.27
EDECCR, External Debug Exception Catch Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.28 EDECR,
External Debug Execution Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.28 EDECR,
External Debug Execution Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.29 EDESR,
External Debug Event Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.29 EDESR,
External Debug Event Status Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.30 EDHSR,
External Debug Halting Syndrome Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.30 EDHSR,
External Debug Halting Syndrome Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.31
EDITCTRL, External Debug Integration mode Control
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.31
EDITCTRL, External Debug Integration mode Control
register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.32 EDITR,
External Debug Instruction Transfer Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.32 EDITR,
External Debug Instruction Transfer Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.33 EDLAR,
External Debug Lock Access Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.33 EDLAR,
External Debug Lock Access Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.34 EDLSR,
External Debug Lock Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.34 EDLSR,
External Debug Lock Status Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.35
EDPCSR, External Debug Program Counter Sample Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.35
EDPCSR, External Debug Program Counter Sample Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.36 EDPFR,
External Debug Processor Feature Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.36 EDPFR,
External Debug Processor Feature Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.37
EDPIDR0, External Debug Peripheral Identification Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.37
EDPIDR0, External Debug Peripheral Identification Register
0

# topic.topics[].topics[].topics[].topics[].label
​H9.2.38
EDPIDR1, External Debug Peripheral Identification Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.38
EDPIDR1, External Debug Peripheral Identification Register
1

# topic.topics[].topics[].topics[].topics[].label
​H9.2.39
EDPIDR2, External Debug Peripheral Identification Register
2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.39
EDPIDR2, External Debug Peripheral Identification Register
2

# topic.topics[].topics[].topics[].topics[].label
​H9.2.40
EDPIDR3, External Debug Peripheral Identification Register
3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.40
EDPIDR3, External Debug Peripheral Identification Register
3

# topic.topics[].topics[].topics[].topics[].label
​H9.2.41
EDPIDR4, External Debug Peripheral Identification Register
4

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.41
EDPIDR4, External Debug Peripheral Identification Register
4

# topic.topics[].topics[].topics[].topics[].label
​H9.2.42
EDPRCR, External Debug Power/Reset Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.42
EDPRCR, External Debug Power/Reset Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.43
EDPRSR, External Debug Processor Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.43
EDPRSR, External Debug Processor Status Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.44 EDRCR,
External Debug Reserve Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.44 EDRCR,
External Debug Reserve Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.45 EDSCR,
External Debug Status and Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.45 EDSCR,
External Debug Status and Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.46
EDSCR2, External Debug Status and Control Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.46
EDSCR2, External Debug Status and Control Register 2

# topic.topics[].topics[].topics[].topics[].label
​H9.2.47
EDVIDSR, External Debug Virtual Context Sample Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.47
EDVIDSR, External Debug Virtual Context Sample Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.48 EDWAR,
External Debug Watchpoint Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.48 EDWAR,
External Debug Watchpoint Address Register

# topic.topics[].topics[].topics[].topics[].label
​H9.2.50
OSLAR_EL1, OS Lock Access Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.2.50
OSLAR_EL1, OS Lock Access Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.1
TRCACATR<n>, Trace Address Comparator Access Type Register
<n>, n = 0 - 15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.1
TRCACATR<n>, Trace Address Comparator Access Type Register
<n>, n = 0 - 15

# topic.topics[].topics[].topics[].topics[].label
​H9.3.2
TRCACVR<n>, Trace Address Comparator Value Register
<n>, n = 0 - 15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.2
TRCACVR<n>, Trace Address Comparator Value Register
<n>, n = 0 - 15

# topic.topics[].topics[].topics[].topics[].label
​H9.3.3
TRCAUTHSTATUS, Trace Authentication Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.3
TRCAUTHSTATUS, Trace Authentication Status Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.4
TRCAUXCTLR, Trace Auxiliary Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.4
TRCAUXCTLR, Trace Auxiliary Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.5
TRCBBCTLR, Trace Branch Broadcast Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.5
TRCBBCTLR, Trace Branch Broadcast Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.6
TRCCCCTLR, Trace Cycle Count Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.6
TRCCCCTLR, Trace Cycle Count Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.7
TRCCIDCCTLR0, Trace Context Identifier Comparator Control
Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.7
TRCCIDCCTLR0, Trace Context Identifier Comparator Control
Register 0

# topic.topics[].topics[].topics[].topics[].label
​H9.3.8
TRCCIDCCTLR1, Trace Context Identifier Comparator Control
Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.8
TRCCIDCCTLR1, Trace Context Identifier Comparator Control
Register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.3.9
TRCCIDCVR<n>, Trace Context Identifier Comparator Value
Registers <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.9
TRCCIDCVR<n>, Trace Context Identifier Comparator Value
Registers <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].label
​H9.3.10
TRCCIDR0, Trace Component Identification Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.10
TRCCIDR0, Trace Component Identification Register 0

# topic.topics[].topics[].topics[].topics[].label
​H9.3.11
TRCCIDR1, Trace Component Identification Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.11
TRCCIDR1, Trace Component Identification Register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.3.12
TRCCIDR2, Trace Component Identification Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.12
TRCCIDR2, Trace Component Identification Register 2

# topic.topics[].topics[].topics[].topics[].label
​H9.3.13
TRCCIDR3, Trace Component Identification Register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.13
TRCCIDR3, Trace Component Identification Register 3

# topic.topics[].topics[].topics[].topics[].label
​H9.3.14
TRCCLAIMCLR, Trace Claim Tag Clear Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.14
TRCCLAIMCLR, Trace Claim Tag Clear Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.15
TRCCLAIMSET, Trace Claim Tag Set Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.15
TRCCLAIMSET, Trace Claim Tag Set Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.16
TRCCNTCTLR<n>, Trace Counter Control Register <n>, n
= 0 - 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.16
TRCCNTCTLR<n>, Trace Counter Control Register <n>, n
= 0 - 3

# topic.topics[].topics[].topics[].topics[].label
​H9.3.17
TRCCNTRLDVR<n>, Trace Counter Reload Value Register
<n>, n = 0 - 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.17
TRCCNTRLDVR<n>, Trace Counter Reload Value Register
<n>, n = 0 - 3

# topic.topics[].topics[].topics[].topics[].label
​H9.3.18
TRCCNTVR<n>, Trace Counter Value Register <n>, n = 0
- 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.18
TRCCNTVR<n>, Trace Counter Value Register <n>, n = 0
- 3

# topic.topics[].topics[].topics[].topics[].label
​H9.3.20
TRCDEVAFF, Trace Device Affinity Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.20
TRCDEVAFF, Trace Device Affinity Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.21
TRCDEVARCH, Trace Device Architecture Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.21
TRCDEVARCH, Trace Device Architecture Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.22
TRCDEVID, Trace Device Configuration Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.22
TRCDEVID, Trace Device Configuration Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.23
TRCDEVID1, Trace Device Configuration Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.23
TRCDEVID1, Trace Device Configuration Register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.3.24
TRCDEVID2, Trace Device Configuration Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.24
TRCDEVID2, Trace Device Configuration Register 2

# topic.topics[].topics[].topics[].topics[].label
​H9.3.25
TRCDEVTYPE, Trace Device Type Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.25
TRCDEVTYPE, Trace Device Type Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.26
TRCEVENTCTL0R, Trace Event Control 0 Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.26
TRCEVENTCTL0R, Trace Event Control 0 Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.27
TRCEVENTCTL1R, Trace Event Control 1 Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.27
TRCEVENTCTL1R, Trace Event Control 1 Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.28
TRCEXTINSELR<n>, Trace External Input Select Register
<n>, n = 0 - 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.28
TRCEXTINSELR<n>, Trace External Input Select Register
<n>, n = 0 - 3

# topic.topics[].topics[].topics[].topics[].label
​H9.3.43
TRCIMSPEC0, Trace IMP DEF Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.43
TRCIMSPEC0, Trace IMP DEF Register 0

# topic.topics[].topics[].topics[].topics[].label
​H9.3.44
TRCIMSPEC<n>, Trace IMP DEF Register <n>, n = 1 -
7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.44
TRCIMSPEC<n>, Trace IMP DEF Register <n>, n = 1 -
7

# topic.topics[].topics[].topics[].topics[].label
​H9.3.45
TRCITCTRL, Trace Integration Mode Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.45
TRCITCTRL, Trace Integration Mode Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.46
TRCITEEDCR, Instrumentation Trace Extension External Debug
Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.46
TRCITEEDCR, Instrumentation Trace Extension External Debug
Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.47
TRCLAR, Trace Lock Access Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.47
TRCLAR, Trace Lock Access Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.48
TRCLSR, Trace Lock Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.48
TRCLSR, Trace Lock Status Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.49
TRCOSLSR, Trace OS Lock Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.49
TRCOSLSR, Trace OS Lock Status Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.50
TRCPDCR, Trace PowerDown Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.50
TRCPDCR, Trace PowerDown Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.51
TRCPDSR, Trace PowerDown Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.51
TRCPDSR, Trace PowerDown Status Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.52
TRCPIDR0, Trace Peripheral Identification Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.52
TRCPIDR0, Trace Peripheral Identification Register 0

# topic.topics[].topics[].topics[].topics[].label
​H9.3.53
TRCPIDR1, Trace Peripheral Identification Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.53
TRCPIDR1, Trace Peripheral Identification Register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.3.54
TRCPIDR2, Trace Peripheral Identification Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.54
TRCPIDR2, Trace Peripheral Identification Register 2

# topic.topics[].topics[].topics[].topics[].label
​H9.3.55
TRCPIDR3, Trace Peripheral Identification Register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.55
TRCPIDR3, Trace Peripheral Identification Register 3

# topic.topics[].topics[].topics[].topics[].label
​H9.3.56
TRCPIDR4, Trace Peripheral Identification Register 4

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.56
TRCPIDR4, Trace Peripheral Identification Register 4

# topic.topics[].topics[].topics[].topics[].label
​H9.3.57
TRCPIDR5, Trace Peripheral Identification Register 5

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.57
TRCPIDR5, Trace Peripheral Identification Register 5

# topic.topics[].topics[].topics[].topics[].label
​H9.3.58
TRCPIDR6, Trace Peripheral Identification Register 6

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.58
TRCPIDR6, Trace Peripheral Identification Register 6

# topic.topics[].topics[].topics[].topics[].label
​H9.3.59
TRCPIDR7, Trace Peripheral Identification Register 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.59
TRCPIDR7, Trace Peripheral Identification Register 7

# topic.topics[].topics[].topics[].topics[].label
​H9.3.60
TRCPRGCTLR, Trace Programming Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.60
TRCPRGCTLR, Trace Programming Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.61
TRCQCTLR, Trace Q Element Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.61
TRCQCTLR, Trace Q Element Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.62
TRCRSCTLR<n>, Trace Resource Selection Control Register
<n>, n = 2 - 31

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.62
TRCRSCTLR<n>, Trace Resource Selection Control Register
<n>, n = 2 - 31

# topic.topics[].topics[].topics[].topics[].label
​H9.3.63
TRCRSR, Trace Resources Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.63
TRCRSR, Trace Resources Status Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.64
TRCSEQEVR<n>, Trace Sequencer State Transition Control
Register <n>, n = 0 - 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.64
TRCSEQEVR<n>, Trace Sequencer State Transition Control
Register <n>, n = 0 - 2

# topic.topics[].topics[].topics[].topics[].label
​H9.3.65
TRCSEQRSTEVR, Trace Sequencer Reset Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.65
TRCSEQRSTEVR, Trace Sequencer Reset Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.66
TRCSEQSTR, Trace Sequencer State Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.66
TRCSEQSTR, Trace Sequencer State Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.67
TRCSSCCR<n>, Trace Single-shot Comparator Control Register
<n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.67
TRCSSCCR<n>, Trace Single-shot Comparator Control Register
<n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].label
​H9.3.68
TRCSSCSR<n>, Trace Single-shot Comparator Control Status
Register <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.68
TRCSSCSR<n>, Trace Single-shot Comparator Control Status
Register <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].label
​H9.3.69
TRCSSPCICR<n>, Trace Single-shot Processing Element
Comparator Input Control Register <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.69
TRCSSPCICR<n>, Trace Single-shot Processing Element
Comparator Input Control Register <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].label
​H9.3.70
TRCSTALLCTLR, Trace Stall Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.70
TRCSTALLCTLR, Trace Stall Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.71
TRCSTATR, Trace Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.71
TRCSTATR, Trace Status Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.72
TRCSYNCPR, Trace Synchronization Period Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.72
TRCSYNCPR, Trace Synchronization Period Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.74
TRCTSCTLR, Trace Timestamp Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.74
TRCTSCTLR, Trace Timestamp Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.75
TRCVICTLR, Trace ViewInst Main Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.75
TRCVICTLR, Trace ViewInst Main Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.76
TRCVIIECTLR, Trace ViewInst Include/Exclude Control
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.76
TRCVIIECTLR, Trace ViewInst Include/Exclude Control
Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.77
TRCVIPCSSCTLR, Trace ViewInst Start/Stop PE Comparator Control
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.77
TRCVIPCSSCTLR, Trace ViewInst Start/Stop PE Comparator Control
Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.78
TRCVISSCTLR, Trace ViewInst Start/Stop Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.78
TRCVISSCTLR, Trace ViewInst Start/Stop Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.3.79
TRCVMIDCCTLR0, Trace Virtual Context Identifier Comparator
Control Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.79
TRCVMIDCCTLR0, Trace Virtual Context Identifier Comparator
Control Register 0

# topic.topics[].topics[].topics[].topics[].label
​H9.3.80
TRCVMIDCCTLR1, Trace Virtual Context Identifier Comparator
Control Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.80
TRCVMIDCCTLR1, Trace Virtual Context Identifier Comparator
Control Register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.3.81
TRCVMIDCVR<n>, Trace Virtual Context Identifier Comparator
Value Register <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.3.81
TRCVMIDCVR<n>, Trace Virtual Context Identifier Comparator
Value Register <n>, n = 0 - 7

# topic.topics[].topics[].topics[].topics[].label
​H9.4.2
TRBBASER_EL1, Trace Buffer Base Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.2
TRBBASER_EL1, Trace Buffer Base Address Register

# topic.topics[].topics[].topics[].topics[].label
​H9.4.3
TRBCIDR0, Component Identification Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.3
TRBCIDR0, Component Identification Register 0

# topic.topics[].topics[].topics[].topics[].label
​H9.4.4
TRBCIDR1, Component Identification Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.4
TRBCIDR1, Component Identification Register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.4.5
TRBCIDR2, Component Identification Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.5
TRBCIDR2, Component Identification Register 2

# topic.topics[].topics[].topics[].topics[].label
​H9.4.6
TRBCIDR3, Component Identification Register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.6
TRBCIDR3, Component Identification Register 3

# topic.topics[].topics[].topics[].topics[].label
​H9.4.7 TRBCR,
Trace Buffer Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.7 TRBCR,
Trace Buffer Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.4.8
TRBDEVAFF, Device Affinity Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.8
TRBDEVAFF, Device Affinity Register

# topic.topics[].topics[].topics[].topics[].label
​H9.4.9
TRBDEVARCH, Trace Buffer Device Architecture Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.9
TRBDEVARCH, Trace Buffer Device Architecture Register

# topic.topics[].topics[].topics[].topics[].label
​H9.4.10
TRBDEVID, Device Configuration Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.10
TRBDEVID, Device Configuration Register

# topic.topics[].topics[].topics[].topics[].label
​H9.4.11
TRBDEVID1, Device Configuration Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.11
TRBDEVID1, Device Configuration Register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.4.12
TRBDEVID2, Device Configuration Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.12
TRBDEVID2, Device Configuration Register 2

# topic.topics[].topics[].topics[].topics[].label
​H9.4.13
TRBDEVTYPE, Device Type Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.13
TRBDEVTYPE, Device Type Register

# topic.topics[].topics[].topics[].topics[].label
​H9.4.14
TRBIDR_EL1, Trace Buffer ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.14
TRBIDR_EL1, Trace Buffer ID Register

# topic.topics[].topics[].topics[].topics[].label
​H9.4.15
TRBITCTRL, Integration Mode Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.15
TRBITCTRL, Integration Mode Control Register

# topic.topics[].topics[].topics[].topics[].label
​H9.4.17
TRBLIMITR_EL1, Trace Buffer Limit Address Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.17
TRBLIMITR_EL1, Trace Buffer Limit Address Register

# topic.topics[].topics[].topics[].topics[].label
​H9.4.19
TRBMAR_EL1, Trace Buffer Memory Attribute Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.19
TRBMAR_EL1, Trace Buffer Memory Attribute Register

# topic.topics[].topics[].topics[].topics[].label
​H9.4.20
TRBMPAM_EL1, Trace Buffer MPAM Configuration Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.20
TRBMPAM_EL1, Trace Buffer MPAM Configuration Register

# topic.topics[].topics[].topics[].topics[].label
​H9.4.21
TRBPIDR0, Peripheral Identification Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.21
TRBPIDR0, Peripheral Identification Register 0

# topic.topics[].topics[].topics[].topics[].label
​H9.4.22
TRBPIDR1, Peripheral Identification Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.22
TRBPIDR1, Peripheral Identification Register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.4.23
TRBPIDR2, Peripheral Identification Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.23
TRBPIDR2, Peripheral Identification Register 2

# topic.topics[].topics[].topics[].topics[].label
​H9.4.24
TRBPIDR3, Peripheral Identification Register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.24
TRBPIDR3, Peripheral Identification Register 3

# topic.topics[].topics[].topics[].topics[].label
​H9.4.25
TRBPIDR4, Peripheral Identification Register 4

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.25
TRBPIDR4, Peripheral Identification Register 4

# topic.topics[].topics[].topics[].topics[].label
​H9.4.26
TRBPIDR5, Peripheral Identification Register 5

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.26
TRBPIDR5, Peripheral Identification Register 5

# topic.topics[].topics[].topics[].topics[].label
​H9.4.27
TRBPIDR6, Peripheral Identification Register 6

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.27
TRBPIDR6, Peripheral Identification Register 6

# topic.topics[].topics[].topics[].topics[].label
​H9.4.28
TRBPIDR7, Peripheral Identification Register 7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.28
TRBPIDR7, Peripheral Identification Register 7

# topic.topics[].topics[].topics[].topics[].label
​H9.4.29
TRBPTR_EL1, Trace Buffer Write Pointer Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.29
TRBPTR_EL1, Trace Buffer Write Pointer Register

# topic.topics[].topics[].topics[].topics[].label
​H9.4.30
TRBSR_EL1, Trace Buffer Status/syndrome Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.30
TRBSR_EL1, Trace Buffer Status/syndrome Register

# topic.topics[].topics[].topics[].topics[].label
​H9.4.31
TRBTRG_EL1, Trace Buffer Trigger Counter Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.4.31
TRBTRG_EL1, Trace Buffer Trigger Counter Register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.1
ASICCTL, CTI External Multiplexer Control register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.1
ASICCTL, CTI External Multiplexer Control register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.2
CTIAPPCLEAR, CTI Application Trigger Clear register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.2
CTIAPPCLEAR, CTI Application Trigger Clear register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.3
CTIAPPPULSE, CTI Application Pulse register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.3
CTIAPPPULSE, CTI Application Pulse register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.4
CTIAPPSET, CTI Application Trigger Set register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.4
CTIAPPSET, CTI Application Trigger Set register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.5
CTIAUTHSTATUS, CTI Authentication Status register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.5
CTIAUTHSTATUS, CTI Authentication Status register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.6
CTICHINSTATUS, CTI Channel In Status register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.6
CTICHINSTATUS, CTI Channel In Status register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.7
CTICHOUTSTATUS, CTI Channel Out Status register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.7
CTICHOUTSTATUS, CTI Channel Out Status register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.8
CTICIDR0, CTI Component Identification Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.8
CTICIDR0, CTI Component Identification Register 0

# topic.topics[].topics[].topics[].topics[].label
​H9.5.9
CTICIDR1, CTI Component Identification Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.9
CTICIDR1, CTI Component Identification Register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.5.10
CTICIDR2, CTI Component Identification Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.10
CTICIDR2, CTI Component Identification Register 2

# topic.topics[].topics[].topics[].topics[].label
​H9.5.11
CTICIDR3, CTI Component Identification Register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.11
CTICIDR3, CTI Component Identification Register 3

# topic.topics[].topics[].topics[].topics[].label
​H9.5.12
CTICLAIMCLR, CTI CLAIM Tag Clear register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.12
CTICLAIMCLR, CTI CLAIM Tag Clear register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.13
CTICLAIMSET, CTI CLAIM Tag Set register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.13
CTICLAIMSET, CTI CLAIM Tag Set register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.14
CTICONTROL, CTI Control register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.14
CTICONTROL, CTI Control register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.15
CTIDEVAFF0, CTI Device Affinity register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.15
CTIDEVAFF0, CTI Device Affinity register 0

# topic.topics[].topics[].topics[].topics[].label
​H9.5.16
CTIDEVAFF1, CTI Device Affinity register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.16
CTIDEVAFF1, CTI Device Affinity register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.5.17
CTIDEVARCH, CTI Device Architecture register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.17
CTIDEVARCH, CTI Device Architecture register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.18
CTIDEVCTL, CTI Device Control register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.18
CTIDEVCTL, CTI Device Control register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.19
CTIDEVID, CTI Device ID register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.19
CTIDEVID, CTI Device ID register 0

# topic.topics[].topics[].topics[].topics[].label
​H9.5.20
CTIDEVID1, CTI Device ID register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.20
CTIDEVID1, CTI Device ID register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.5.21
CTIDEVID2, CTI Device ID register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.21
CTIDEVID2, CTI Device ID register 2

# topic.topics[].topics[].topics[].topics[].label
​H9.5.22
CTIDEVTYPE, CTI Device Type register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.22
CTIDEVTYPE, CTI Device Type register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.23
CTIGATE, CTI Channel Gate Enable register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.23
CTIGATE, CTI Channel Gate Enable register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.24
CTIINEN<n>, CTI Input Trigger to Output Channel Enable
registers, n = 0 - 31

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.24
CTIINEN<n>, CTI Input Trigger to Output Channel Enable
registers, n = 0 - 31

# topic.topics[].topics[].topics[].topics[].label
​H9.5.25
CTIINTACK, CTI Output Trigger Acknowledge register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.25
CTIINTACK, CTI Output Trigger Acknowledge register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.26
CTIITCTRL, CTI Integration mode Control register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.26
CTIITCTRL, CTI Integration mode Control register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.27
CTILAR, CTI Lock Access Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.27
CTILAR, CTI Lock Access Register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.28
CTILSR, CTI Lock Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.28
CTILSR, CTI Lock Status Register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.29
CTIOUTEN<n>, CTI Input Channel to Output Trigger Enable
registers, n = 0 - 31

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.29
CTIOUTEN<n>, CTI Input Channel to Output Trigger Enable
registers, n = 0 - 31

# topic.topics[].topics[].topics[].topics[].label
​H9.5.30
CTIPIDR0, CTI Peripheral Identification Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.30
CTIPIDR0, CTI Peripheral Identification Register 0

# topic.topics[].topics[].topics[].topics[].label
​H9.5.31
CTIPIDR1, CTI Peripheral Identification Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.31
CTIPIDR1, CTI Peripheral Identification Register 1

# topic.topics[].topics[].topics[].topics[].label
​H9.5.32
CTIPIDR2, CTI Peripheral Identification Register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.32
CTIPIDR2, CTI Peripheral Identification Register 2

# topic.topics[].topics[].topics[].topics[].label
​H9.5.33
CTIPIDR3, CTI Peripheral Identification Register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.33
CTIPIDR3, CTI Peripheral Identification Register 3

# topic.topics[].topics[].topics[].topics[].label
​H9.5.34
CTIPIDR4, CTI Peripheral Identification Register 4

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.34
CTIPIDR4, CTI Peripheral Identification Register 4

# topic.topics[].topics[].topics[].topics[].label
​H9.5.35
CTITRIGINSTATUS, CTI Trigger In Status register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.35
CTITRIGINSTATUS, CTI Trigger In Status register

# topic.topics[].topics[].topics[].topics[].label
​H9.5.36
CTITRIGOUTSTATUS, CTI Trigger Out Status register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​H9.5.36
CTITRIGOUTSTATUS, CTI Trigger Out Status register

# topic.topics[].topics[].anchors[].title
​Chapter H9
External Debug Register Descriptions

# topic.topics[].label
​Part I Memory-mapped Components of the Arm
Architecture

# topic.topics[].topics[].label
​Chapter I1 Requirements for Memory-mapped
Components

# topic.topics[].topics[].topics[].label
​I1.2 Synchronization of memory-mapped
registers

# topic.topics[].topics[].topics[].anchors[].title
​I1.2 Synchronization of memory-mapped
registers

# topic.topics[].topics[].topics[].label
​I1.3 Access requirements for reserved and
unallocated registers

# topic.topics[].topics[].topics[].anchors[].title
​I1.3 Access requirements for reserved and
unallocated registers

# topic.topics[].topics[].anchors[].title
​Chapter I1 Requirements for Memory-mapped
Components

# topic.topics[].topics[].label
​Chapter I2 System Level Implementation of
the Generic Timer

# topic.topics[].topics[].topics[].label
​I2.1 About the Generic Timer
specification

# topic.topics[].topics[].topics[].topics[].label
​I2.1.1 Registers in the system level
implementation of the Generic Timer

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I2.1.1 Registers in the system level
implementation of the Generic Timer

# topic.topics[].topics[].topics[].topics[].label
​I2.1.2 The system level components of the
Generic Timer

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I2.1.2 The system level components of the
Generic Timer

# topic.topics[].topics[].topics[].anchors[].title
​I2.1 About the Generic Timer
specification

# topic.topics[].topics[].topics[].topics[].label
​I2.2.1 Control of counter resolution and
increment

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I2.2.1 Control of counter resolution and
increment

# topic.topics[].topics[].topics[].topics[].label
​I2.2.3 Counter module control and status
register summary

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I2.2.3 Counter module control and status
register summary

# topic.topics[].topics[].topics[].topics[].label
​I2.3.2 The CNTBaseN and CNTEL0BaseN
frames

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I2.3.2 The CNTBaseN and CNTEL0BaseN
frames

# topic.topics[].topics[].anchors[].title
​Chapter I2 System Level Implementation of
the Generic Timer

# topic.topics[].topics[].label
​Chapter I3 Recommended External Interface
to the Performance Monitors

# topic.topics[].topics[].topics[].label
​I3.1 About the external interface to the
Performance Monitors registers

# topic.topics[].topics[].topics[].topics[].label
​I3.1.1 Endianness and supported access
sizes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I3.1.1 Endianness and supported access
sizes

# topic.topics[].topics[].topics[].topics[].label
​I3.1.2 Differences in the external views of
the Performance Monitors registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I3.1.2 Differences in the external views of
the Performance Monitors registers

# topic.topics[].topics[].topics[].topics[].label
​I3.1.3 Synchronization of changes to the
memory-mapped views

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I3.1.3 Synchronization of changes to the
memory-mapped views

# topic.topics[].topics[].topics[].topics[].label
​I3.1.4 Access permissions for external
views of the Performance Monitors

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I3.1.4 Access permissions for external
views of the Performance Monitors

# topic.topics[].topics[].topics[].anchors[].title
​I3.1 About the external interface to the
Performance Monitors registers

# topic.topics[].topics[].anchors[].title
​Chapter I3 Recommended External Interface
to the Performance Monitors

# topic.topics[].topics[].label
​Chapter I4 Recommended External Interface
to the Activity Monitors

# topic.topics[].topics[].topics[].label
​I4.1 About the external interface to the
Activity Monitors Extension registers

# topic.topics[].topics[].topics[].topics[].label
​I4.1.1 Endianness and supported access
sizes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I4.1.1 Endianness and supported access
sizes

# topic.topics[].topics[].topics[].topics[].label
​I4.1.2 Differences in the external views of
the Activity Monitors Extension registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I4.1.2 Differences in the external views of
the Activity Monitors Extension registers

# topic.topics[].topics[].topics[].topics[].label
​I4.1.3 Access during reset and power
transitions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I4.1.3 Access during reset and power
transitions

# topic.topics[].topics[].topics[].anchors[].title
​I4.1 About the external interface to the
Activity Monitors Extension registers

# topic.topics[].topics[].anchors[].title
​Chapter I4 Recommended External Interface
to the Activity Monitors

# topic.topics[].topics[].label
​Chapter I5
External System Control Register Descriptions

# topic.topics[].topics[].topics[].label
​I5.1 About the external system control
register descriptions

# topic.topics[].topics[].topics[].anchors[].title
​I5.1 About the external system control
register descriptions

# topic.topics[].topics[].topics[].label
​I5.2 External Performance Monitors
registers summary

# topic.topics[].topics[].topics[].topics[].label
​I5.2.1 Performance Monitors external
register views

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.2.1 Performance Monitors external
register views

# topic.topics[].topics[].topics[].anchors[].title
​I5.2 External Performance Monitors
registers summary

# topic.topics[].topics[].topics[].label
​I5.3
Performance Monitors external register descriptions

# topic.topics[].topics[].topics[].topics[].label
​I5.3.2
PMCCFILTR_EL0, Performance Monitors Cycle Counter Filter
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.2
PMCCFILTR_EL0, Performance Monitors Cycle Counter Filter
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.3
PMCCIDSR, CONTEXTIDR_ELx Sample Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.3
PMCCIDSR, CONTEXTIDR_ELx Sample Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.4
PMCCNTR_EL0, Performance Monitors Cycle Counter

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.4
PMCCNTR_EL0, Performance Monitors Cycle Counter

# topic.topics[].topics[].topics[].topics[].label
​I5.3.5
PMCCNTSVR_EL1, Performance Monitors Cycle Count Saved Value
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.5
PMCCNTSVR_EL1, Performance Monitors Cycle Count Saved Value
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.6
PMCEID0, Performance Monitors Common Event Identification
register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.6
PMCEID0, Performance Monitors Common Event Identification
register 0

# topic.topics[].topics[].topics[].topics[].label
​I5.3.7
PMCEID1, Performance Monitors Common Event Identification
register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.7
PMCEID1, Performance Monitors Common Event Identification
register 1

# topic.topics[].topics[].topics[].topics[].label
​I5.3.8
PMCEID2, Performance Monitors Common Event Identification
register 2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.8
PMCEID2, Performance Monitors Common Event Identification
register 2

# topic.topics[].topics[].topics[].topics[].label
​I5.3.9
PMCEID3, Performance Monitors Common Event Identification
register 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.9
PMCEID3, Performance Monitors Common Event Identification
register 3

# topic.topics[].topics[].topics[].topics[].label
​I5.3.10
PMCGCR0, Counter Group Configuration Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.10
PMCGCR0, Counter Group Configuration Register 0

# topic.topics[].topics[].topics[].topics[].label
​I5.3.11
PMCFGR, Performance Monitors Configuration Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.11
PMCFGR, Performance Monitors Configuration Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.14
PMCIDR0, Performance Monitors Component Identification Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.14
PMCIDR0, Performance Monitors Component Identification Register
0

# topic.topics[].topics[].topics[].topics[].label
​I5.3.15
PMCIDR1, Performance Monitors Component Identification Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.15
PMCIDR1, Performance Monitors Component Identification Register
1

# topic.topics[].topics[].topics[].topics[].label
​I5.3.16
PMCIDR2, Performance Monitors Component Identification Register
2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.16
PMCIDR2, Performance Monitors Component Identification Register
2

# topic.topics[].topics[].topics[].topics[].label
​I5.3.17
PMCIDR3, Performance Monitors Component Identification Register
3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.17
PMCIDR3, Performance Monitors Component Identification Register
3

# topic.topics[].topics[].topics[].topics[].label
​I5.3.18
PMCNTEN, Performance Monitors Count Enable register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.18
PMCNTEN, Performance Monitors Count Enable register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.19
PMCNTENCLR_EL0, Performance Monitors Count Enable Clear
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.19
PMCNTENCLR_EL0, Performance Monitors Count Enable Clear
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.20
PMCNTENSET_EL0, Performance Monitors Count Enable Set
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.20
PMCNTENSET_EL0, Performance Monitors Count Enable Set
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.21
PMCR_EL0, Performance Monitors Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.21
PMCR_EL0, Performance Monitors Control Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.22
PMDEVAFF0, Performance Monitors Device Affinity register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.22
PMDEVAFF0, Performance Monitors Device Affinity register
0

# topic.topics[].topics[].topics[].topics[].label
​I5.3.23
PMDEVAFF1, Performance Monitors Device Affinity register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.23
PMDEVAFF1, Performance Monitors Device Affinity register
1

# topic.topics[].topics[].topics[].topics[].label
​I5.3.24
PMDEVAFF, Performance Monitors Device Affinity register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.24
PMDEVAFF, Performance Monitors Device Affinity register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.25
PMDEVARCH, Performance Monitors Device Architecture
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.25
PMDEVARCH, Performance Monitors Device Architecture
register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.26
PMDEVID, Performance Monitors Device ID register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.26
PMDEVID, Performance Monitors Device ID register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.27
PMDEVTYPE, Performance Monitors Device Type register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.27
PMDEVTYPE, Performance Monitors Device Type register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.28
PMEVCNTR<n>_EL0, Performance Monitors Event Count
Registers, n = 0 - 30

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.28
PMEVCNTR<n>_EL0, Performance Monitors Event Count
Registers, n = 0 - 30

# topic.topics[].topics[].topics[].topics[].label
​I5.3.29
PMEVCNTSVR<n>_EL1, Performance Monitors Event Count Saved
Value Registers, n = 0 - 30

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.29
PMEVCNTSVR<n>_EL1, Performance Monitors Event Count Saved
Value Registers, n = 0 - 30

# topic.topics[].topics[].topics[].topics[].label
​I5.3.30
PMEVTYPER<n>_EL0, Performance Monitors Event Type
Registers, n = 0 - 30

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.30
PMEVTYPER<n>_EL0, Performance Monitors Event Type
Registers, n = 0 - 30

# topic.topics[].topics[].topics[].topics[].label
​I5.3.31
PMEVFILT2R<n>, Performance Monitors Event Filter Registers,
n = 0 - 63

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.31
PMEVFILT2R<n>, Performance Monitors Event Filter Registers,
n = 0 - 63

# topic.topics[].topics[].topics[].topics[].label
​I5.3.32
PMICFILTR_EL0, Performance Monitors Instruction Counter Filter
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.32
PMICFILTR_EL0, Performance Monitors Instruction Counter Filter
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.33
PMICNTR_EL0, Performance Monitors Instruction Counter
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.33
PMICNTR_EL0, Performance Monitors Instruction Counter
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.34
PMICNTSVR_EL1, Performance Monitors Instruction Count Saved Value
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.34
PMICNTSVR_EL1, Performance Monitors Instruction Count Saved Value
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.36
PMINTENCLR_EL1, Performance Monitors Interrupt Enable Clear
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.36
PMINTENCLR_EL1, Performance Monitors Interrupt Enable Clear
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.37
PMINTEN, Performance Monitors Interrupt Enable register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.37
PMINTEN, Performance Monitors Interrupt Enable register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.38
PMINTENSET_EL1, Performance Monitors Interrupt Enable Set
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.38
PMINTENSET_EL1, Performance Monitors Interrupt Enable Set
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.39
PMITCTRL, Performance Monitors Integration mode Control
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.39
PMITCTRL, Performance Monitors Integration mode Control
register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.40 PMLAR,
Performance Monitors Lock Access Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.40 PMLAR,
Performance Monitors Lock Access Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.41 PMLSR,
Performance Monitors Lock Status Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.41 PMLSR,
Performance Monitors Lock Status Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.42 PMMIR,
Performance Monitors Machine Identification Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.42 PMMIR,
Performance Monitors Machine Identification Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.43
PMOVSCLR_EL0, Performance Monitors Overflow Flag Status Clear
register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.43
PMOVSCLR_EL0, Performance Monitors Overflow Flag Status Clear
register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.44 PMOVS,
Performance Monitors Overflow Flag Status register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.44 PMOVS,
Performance Monitors Overflow Flag Status register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.45
PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.45
PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.46
PMPCSCTL, PC Sample-based Profiling Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.46
PMPCSCTL, PC Sample-based Profiling Control Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.47 PMCCR,
PMU Configuration Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.47 PMCCR,
PMU Configuration Control Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.48
PMPCSR, Program Counter Sample Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.48
PMPCSR, Program Counter Sample Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.49
PMPIDR0, Performance Monitors Peripheral Identification Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.49
PMPIDR0, Performance Monitors Peripheral Identification Register
0

# topic.topics[].topics[].topics[].topics[].label
​I5.3.50
PMPIDR1, Performance Monitors Peripheral Identification Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.50
PMPIDR1, Performance Monitors Peripheral Identification Register
1

# topic.topics[].topics[].topics[].topics[].label
​I5.3.51
PMPIDR2, Performance Monitors Peripheral Identification Register
2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.51
PMPIDR2, Performance Monitors Peripheral Identification Register
2

# topic.topics[].topics[].topics[].topics[].label
​I5.3.52
PMPIDR3, Performance Monitors Peripheral Identification Register
3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.52
PMPIDR3, Performance Monitors Peripheral Identification Register
3

# topic.topics[].topics[].topics[].topics[].label
​I5.3.53
PMPIDR4, Performance Monitors Peripheral Identification Register
4

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.53
PMPIDR4, Performance Monitors Peripheral Identification Register
4

# topic.topics[].topics[].topics[].topics[].label
​I5.3.54
PMSSCR_EL1, Performance Monitors Snapshot Status and Capture
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.54
PMSSCR_EL1, Performance Monitors Snapshot Status and Capture
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.55
PMSWINC_EL0, Performance Monitors Software Increment
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.55
PMSWINC_EL0, Performance Monitors Software Increment
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.57
PMVCIDSR, CONTEXTIDR_EL1 and VMID Sample Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.57
PMVCIDSR, CONTEXTIDR_EL1 and VMID Sample Register

# topic.topics[].topics[].topics[].topics[].label
​I5.3.58
PMZR_EL0, Performance Monitors Zero with Mask

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.3.58
PMZR_EL0, Performance Monitors Zero with Mask

# topic.topics[].topics[].topics[].anchors[].title
​I5.3
Performance Monitors external register descriptions

# topic.topics[].topics[].topics[].label
​I5.4 External Activity Monitors Extension
registers summary

# topic.topics[].topics[].topics[].topics[].label
​I5.4.1 Activity Monitors external register
views

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.4.1 Activity Monitors external register
views

# topic.topics[].topics[].topics[].anchors[].title
​I5.4 External Activity Monitors Extension
registers summary

# topic.topics[].topics[].topics[].label
​I5.5
Activity Monitors external register descriptions

# topic.topics[].topics[].topics[].topics[].label
​I5.5.1
AMCFGR, Activity Monitors Configuration Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.1
AMCFGR, Activity Monitors Configuration Register

# topic.topics[].topics[].topics[].topics[].label
​I5.5.2
AMCGCR, Activity Monitors Counter Group Configuration
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.2
AMCGCR, Activity Monitors Counter Group Configuration
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.5.3
AMCIDR0, Activity Monitors Component Identification Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.3
AMCIDR0, Activity Monitors Component Identification Register
0

# topic.topics[].topics[].topics[].topics[].label
​I5.5.4
AMCIDR1, Activity Monitors Component Identification Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.4
AMCIDR1, Activity Monitors Component Identification Register
1

# topic.topics[].topics[].topics[].topics[].label
​I5.5.5
AMCIDR2, Activity Monitors Component Identification Register
2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.5
AMCIDR2, Activity Monitors Component Identification Register
2

# topic.topics[].topics[].topics[].topics[].label
​I5.5.6
AMCIDR3, Activity Monitors Component Identification Register
3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.6
AMCIDR3, Activity Monitors Component Identification Register
3

# topic.topics[].topics[].topics[].topics[].label
​I5.5.7
AMCNTEN, Activity Monitors Count Set and Clear Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.7
AMCNTEN, Activity Monitors Count Set and Clear Register

# topic.topics[].topics[].topics[].topics[].label
​I5.5.8
AMCNTENCLR, Activity Monitors Count Enable Clear
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.8
AMCNTENCLR, Activity Monitors Count Enable Clear
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.5.9
AMCNTENCLR0, Activity Monitors Count Enable Clear Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.9
AMCNTENCLR0, Activity Monitors Count Enable Clear Register
0

# topic.topics[].topics[].topics[].topics[].label
​I5.5.10
AMCNTENCLR1, Activity Monitors Count Enable Clear Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.10
AMCNTENCLR1, Activity Monitors Count Enable Clear Register
1

# topic.topics[].topics[].topics[].topics[].label
​I5.5.11
AMCNTENSET, Activity Monitors Count Enable Set Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.11
AMCNTENSET, Activity Monitors Count Enable Set Register

# topic.topics[].topics[].topics[].topics[].label
​I5.5.12
AMCNTENSET0, Activity Monitors Count Enable Set Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.12
AMCNTENSET0, Activity Monitors Count Enable Set Register
0

# topic.topics[].topics[].topics[].topics[].label
​I5.5.13
AMCNTENSET1, Activity Monitors Count Enable Set Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.13
AMCNTENSET1, Activity Monitors Count Enable Set Register
1

# topic.topics[].topics[].topics[].topics[].label
​I5.5.14 AMCR,
Activity Monitors Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.14 AMCR,
Activity Monitors Control Register

# topic.topics[].topics[].topics[].topics[].label
​I5.5.15
AMDEVAFF, Activity Monitors Device Affinity Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.15
AMDEVAFF, Activity Monitors Device Affinity Register

# topic.topics[].topics[].topics[].topics[].label
​I5.5.16
AMDEVAFF0, Activity Monitors Device Affinity Register 0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.16
AMDEVAFF0, Activity Monitors Device Affinity Register 0

# topic.topics[].topics[].topics[].topics[].label
​I5.5.17
AMDEVAFF1, Activity Monitors Device Affinity Register 1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.17
AMDEVAFF1, Activity Monitors Device Affinity Register 1

# topic.topics[].topics[].topics[].topics[].label
​I5.5.18
AMDEVARCH, Activity Monitors Device Architecture
Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.18
AMDEVARCH, Activity Monitors Device Architecture
Register

# topic.topics[].topics[].topics[].topics[].label
​I5.5.19
AMDEVTYPE, Activity Monitors Device Type Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.19
AMDEVTYPE, Activity Monitors Device Type Register

# topic.topics[].topics[].topics[].topics[].label
​I5.5.20
AMEVCNTR0<n>, Activity Monitors Event Counter Registers 0,
n = 0 - 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.20
AMEVCNTR0<n>, Activity Monitors Event Counter Registers 0,
n = 0 - 3

# topic.topics[].topics[].topics[].topics[].label
​I5.5.21
AMEVCNTR1<n>, Activity Monitors Event Counter Registers 1,
n = 0 - 15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.21
AMEVCNTR1<n>, Activity Monitors Event Counter Registers 1,
n = 0 - 15

# topic.topics[].topics[].topics[].topics[].label
​I5.5.22
AMEVTYPER0<n>, Activity Monitors Event Type Registers 0, n
= 0 - 3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.22
AMEVTYPER0<n>, Activity Monitors Event Type Registers 0, n
= 0 - 3

# topic.topics[].topics[].topics[].topics[].label
​I5.5.23
AMEVTYPER1<n>, Activity Monitors Event Type Registers 1, n
= 0 - 15

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.23
AMEVTYPER1<n>, Activity Monitors Event Type Registers 1, n
= 0 - 15

# topic.topics[].topics[].topics[].topics[].label
​I5.5.25
AMPIDR0, Activity Monitors Peripheral Identification Register
0

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.25
AMPIDR0, Activity Monitors Peripheral Identification Register
0

# topic.topics[].topics[].topics[].topics[].label
​I5.5.26
AMPIDR1, Activity Monitors Peripheral Identification Register
1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.26
AMPIDR1, Activity Monitors Peripheral Identification Register
1

# topic.topics[].topics[].topics[].topics[].label
​I5.5.27
AMPIDR2, Activity Monitors Peripheral Identification Register
2

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.27
AMPIDR2, Activity Monitors Peripheral Identification Register
2

# topic.topics[].topics[].topics[].topics[].label
​I5.5.28
AMPIDR3, Activity Monitors Peripheral Identification Register
3

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.28
AMPIDR3, Activity Monitors Peripheral Identification Register
3

# topic.topics[].topics[].topics[].topics[].label
​I5.5.29
AMPIDR4, Activity Monitors Peripheral Identification Register
4

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.29
AMPIDR4, Activity Monitors Peripheral Identification Register
4

# topic.topics[].topics[].topics[].topics[].label
​I5.5.30
AMROOTCR, Activity Monitors Root Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.30
AMROOTCR, Activity Monitors Root Control Register

# topic.topics[].topics[].topics[].topics[].label
​I5.5.31 AMSCR,
Activity Monitors Secure Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.5.31 AMSCR,
Activity Monitors Secure Control Register

# topic.topics[].topics[].topics[].anchors[].title
​I5.5
Activity Monitors external register descriptions

# topic.topics[].topics[].topics[].label
​I5.6 Generic Timer memory-mapped registers
overview

# topic.topics[].topics[].topics[].anchors[].title
​I5.6 Generic Timer memory-mapped registers
overview

# topic.topics[].topics[].topics[].label
​I5.7
Generic Timer memory-mapped register descriptions

# topic.topics[].topics[].topics[].topics[].label
​I5.7.1
CNTACR<n>, Counter-timer Access Control Registers, n = 0 -
7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.1
CNTACR<n>, Counter-timer Access Control Registers, n = 0 -
7

# topic.topics[].topics[].topics[].topics[].label
​I5.7.3 CNTCV,
Counter Count Value register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.3 CNTCV,
Counter Count Value register

# topic.topics[].topics[].topics[].topics[].label
​I5.7.4
CNTEL0ACR, Counter-timer EL0 Access Control Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.4
CNTEL0ACR, Counter-timer EL0 Access Control Register

# topic.topics[].topics[].topics[].topics[].label
​I5.7.8 CNTID,
Counter Identification Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.8 CNTID,
Counter Identification Register

# topic.topics[].topics[].topics[].topics[].label
​I5.7.9
CNTNSAR, Counter-timer Non-secure Access Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.9
CNTNSAR, Counter-timer Non-secure Access Register

# topic.topics[].topics[].topics[].topics[].label
​I5.7.10
CNTP_CTL, Counter-timer Physical Timer Control

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.10
CNTP_CTL, Counter-timer Physical Timer Control

# topic.topics[].topics[].topics[].topics[].label
​I5.7.12
CNTP_TVAL, Counter-timer Physical Timer TimerValue

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.12
CNTP_TVAL, Counter-timer Physical Timer TimerValue

# topic.topics[].topics[].topics[].topics[].label
​I5.7.13
CNTPCT, Counter-timer Physical Count

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.13
CNTPCT, Counter-timer Physical Count

# topic.topics[].topics[].topics[].topics[].label
​I5.7.16
CNTTIDR, Counter-timer Timer ID Register

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.16
CNTTIDR, Counter-timer Timer ID Register

# topic.topics[].topics[].topics[].topics[].label
​I5.7.17
CNTV_CTL, Counter-timer Virtual Timer Control

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.17
CNTV_CTL, Counter-timer Virtual Timer Control

# topic.topics[].topics[].topics[].topics[].label
​I5.7.18
CNTV_CVAL, Counter-timer Virtual Timer CompareValue

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.18
CNTV_CVAL, Counter-timer Virtual Timer CompareValue

# topic.topics[].topics[].topics[].topics[].label
​I5.7.19
CNTV_TVAL, Counter-timer Virtual Timer TimerValue

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.19
CNTV_TVAL, Counter-timer Virtual Timer TimerValue

# topic.topics[].topics[].topics[].topics[].label
​I5.7.20
CNTVCT, Counter-timer Virtual Count

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.20
CNTVCT, Counter-timer Virtual Count

# topic.topics[].topics[].topics[].topics[].label
​I5.7.21
CNTVOFF, Counter-timer Virtual Offset

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.21
CNTVOFF, Counter-timer Virtual Offset

# topic.topics[].topics[].topics[].topics[].label
​I5.7.22
CNTVOFF<n>, Counter-timer Virtual Offsets, n = 0 -
7

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.22
CNTVOFF<n>, Counter-timer Virtual Offsets, n = 0 -
7

# topic.topics[].topics[].topics[].topics[].label
​I5.7.23
CounterID<n>, Counter ID registers, n = 0 - 11

# topic.topics[].topics[].topics[].topics[].anchors[].title
​I5.7.23
CounterID<n>, Counter ID registers, n = 0 - 11

# topic.topics[].topics[].topics[].anchors[].title
​I5.7
Generic Timer memory-mapped register descriptions

# topic.topics[].topics[].anchors[].title
​Chapter I5
External System Control Register Descriptions

# topic.topics[].anchors[].title
​Part I Memory-mapped Components of the Arm
Architecture

# topic.topics[].topics[].label
​Chapter J1
A-profile Architecture Pseudocode

# topic.topics[].topics[].anchors[].title
​Chapter J1
A-profile Architecture Pseudocode

# topic.topics[].topics[].label
​Appendix K1 Architectural Constraints on
UNPREDICTABLE Behaviors

# topic.topics[].topics[].topics[].topics[].label
​K1.1.1 Overview of the constraints on Armv7
UNPREDICTABLE behaviors

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.1 Overview of the constraints on Armv7
UNPREDICTABLE behaviors

# topic.topics[].topics[].topics[].topics[].label
​K1.1.6 Loads and Stores to unaligned
locations

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.6 Loads and Stores to unaligned
locations

# topic.topics[].topics[].topics[].topics[].label
​K1.1.7 CONSTRAINED UNPREDICTABLE behavior
associated with IT instructions and PSTATE.IT

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.7 CONSTRAINED UNPREDICTABLE behavior
associated with IT instructions and PSTATE.IT

# topic.topics[].topics[].topics[].topics[].label
​K1.1.8 Unallocated System register access
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.8 Unallocated System register access
instructions

# topic.topics[].topics[].topics[].topics[].label
​K1.1.9 SBZ or SBO fields T32 and A32 in
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.9 SBZ or SBO fields T32 and A32 in
instructions

# topic.topics[].topics[].topics[].topics[].label
​K1.1.10 UNPREDICTABLE cases in immediate
constants in T32 data-processing instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.10 UNPREDICTABLE cases in immediate
constants in T32 data-processing instructions

# topic.topics[].topics[].topics[].topics[].label
​K1.1.11 UNPREDICTABLE cases in immediate
constants in Advanced SIMD instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.11 UNPREDICTABLE cases in immediate
constants in Advanced SIMD instructions

# topic.topics[].topics[].topics[].topics[].label
​K1.1.12 CONSTRAINED UNPREDICTABLE behaviors
due to caching of System register control or data values

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.12 CONSTRAINED UNPREDICTABLE behaviors
due to caching of System register control or data values

# topic.topics[].topics[].topics[].topics[].label
​K1.1.13 CONSTRAINED UNPREDICTABLE behavior
due to inadequate context synchronization

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.13 CONSTRAINED UNPREDICTABLE behavior
due to inadequate context synchronization

# topic.topics[].topics[].topics[].topics[].label
​K1.1.14 Unallocated values with register
fields of CP15 registers and Translation Table entries

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.14 Unallocated values with register
fields of CP15 registers and Translation Table entries

# topic.topics[].topics[].topics[].topics[].label
​K1.1.15 Translation Table Base Address
alignment

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.15 Translation Table Base Address
alignment

# topic.topics[].topics[].topics[].topics[].label
​K1.1.16 Handling of System register control
fields for Advanced SIMD and floating-point operation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.16 Handling of System register control
fields for Advanced SIMD and floating-point operation

# topic.topics[].topics[].topics[].topics[].label
​K1.1.17 Mapping of non-idempotent memory
locations using the Normal memory type

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.17 Mapping of non-idempotent memory
locations using the Normal memory type

# topic.topics[].topics[].topics[].topics[].label
​K1.1.18 The Performance Monitors
Extension

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.18 The Performance Monitors
Extension

# topic.topics[].topics[].topics[].topics[].label
​K1.1.19 The Activity Monitors
Extension

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.19 The Activity Monitors
Extension

# topic.topics[].topics[].topics[].topics[].label
​K1.1.20 Syndrome register handling for
CONSTRAINED UNPREDICTABLE instructions treated as UNDEFINED

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.20 Syndrome register handling for
CONSTRAINED UNPREDICTABLE instructions treated as UNDEFINED

# topic.topics[].topics[].topics[].topics[].label
​K1.1.22 Instruction fetches from Device
memory

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.22 Instruction fetches from Device
memory

# topic.topics[].topics[].topics[].topics[].label
​K1.1.23 Multi-access instructions that load
the PC from Device memory

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.23 Multi-access instructions that load
the PC from Device memory

# topic.topics[].topics[].topics[].topics[].label
​K1.1.24 Programming CSSELR.Level for a
cache level that is not implemented

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.24 Programming CSSELR.Level for a
cache level that is not implemented

# topic.topics[].topics[].topics[].topics[].label
​K1.1.25 Crossing a page boundary with
different memory types or Shareability attributes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.25 Crossing a page boundary with
different memory types or Shareability attributes

# topic.topics[].topics[].topics[].topics[].label
​K1.1.26 Crossing a 4KB boundary with a
Device access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.26 Crossing a 4KB boundary with a
Device access

# topic.topics[].topics[].topics[].topics[].label
​K1.1.28 CONSTRAINED UNPREDICTABLE behavior
for T32 and A32 instruction encodings

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.28 CONSTRAINED UNPREDICTABLE behavior
for T32 and A32 instruction encodings

# topic.topics[].topics[].topics[].topics[].label
​K1.1.29 Out of range values of the
Set/Way/Index fields in cache maintenance instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.29 Out of range values of the
Set/Way/Index fields in cache maintenance instructions

# topic.topics[].topics[].topics[].topics[].label
​K1.1.30 CONSTRAINED UNPREDICTABLE behavior
for T32 and A32 System instructions in the base instruction set

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.30 CONSTRAINED UNPREDICTABLE behavior
for T32 and A32 System instructions in the base instruction set

# topic.topics[].topics[].topics[].topics[].label
​K1.1.31 CONSTRAINED UNPREDICTABLE behavior,
T32 and A32 Advanced SIMD and floating-point instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.31 CONSTRAINED UNPREDICTABLE behavior,
T32 and A32 Advanced SIMD and floating-point instructions

# topic.topics[].topics[].topics[].topics[].label
​K1.1.32 CONSTRAINED UNPREDICTABLE behaviors
associated with the VTCR

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.32 CONSTRAINED UNPREDICTABLE behaviors
associated with the VTCR

# topic.topics[].topics[].topics[].topics[].label
​K1.1.33 CONSTRAINED UNPREDICTABLE behavior
of EL2 features

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.33 CONSTRAINED UNPREDICTABLE behavior
of EL2 features

# topic.topics[].topics[].topics[].topics[].label
​K1.1.34 Reserved values in System and
memory-mapped registers and translation table entries

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.34 Reserved values in System and
memory-mapped registers and translation table entries

# topic.topics[].topics[].topics[].topics[].label
​K1.1.35 CONSTRAINED UNPREDICTABLE behavior
in Debug state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.1.35 CONSTRAINED UNPREDICTABLE behavior
in Debug state

# topic.topics[].topics[].topics[].topics[].label
​K1.2.1 Overview of the constraints on
AArch64 UNPREDICTABLE behaviors

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.1 Overview of the constraints on
AArch64 UNPREDICTABLE behaviors

# topic.topics[].topics[].topics[].topics[].label
​K1.2.2 SBZ or SBO fields in A64
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.2 SBZ or SBO fields in A64
instructions

# topic.topics[].topics[].topics[].topics[].label
​K1.2.3 CONSTRAINED UNPREDICTABLE behaviors
due to caching of control or data values

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.3 CONSTRAINED UNPREDICTABLE behaviors
due to caching of control or data values

# topic.topics[].topics[].topics[].topics[].label
​K1.2.4 CONSTRAINED UNPREDICTABLE behavior
due to inadequate context synchronization

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.4 CONSTRAINED UNPREDICTABLE behavior
due to inadequate context synchronization

# topic.topics[].topics[].topics[].topics[].label
​K1.2.5 Translation table base address
alignment

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.5 Translation table base address
alignment

# topic.topics[].topics[].topics[].topics[].label
​K1.2.6 The Performance Monitors
Extension

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.6 The Performance Monitors
Extension

# topic.topics[].topics[].topics[].topics[].label
​K1.2.8 Syndrome register handling for
CONSTRAINED UNPREDICTABLE instructions treated as UNDEFINED

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.8 Syndrome register handling for
CONSTRAINED UNPREDICTABLE instructions treated as UNDEFINED

# topic.topics[].topics[].topics[].topics[].label
​K1.2.10 Mapping of non-idempotent memory
locations using the Normal memory type

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.10 Mapping of non-idempotent memory
locations using the Normal memory type

# topic.topics[].topics[].topics[].topics[].label
​K1.2.11 Instruction fetches from Device
memory

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.11 Instruction fetches from Device
memory

# topic.topics[].topics[].topics[].topics[].label
​K1.2.12 Programming the CSSELR_EL1.{Level,
InD, TnD} for a cache level that is not implemented

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.12 Programming the CSSELR_EL1.{Level,
InD, TnD} for a cache level that is not implemented

# topic.topics[].topics[].topics[].topics[].label
​K1.2.13 Crossing a page boundary with
different memory types or Shareability attributes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.13 Crossing a page boundary with
different memory types or Shareability attributes

# topic.topics[].topics[].topics[].topics[].label
​K1.2.14 Crossing a peripheral boundary with
a Device access

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.14 Crossing a peripheral boundary with
a Device access

# topic.topics[].topics[].topics[].topics[].label
​K1.2.15 CONSTRAINED UNPREDICTABLE behaviors
with SVE memory accesses

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.15 CONSTRAINED UNPREDICTABLE behaviors
with SVE memory accesses

# topic.topics[].topics[].topics[].topics[].label
​K1.2.17 CONSTRAINED UNPREDICTABLE behavior
for A64 instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.17 CONSTRAINED UNPREDICTABLE behavior
for A64 instructions

# topic.topics[].topics[].topics[].topics[].label
​K1.2.18 Out of range values of the
Set/Way/Index fields in cache maintenance instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.18 Out of range values of the
Set/Way/Index fields in cache maintenance instructions

# topic.topics[].topics[].topics[].topics[].label
​K1.2.19 Reserved values in System and
memory-mapped registers and translation table entries

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.19 Reserved values in System and
memory-mapped registers and translation table entries

# topic.topics[].topics[].topics[].topics[].label
​K1.2.20 CONSTRAINED UNPREDICTABLE behavior
in Debug state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K1.2.20 CONSTRAINED UNPREDICTABLE behavior
in Debug state

# topic.topics[].topics[].anchors[].title
​Appendix K1 Architectural Constraints on
UNPREDICTABLE Behaviors

# topic.topics[].topics[].label
​Appendix K2 Recommendations for Reporting
Memory Attributes on an Interconnect

# topic.topics[].topics[].topics[].label
​K2.1 Arm recommendations for reporting
memory attributes on an interconnect

# topic.topics[].topics[].topics[].topics[].label
​K2.1.1 Effect of microarchitectural choices
on memory attributes

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K2.1.1 Effect of microarchitectural choices
on memory attributes

# topic.topics[].topics[].topics[].anchors[].title
​K2.1 Arm recommendations for reporting
memory attributes on an interconnect

# topic.topics[].topics[].anchors[].title
​Appendix K2 Recommendations for Reporting
Memory Attributes on an Interconnect

# topic.topics[].topics[].label
​Appendix K3 ETE Recommended
Configurations

# topic.topics[].topics[].anchors[].title
​Appendix K3 ETE Recommended
Configurations

# topic.topics[].topics[].label
​Appendix K5 Recommended External Debug
Interface

# topic.topics[].topics[].topics[].label
​K5.1 About the recommended external debug
interface

# topic.topics[].topics[].topics[].topics[].label
​K5.1.2
Non-secure, Secure, Realm, and Root views of the debug
registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K5.1.2
Non-secure, Secure, Realm, and Root views of the debug
registers

# topic.topics[].topics[].topics[].anchors[].title
​K5.1 About the recommended external debug
interface

# topic.topics[].topics[].topics[].label
​K5.4 Management registers and CoreSight
compliance

# topic.topics[].topics[].topics[].topics[].label
​K5.4.1 CoreSight interface register
map

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K5.4.1 CoreSight interface register
map

# topic.topics[].topics[].topics[].topics[].label
​K5.4.2 Management register access
permissions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K5.4.2 Management register access
permissions

# topic.topics[].topics[].topics[].topics[].label
​K5.4.4 About the Peripheral identification
scheme

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K5.4.4 About the Peripheral identification
scheme

# topic.topics[].topics[].topics[].topics[].label
​K5.4.5 About the Component Identification
scheme

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K5.4.5 About the Component Identification
scheme

# topic.topics[].topics[].topics[].anchors[].title
​K5.4 Management registers and CoreSight
compliance

# topic.topics[].topics[].anchors[].title
​Appendix K5 Recommended External Debug
Interface

# topic.topics[].topics[].label
​Appendix K6 Additional Information for
Implementations of the Generic Timer

# topic.topics[].topics[].topics[].label
​K6.1 Providing a complete set of features
in a system level implementation

# topic.topics[].topics[].topics[].anchors[].title
​K6.1 Providing a complete set of features
in a system level implementation

# topic.topics[].topics[].topics[].label
​K6.2 Gray count scheme for timer
distribution scheme

# topic.topics[].topics[].topics[].anchors[].title
​K6.2 Gray count scheme for timer
distribution scheme

# topic.topics[].topics[].anchors[].title
​Appendix K6 Additional Information for
Implementations of the Generic Timer

# topic.topics[].topics[].label
​Appendix K7 Legacy Instruction Syntax for
AArch32 Instruction Sets

# topic.topics[].topics[].topics[].topics[].label
​K7.1.1 Pre-UAL instruction syntax for the
A32 base instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K7.1.1 Pre-UAL instruction syntax for the
A32 base instructions

# topic.topics[].topics[].topics[].topics[].label
​K7.1.2 Pre-UAL instruction syntax for the
A32 floating-point instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K7.1.2 Pre-UAL instruction syntax for the
A32 floating-point instructions

# topic.topics[].topics[].anchors[].title
​Appendix K7 Legacy Instruction Syntax for
AArch32 Instruction Sets

# topic.topics[].topics[].label
​Appendix K8 Address Translation
Examples

# topic.topics[].topics[].topics[].label
​K8.1 AArch64 Address translation
examples

# topic.topics[].topics[].topics[].topics[].label
​K8.1.1 Examples of performing the initial
lookup

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K8.1.1 Examples of performing the initial
lookup

# topic.topics[].topics[].topics[].topics[].label
​K8.1.2 Full translation flows for VMSAv8-64
address translation

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K8.1.2 Full translation flows for VMSAv8-64
address translation

# topic.topics[].topics[].topics[].anchors[].title
​K8.1 AArch64 Address translation
examples

# topic.topics[].topics[].topics[].label
​K8.2 AArch32 Address translation
examples

# topic.topics[].topics[].topics[].topics[].label
​K8.2.1 Address translation examples using
the VMSAv8-32 Short descriptor translation table format

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K8.2.1 Address translation examples using
the VMSAv8-32 Short descriptor translation table format

# topic.topics[].topics[].topics[].topics[].label
​K8.2.2 Address translation examples using
the VMSAv8-32 Long descriptor translation table format

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K8.2.2 Address translation examples using
the VMSAv8-32 Long descriptor translation table format

# topic.topics[].topics[].topics[].anchors[].title
​K8.2 AArch32 Address translation
examples

# topic.topics[].topics[].anchors[].title
​Appendix K8 Address Translation
Examples

# topic.topics[].topics[].label
​Appendix K9 Recommended Upload and Download
Processes for External Debug

# topic.topics[].topics[].topics[].label
​K9.1 Using Memory access mode in AArch64
state

# topic.topics[].topics[].topics[].anchors[].title
​K9.1 Using Memory access mode in AArch64
state

# topic.topics[].topics[].anchors[].title
​Appendix K9 Recommended Upload and Download
Processes for External Debug

# topic.topics[].topics[].topics[].label
​K10.1 Use of the Advanced SIMD complex
number instructions

# topic.topics[].topics[].topics[].anchors[].title
​K10.1 Use of the Advanced SIMD complex
number instructions

# topic.topics[].topics[].topics[].label
​K10.2 Use of the Armv8.2 extensions to the
Cryptographic Extension

# topic.topics[].topics[].topics[].anchors[].title
​K10.2 Use of the Armv8.2 extensions to the
Cryptographic Extension

# topic.topics[].topics[].topics[].label
​K10.3 SVE and SVE2 Programming
Examples

# topic.topics[].topics[].topics[].anchors[].title
​K10.3 SVE and SVE2 Programming
Examples

# topic.topics[].topics[].topics[].label
​K10.4 Use of the FEAT_PCDPHINT STSHH and
PRFM IR (immediate) hint instructions

# topic.topics[].topics[].topics[].topics[].label
​K10.4.1 Example ticket lock use of the
STSHH hint instruction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K10.4.1 Example ticket lock use of the
STSHH hint instruction

# topic.topics[].topics[].topics[].topics[].label
​K10.4.2 Example data sharing use of the
STSHH and PRFM IR (immediate) instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K10.4.2 Example data sharing use of the
STSHH and PRFM IR (immediate) instructions

# topic.topics[].topics[].topics[].anchors[].title
​K10.4 Use of the FEAT_PCDPHINT STSHH and
PRFM IR (immediate) hint instructions

# topic.topics[].topics[].topics[].label
​K10.5 Use of the Embedded Trace and Trace
Buffer Extensions

# topic.topics[].topics[].topics[].topics[].label
​K10.5.2
Stage 1, parsing the byte stream

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K10.5.2
Stage 1, parsing the byte stream

# topic.topics[].topics[].topics[].topics[].label
​K10.5.3 Stage 2, speculation
resolution

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K10.5.3 Stage 2, speculation
resolution

# topic.topics[].topics[].topics[].topics[].label
​K10.5.4 Stage 2, transaction
resolution

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K10.5.4 Stage 2, transaction
resolution

# topic.topics[].topics[].topics[].topics[].label
​K10.5.9
Differences between ETM and ETE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K10.5.9
Differences between ETM and ETE

# topic.topics[].topics[].topics[].topics[].label
​K10.5.11
Controlling generation of trace buffer management events

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K10.5.11
Controlling generation of trace buffer management events

# topic.topics[].topics[].topics[].anchors[].title
​K10.5 Use of the Embedded Trace and Trace
Buffer Extensions

# topic.topics[].topics[].topics[].topics[].label
​K10.6.1 Recording the call stacks from the
current PE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K10.6.1 Recording the call stacks from the
current PE

# topic.topics[].topics[].topics[].topics[].label
​K10.6.2 Recording the call stacks from a
different PE

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K10.6.2 Recording the call stacks from a
different PE

# topic.topics[].topics[].topics[].topics[].label
​K10.6.3 Overwriting a Guarded Control Stack
record from a higher Exception level

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K10.6.3 Overwriting a Guarded Control Stack
record from a higher Exception level

# topic.topics[].topics[].topics[].topics[].label
​K10.6.5 Switching EL0 Guarded Control
Stacks from EL1

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K10.6.5 Switching EL0 Guarded Control
Stacks from EL1

# topic.topics[].topics[].topics[].topics[].label
​K10.6.6 Synchronization of GCS
accesses

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K10.6.6 Synchronization of GCS
accesses

# topic.topics[].topics[].topics[].topics[].label
​K10.7.1 Using DC {G}ZVA and DC CI{GD}VAPS
to remove poison

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K10.7.1 Using DC {G}ZVA and DC CI{GD}VAPS
to remove poison

# topic.topics[].topics[].topics[].label
​K10.8 Example OS Save and Restore
sequences

# topic.topics[].topics[].topics[].anchors[].title
​K10.8 Example OS Save and Restore
sequences

# topic.topics[].topics[].topics[].label
​K11.2 Load-Acquire, Store-Release and
barriers

# topic.topics[].topics[].topics[].topics[].label
​K11.2.2 Address dependency with object
construction

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K11.2.2 Address dependency with object
construction

# topic.topics[].topics[].topics[].anchors[].title
​K11.2 Load-Acquire, Store-Release and
barriers

# topic.topics[].topics[].topics[].label
​K11.3 Load-Acquire Exclusive, Store-Release
Exclusive and barriers

# topic.topics[].topics[].topics[].topics[].label
​K11.3.4 Use of Wait For Event (WFE) and
Send Event (SEV) with locks

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K11.3.4 Use of Wait For Event (WFE) and
Send Event (SEV) with locks

# topic.topics[].topics[].topics[].anchors[].title
​K11.3 Load-Acquire Exclusive, Store-Release
Exclusive and barriers

# topic.topics[].topics[].topics[].label
​K11.4 Using a mailbox to send an
interrupt

# topic.topics[].topics[].topics[].anchors[].title
​K11.4 Using a mailbox to send an
interrupt

# topic.topics[].topics[].topics[].label
​K11.5 Cache and TLB maintenance
instructions and barriers

# topic.topics[].topics[].topics[].topics[].label
​K11.5.1 Data cache maintenance
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K11.5.1 Data cache maintenance
instructions

# topic.topics[].topics[].topics[].topics[].label
​K11.5.3 TLB maintenance instructions and
barriers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K11.5.3 TLB maintenance instructions and
barriers

# topic.topics[].topics[].topics[].topics[].label
​K11.5.4 Ordering of Memory-mapped device
control with payloads

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K11.5.4 Ordering of Memory-mapped device
control with payloads

# topic.topics[].topics[].topics[].anchors[].title
​K11.5 Cache and TLB maintenance
instructions and barriers

# topic.topics[].topics[].topics[].label
​K12.1 Properties of the generated random
number

# topic.topics[].topics[].topics[].anchors[].title
​K12.1 Properties of the generated random
number

# topic.topics[].topics[].topics[].topics[].label
​K13.1.1 General limitations of Arm
pseudocode

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K13.1.1 General limitations of Arm
pseudocode

# topic.topics[].topics[].topics[].label
​K13.2 Pseudocode for instruction
descriptions

# topic.topics[].topics[].topics[].topics[].label
​K13.2.1 Instruction encoding diagrams and
instruction pseudocode

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K13.2.1 Instruction encoding diagrams and
instruction pseudocode

# topic.topics[].topics[].topics[].topics[].label
​K13.2.2 Limitations of the instruction
pseudocode

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K13.2.2 Limitations of the instruction
pseudocode

# topic.topics[].topics[].topics[].anchors[].title
​K13.2 Pseudocode for instruction
descriptions

# topic.topics[].topics[].topics[].label
​K13.5 Statements and control structures

# topic.topics[].topics[].topics[].anchors[].title
​K13.5 Statements and control structures

# topic.topics[].topics[].topics[].label
​K13.7 Miscellaneous helper procedures and
functions

# topic.topics[].topics[].topics[].anchors[].title
​K13.7 Miscellaneous helper procedures and
functions

# topic.topics[].topics[].topics[].label
​K14.1 Introduction and register
disambiguation

# topic.topics[].topics[].topics[].topics[].label
​K14.1.1 Register name disambiguation by
Execution state

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K14.1.1 Register name disambiguation by
Execution state

# topic.topics[].topics[].topics[].topics[].label
​K14.1.2 Register name disambiguation by
Exception level

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K14.1.2 Register name disambiguation by
Exception level

# topic.topics[].topics[].topics[].anchors[].title
​K14.1 Introduction and register
disambiguation

# topic.topics[].topics[].topics[].label
​K14.2 Alphabetical index of AArch64
registers and System instructions

# topic.topics[].topics[].topics[].anchors[].title
​K14.2 Alphabetical index of AArch64
registers and System instructions

# topic.topics[].topics[].topics[].label
​K14.3 Functional index of AArch64 registers
and System instructions

# topic.topics[].topics[].topics[].topics[].label
​K14.3.11 Memory Partitioning and Monitoring
registers

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K14.3.11 Memory Partitioning and Monitoring
registers

# topic.topics[].topics[].topics[].topics[].label
​K14.3.13 Cache maintenance system
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K14.3.13 Cache maintenance system
instructions

# topic.topics[].topics[].topics[].topics[].label
​K14.3.15 TLB maintenance system
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K14.3.15 TLB maintenance system
instructions

# topic.topics[].topics[].topics[].anchors[].title
​K14.3 Functional index of AArch64 registers
and System instructions

# topic.topics[].topics[].topics[].label
​K14.4 Alphabetical index of AArch32
registers and System instructions

# topic.topics[].topics[].topics[].anchors[].title
​K14.4 Alphabetical index of AArch32
registers and System instructions

# topic.topics[].topics[].topics[].label
​K14.5 Functional index of AArch32 registers
and System instructions

# topic.topics[].topics[].topics[].topics[].label
​K14.5.9 Cache maintenance system
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K14.5.9 Cache maintenance system
instructions

# topic.topics[].topics[].topics[].topics[].label
​K14.5.11 TLB maintenance system
instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K14.5.11 TLB maintenance system
instructions

# topic.topics[].topics[].topics[].topics[].label
​K14.5.13 Legacy feature registers and
system instructions

# topic.topics[].topics[].topics[].topics[].anchors[].title
​K14.5.13 Legacy feature registers and
system instructions

# topic.topics[].topics[].topics[].anchors[].title
​K14.5 Functional index of AArch32 registers
and System instructions

# topic.topics[].topics[].topics[].label
​K14.6
Alphabetical index of memory-mapped registers

# topic.topics[].topics[].topics[].anchors[].title
​K14.6
Alphabetical index of memory-mapped registers

# topic.topics[].topics[].topics[].label
​K14.7
Functional index of memory-mapped registers

# topic.topics[].topics[].topics[].anchors[].title
​K14.7
Functional index of memory-mapped registers

# metadata.contentDescription
This Manual describes the Arm® architecture v8, Armv8, and the Arm® architecture v9, Armv9. The architecture describes the operation of an Armv8-A and an Armv9-A Processing element (PE).