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ARM CoreLink CCI-400 Cache Coherent Interconnect Technical Reference Manual r1p5

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ARM CoreLink CCI-400 Cache Coherent Interconnect Technical Reference Manual

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About the CoreLink Cache Coherent Interconnect

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Product documentation, design flow, and architecture

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Removing a master from the coherent domain

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WriteEvict Transactions memory update operation

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Regulation based on outstanding transactions

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Performance Monitor Control Register (PMCR)

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Read Channel QoS Value Override Register

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Write Channel QoS Value Override Register

# metadata.contentDescription
This is the Technical Reference Manual (TRM) for the CoreLink CCI-400 Cache Coherent Interconnect.