# title
Cortex-A7 MPCore Technical Reference Manual r0p5

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Cortex-A7 MPCore Technical Reference Manual

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About the Cortex-A7 MPCore processor functions

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Communication to the Power Management Controller

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Security Extensions write access disable

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Large Physical Address Extension architecture

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MAIR0 and MAIR1, Memory Attribute Indirection Registers 0 and 1

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Hyp Auxiliary Configuration Register (HACTLR)

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Hyp Auxiliary Configuration Register (HACR)

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Auxiliary Instruction Fault Status Register

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Hyp Auxiliary Data Fault Status Syndrome Register

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Hyp Auxiliary Instruction Fault Status Syndrome Register

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Auxiliary Memory Attribute Indirection Register 0

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Auxiliary Memory Attribute Indirection Register 1

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Hyp Auxiliary Memory Attribute Indirection Register 0

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Hyp Auxiliary Memory Attribute Indirection Register 1

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Instruction cache speculative memory accesses

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Virtual interface control register summary

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Virtual Interface Control Register description

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Virtual CPU interface register description

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Debug External Auxiliary Control Register

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Device Power-down and Reset Control Register

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Integration Miscellaneous Signals Input Register

# metadata.contentDescription
This book is for the Cortex-A7 MPCore processor, a multiprocessor device that has between one to four processors. The book is written for hardware and software engineers implementing the Cortex-A7 MPCore processor in system designs. It provides information that enables designers to integrate the Cortex-A7 MPCore processor into a target system.