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ARM Cortex-R7 MPCore Technical Reference Manual r0p1

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ARM Cortex-R7 MPCore Technical Reference Manual

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Components of the Cortex-R7 MPCore processor

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Addresses in the Cortex-R7 MPCore processor

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System identification, control, and configuration register

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Interface control and configuration registers

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IEEE 754 standard implementation choices

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Processor modes for accessing the FPU system registers

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Floating-Point Status and Control Register

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Memory types and L1 memory system behavior

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Peripherals Filtering Start Address Register

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Peripherals Filtering End Address Register

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AXI protocol configurability, xID and AxUSER

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Optimized accesses to the L2 memory interface

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Event communication with an external agent using WFE/SEV

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Error detection global notification signals

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Bus ECC error signals on AXI master ports

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Bus ECC error signals on AXI peripheral ports

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Bus ECC error signals on AXI slave ports

# metadata.contentDescription
This book is written for system designers, system integrators, and programmers who are designing or programming a System-on-Chip (SoC) that uses the Cortex-R7 MPCore processor.