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Cortex-A15 MPCore Processor Technical Reference Manual r4p0

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ARM Cortex-A15 MPCore Processor Technical Reference Manual

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About the Cortex-A15 MPCore processor functions

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Event communication using WFE and SEV instructions

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Security Extensions configuration write access disable

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Large Physical Address Extension architecture

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Translation Table Base Register 0 and Register 1

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Auxiliary Instruction Fault Status Register

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Hyp Auxiliary Data Fault Syndrome Register

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Hyp Auxiliary Instruction Fault Syndrome Register

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Auxiliary Memory Attribute Indirection Register 0

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Auxiliary Memory Attribute Indirection Register 1

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Hyp Auxiliary Memory Attribute Indirection Register 0

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Hyp Auxiliary Memory Attribute Indirection Register 1

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Instruction cache speculative memory accesses

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Cache line length and heterogeneous systems

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Strictly-enforced inclusion property with L1 data caches

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Register slice support for large cache sizes

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Virtual interface control register summary

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Virtual interface control register descriptions

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Virtual CPU interface register descriptions

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Debug External Auxiliary Control Register

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Device Powerdown and Reset Control Register

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Performance Monitor Common Event Identification Register 0

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Performance Monitor Common Event Identification Register 1

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Effect of OS Double Lock on PMU register access

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Interaction with the performance monitoring unit

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Effect of OS Double Lock on trace register access

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Extended External Input Selection Register

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Accessing the Advanced SIMD and VFP feature identification registers

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Enabling Advanced SIMD and VFP extensions

# metadata.contentDescription
This is the Technical Reference Manual (TRM) for the Cortex-A15 MPCore processor.