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Arm Cortex-A5 MPCore Technical Reference Manual r0p1

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Cortex-A5 MPCore Technical Reference Manual

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Product documentation, design flow, and architecture

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Individual Cortex-A5 core power management

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Communication to the Power Management Controller

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Interworking ARM and Thumb code sequences

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Addresses in the Cortex-A5 MPCore processor

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Security Extensions write access disable

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c0, Instruction set attributes registers

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Instruction Set Attributes Registers 6-7

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Auxiliary Instruction Fault Status Register

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Jazelle Identity and Miscellaneous Functions Register

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Jazelle Operating System Control Register

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Jazelle Configurable Opcode Translation Table Register

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Cortex-A5 MPCore configuration and control registers

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SCU Invalidate All in Secure State Register

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Global Timer Counter Registers, 0x00 and 0x04

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Private Peripheral Interrupt Status Register

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Shared Peripheral Interrupt Status Registers

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Operating System Lock and Save/Restore Registers

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Device Power-down and Reset Control Register

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Device Power-down and Reset Status Register

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Memory mapped accesses, DBGROMADDR, and DBGSELFADDR

# metadata.contentDescription
This book is written for hardware and software engineers implementing Cortex-A5 MPCore system designs. It provides information that enables designers to integrate the MPCore processor into a target system.