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CoreLink DMA-330 DMA Controller Technical Reference Manual r1p2

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CoreLink DMA-330 DMA Controller Technical Reference Manual

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Product documentation, design flow, and architecture

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ARM architecture and protocol information

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How to set the security state of the DMA manager

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How to set the location of the first instruction for the DMAC to execute

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How to set the security state for the interrupt outputs

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How to set the security state for a peripheral request interface

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Issuing instructions to the DMAC using an APB interface

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Peripheral request interface timing diagrams

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DMA manager thread is in the Secure state

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DMA manager thread is in the Non-secure state

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DMA channel thread is in the Secure state

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DMA channel thread is in the Non-secure state

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Updating DMA channel control registers during a DMA cycle

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Aligned asymmetric program with multiple loads

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Aligned asymmetric program with multiple stores

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Aligned source address to unaligned destination address

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Unaligned source address to aligned destination address

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Unaligned source address to aligned destination address, with excess initial load

# metadata.contentDescription
This is the Technical Reference Manual (TRM) for the CoreLink DMA Controller (DMA-330).