# title
Cortex-M1 Technical Reference Manual r1p0

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Binary compatibility with Cortex-M3 processor

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Special-purpose program status registers (xPSR)

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Returning the processor from an exception

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Application Interrupt and Reset Control Register

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System Handler Control and State Register

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Debug Halting Control and Status Register

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Debug Exception and Monitor Control Register

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Examples of debug register halt, access, and step

# metadata.contentDescription
This is the Technical Reference Manual (TRM) for the Cortex-M1 processor.