# title
CoreLink Level 2 MBIST Controller L2C-310 Technical Reference Manual r3p3

# topic.label
CoreLink Level 2 MBIST Controller L2C-310 Technical Reference Manual

# topic.topics[].topics[].topics[].label
Read latency and write latency fields, MBIR[44:41] and MBIR[48:45]

# topic.topics[].topics[].topics[].label
Y-address and X-address fields, MBIR[36:33] and MBIR[40:37]

# metadata.contentDescription
This book is for the Technical Reference Manual (TRM) for the CoreLink Level 2 Memory Built In Self Test (MBIST) Controller L2C-310. In this manual the generic term MBIST controller means the CoreLink Level 2 MBIST Controller, and cache controller means the CoreLink Level 2 Cache Controller.