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Cortex-A9 Technical Reference Manual r4p1

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Program Flow Trace and Program Trace Macrocell

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Preload Engine User Accessibility Register

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Preload Engine Parameters Control Register

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Jazelle Operating System Control Register

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Jazelle Configurable Opcode Translation Table Register

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About the L1 instruction side memory system

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Cortex-A9 behavior for Normal Memory Cacheable memory regions

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Optimized accesses to the L2 memory interface

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Prefetch hint to the L2 memory interface

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AXI Master1 signals instruction accesses

# metadata.contentDescription
This is the Technical Reference Manual for the Cortex-A9 processor.