# title
ARM Architecture Reference Manual Debug supplement

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ARM Architecture Reference Manual Debug supplement

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unpredictable behavior on Software Debug events

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Effects of Debug Exceptions on CP15 registers and the WFAR

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The effect of entering Debug state on core registers

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The effect of entering Debug state on CP15 registers and the WFAR

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Imprecise Data Aborts and entry to Debug state

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Behavior of the PC and CPSR in Debug state

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Data processing instructions with R15 as the target

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Altering CPSR Privileged bits in Debug state

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Behavior of non-invasive debug in Debug state

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Operating System Save and Restore support

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Internal and external views of DSCR and DTR

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Synchronization of debug register updates

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Permissions in relation to the privilege of the access

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Access to Reserved and implementation defined locations

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The Memory-mapped and recommended external debug interfaces

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Shared interface port for the Memory-mapped and external debug interfaces

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Permission summaries for Memory-mapped and external debug interface

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Registers not implemented in the Memory-mapped or external debug interface

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EDBGRQ, DBGTRIGGER, DBGCPUDONE and DBGACK

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About debug requirements on memory systems

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Recommended access to specific CP15 registers

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Non-invasive debug authentication, Security Extensions not implemented

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Interaction with power saving operations

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Power domains and performance counters registers reset

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Debug Self Address Offset Register (DSAR)

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Debug Status and Control Register (DSCR)

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Watchpoint Fault Address Register (WFAR)

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Device Power-Down and Reset Control Register (PRCR)

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Device Power-Down and Reset Status Register (PRSR)

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Program Counter Sampling Register (PSCR)

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Host to Target Data Transfer Register (DTRRX)

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Target to Host Data Transfer Register (DTRTX)

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Operating-system save and restore registers

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Debug State Cache Control Register (DSCCR)

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Debug State MMU Control Register (DSMCR)

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Integration Mode Control Register (ITCTRL)

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Performance Monitor Control Register (PMNC)

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Interrupt Enable Clear Register (INTENC)

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Performance Counter Selection Register (PMNXSEL)

# metadata.contentDescription
The purpose of this manual is to describe the ARM Debug architecture. It is a supplement to the ARM Architecture Reference Manual (ARM DDI 0100, the ARM ARM), and is intended to be used with it.