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Cortex-R4 and Cortex-R4F Technical Reference Manual r1p4

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Cortex-R4 and Cortex-R4F Technical Reference Manual

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Product documentation, architecture and design flow

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Modification of PSR bits by MSR instructions

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Unaligned and mixed-endian data access support

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System identification control and configuration

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c0, Current Cache Size Identification Register

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c15, Secondary Auxiliary Control Register

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c6, MPU memory region programming registers

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Controlling instruction prefetch and program flow prediction

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c9, Performance Monitor Control Register

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c9, Performance Counter Selection Register

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About the error detection and correction schemes

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TCM internal error detection and correction

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Memory types and L1 memory system behavior

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Linefill buffers and the AXI master interface

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Enabling or disabling AXI slave accesses

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Accessing RAMs using the AXI slave interface

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Communication to the Power Management Controller

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Floating-Point Status and Control Register, FPSCR

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Media and VFP Feature Registers, MVFR0 and MVFR1

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Complete implementation of the IEEE 754 standard

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IEEE 754 standard implementation choices

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Memory addresses for breakpoints and watchpoints

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CP14 c0, Debug Self Address Offset Register

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CP14 c1, Debug Status and Control Register

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Device Power-down and Reset Control Register

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Device Power-down and Reset Status Register

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Behavior of the processor on debug events

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Effect of debug exceptions on CP15 registers and DBGWFAR

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Behavior of the PC and CPSR in debug state

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Effect of debug state on non-invasive debug

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Effects of debug events on processor registers

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Accessing registers and memory in debug state

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Debugging systems with energy management capabilities

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Summary of the processor registers used for integration testing

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Interrupt signals, including VIC interface signals

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About cycle timings and interlock behavior

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QADD, QDADD, QSUB, and QDSUB instructions

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Load and Store Multiples, other than load multiples including the PC

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Load Multiples, where the PC is in the register list

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SVC, BKPT, Undefined, and Prefetch Aborted instructions

# metadata.contentDescription
This is the Technical Reference Manual for the Cortex-R4 and Cortex-R4F processors.