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ARM11 MPCore Processor Technical Reference Manual r2p0

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ARM11 MPCore Processor Technical Reference Manual

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MPCore architecture with Jazelle technology

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ARM state and Thumb state registers relationship

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Modification of PSR bits by MSR instructions

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Imprecise Data Abort mask in the CPSR/SPSR

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Summary of control coprocessor CP15 registers and operations

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c0, Instruction Set Attributes Registers

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c2, Translation Table Base Control Register

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c15, Performance Monitor Control Register (PMNC)

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c15, Count Register 0 (PMN0) and Count Register 1 (PMN1)

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Unaligned and Mixed-Endian Data Access Support

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About unaligned and mixed-endian support

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Word-invariant mode and ARMv6 configurations

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Word-invariant data access in ARMv6 (U=0)

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Support for unaligned data access in ARMv6 (U=1)

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ARMv6 unaligned data access restrictions

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Load double, load multiple, load coprocessor (little-endian, E = 0)

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Load double, load multiple, load coprocessor (big-endian, E=1)

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Store double, store multiple, store coprocessor (little-endian, E=0)

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Store double, store multiple, store coprocessor (big-endian, E=1)

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Instructions to reverse bytes in a general-purpose register

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C and B bit, and type extension field encodings

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Page table descriptors when using remapping

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Ordering requirements for memory accesses

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Backwards-compatible page table translation (subpage AP bits enabled)

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ARMv6 page table translation subpage AP bits disabled

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Restrictions on page table mappings for the instruction cache

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About the Level 1 data side memory system

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About the Level 1 instruction side memory system

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Watchdog Interrupt Status Register, 0x2C

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About the Distributed Interrupt Controller

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Distributed Interrupt Controller clock frequency

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Interrupt Distributor Control Register, 0x000

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Interrupt Controller Type Register, 0x004

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Interrupt Enable clear and Enable set registers, 0x100-0x11C and 0x180-0x19C

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Interrupt Pending clear and Pending set registers, 0x200-0x21C and 0x280-0x29C

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Interrupt CPU Targets Registers, 0x800-0x8FC

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Interrupt Line Level Registers, 0xD00-0xD1C

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Highest Pending Interrupt Register, 0x18

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Communication to the Power Management Controller

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CP14 c1, Debug Status and Control Register (DSCR)

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CP14 c64-c69, Breakpoint Value Registers (BVR)

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CP14 c80-c85, Breakpoint Control Registers (BCR)

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CP14 c96-c97, Watchpoint Value Registers (WVR)

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CP14 c112-c113, Watchpoint Control Registers (WCR)

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Behavior of the processor on debug events

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Effect of a debug event on CP15 registers

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Setting breakpoints, watchpoints, and vector catch debug events

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Setting software breakpoint debug events (BKPT)

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Debug Test Access Port and Halting debug-mode

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Transferring data between the host and the core

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Target to host debug communications channel sequence

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Host to target debug communications channel

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Reading a current mode ARM register in the range r0-r14

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Writing a current mode ARM register in the range r0-r14

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General notes about reading and writing memory

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Setting breakpoints, watchpoints and vector catches

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About cycle timings and interlock behavior

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Cycle counts if destination is not the PC

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QADD, QDADD, QSUB, and QDSUB instructions

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Load and store multiples, other than load multiples including the PC

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Load multiples, where the PC is in the register list

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SWI, BKPT, Undefined, and Prefetch Aborted instructions

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Maintaining consistency in register precision

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Data transfer between memory and VFP11 registers

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Access to register banks in CDP operations

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An IEEE 754 standard-compliant implementation

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Complete implementation of the IEEE 754 standard

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IEEE 754 standard implementation choices

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Floating-Point System ID Register, FPSID

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Floating-Point Status and Control Register, FPSCR

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Instruction registers, FPINST and FPINST2

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Scoreboard operation when an instruction bounces

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Load multiple-short vector CDP RAW hazard example

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Short vector CDP-load multiple WAR hazard example

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Short vector CDP-load multiple WAR hazard example

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Load multiple-load-CDP resource hazard example

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Load multiple-short vector CDP resource hazard example

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Short vector CDP-CDP resource hazard example

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Potential or actual exception that the VFP11 coprocessor cannot handle

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Potential or actual exception with the exception enable bit set

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Determination of the trigger instruction

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Exception processing for CDP scalar instructions

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Exception processing for CDP short vector instructions

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Examples of exception detection for vector instructions

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MBIST controller and MBIST dispatch unit

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MBIST tester and MBIST controller signals

# metadata.contentDescription
This book is for the ARM11 MPCore Processor.