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Cortex-A8 Technical Reference Manual r3p2

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Modification of PSR bits by MSR instructions

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Imprecise data abort mask in the CPSR/SPSR

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Software consideration for Security Extensions

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Hardware consideration for Security Extensions

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Security Extensions write access disable

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System control coprocessor functional groups

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L2 cache preload engine control and configuration

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c0, Instruction Set Attributes Register 0

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c0, Instruction Set Attributes Register 1

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c0, Instruction Set Attributes Register 2

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c0, Instruction Set Attributes Register 3

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c0, Instruction Set Attributes Register 4

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c0, Instruction Set Attributes Registers 5-7

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c2, Translation Table Base Control Register

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c9, Performance Monitor Control Register

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c9, Performance Counter Selection Register

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c11, PLE Identification and Status Registers

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c11, PLE Internal Start Address Register

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c12, Secure or Nonsecure Vector Base Address Register

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c12, Monitor Vector Base Address Register

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c15, L1 system array debug data registers

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c15, L2 system array debug data registers

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Unaligned Data and Mixed-endian Data Support

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Instruction cache speculative memory accesses

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Hardware support for virtual aliasing conditions

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Enabling and disabling the L2 cache controller

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Preload engine commands and status interaction

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Interaction of the preload engine with WFI

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Memory region interaction with the preload engine

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Processor configuration and the impact on the preload engine

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Effects of cache maintenance operations during preloading engine transfers

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External interface servicing instruction fetch transactions

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External interface servicing data transactions

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Read/write data bus width configuration pin

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NEON accesses to strongly ordered and device memory

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Debugging the processor while powered down

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Special note on reset during power transition

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Memory addresses for breakpoints and watchpoints

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CP14 c0, Debug Self Address Offset Register

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CP14 c1, Debug Status and Control Register

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Operating System Save and Restore Register

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Device Power Down and Reset Control Register

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Device Power Down and Reset Status Register

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Integration Internal Output Control Register

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Integration External Output Control Register

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Behavior of the processor on debug events

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Effect of debug exceptions on CP15 registers and WFAR

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Behavior of the PC and CPSR in debug state

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Effect of debug state on noninvasive debug

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Accessing registers and memory in debug state

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Debugging systems with energy management capabilities

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About the NEON and VFP programmers model

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Floating-Point System ID Register, FPSID

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Floating-Point Status and Control Register, FPSCR

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Media and VFP Feature Registers, MVFR0 and MVFR1

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Complete implementation of the IEEE 754 standard

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IEEE 754 standard implementation choices

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Address comparators configured for instruction addresses

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Address comparators configured for data addresses

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Interaction with the Performance Monitoring Unit

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CTI Interrupt Acknowledge Register, CTIINTACK

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CTI Application Trigger Set Register, CTIAPPSET

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CTI Application Trigger Clear Register, CTIAPPCLEAR

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CTI Application Pulse Register, CTIAPPPULSE

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CTI Trigger to Channel Enable Registers, CTIINEN0-8

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CTI Channel to Trigger Enable Registers, CTIOUTEN0-8

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CTI Trigger In Status Register, CTITRIGINSTATUS

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CTI Trigger Out Status Register, CTITRIGOUTSTATUS

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CTI Channel In Status Register, CTICHINSTATUS

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CTI Channel Out Status Register, CTICHOUTSTATUS

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Example of how to read ARM instruction tables

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Parallel arithmetic and DSP instructions

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Load multiple and store multiple instructions

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Cycle penalty for instruction flow change

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Memory system effects on instruction timings

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Mixed ARM and Advanced SIMD instruction sequences

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Dual issue for Advanced SIMD instructions

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Example of how to read Advanced SIMD instruction tables

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Advanced SIMD integer multiply instructions

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Advanced SIMD integer shift instructions

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Advanced SIMD register transfer instructions

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VFP instruction execution in the VFP coprocessor

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VFP instruction execution in the NFP pipeline

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APB interface and miscellaneous debug signals

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DFT pins and additional MBIST pin requirements during MBIST testing

# metadata.contentDescription
This is the Technical Reference Manual (TRM) for the Cortex-A8 processor.