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Cortex-M3 Technical Reference Manual  r2p0

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Differences in functionality between r0p0 and r1p0

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Differences in functionality between r1p0 and r1p1

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Differences in functionality between r1p1 and r2p0

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Binary compatibility with other Cortex processors

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Interrupt Controller Type Register, ICTR

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Cortex-M3 ROM table identification and entries

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About the Flash Patch and Breakpoint Unit (FPB)

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Data and instruction address compare resources

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TraceEnable Control 1 Register, ETMTECR1

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Configuration Code Extension Register, ETMCCER

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Device Power-Down Status Register, ETMPDSR

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Integration Test Miscellaneous Inputs, ITMISCIN

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ETM Integration Test ATB Control 2, ETM_ITATBCTR2

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ETM Integration Test ATB Control 0, ETM_ITATBCTR0

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Asynchronous Clock Prescaler Register, TPIU_ACPR

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Formatter and Flush Status Register, TPIU_FFSR

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Formatter and Flush Control Register, TPIU_FFCR

# metadata.contentDescription
The Cortex-M3 is a low-power processor that features low gate count, low interrupt latency, and low-cost debug. It is intended for deeply embedded applications that require FIQ interrupt response features.