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L220 Cache Controller Technical Reference Manual r1p7

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L220 Cache Controller Technical Reference Manual

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Clock enable usage model in the Cache Controller AXI interfaces

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TrustZone support in the cache controller

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Register 2, Event Counter Control Register

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Register 2, Event Counter1 Configuration Register

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Register 2, Event Counter0 Configuration Register

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Register 2, Event Counter1 Value Register

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Register 2, Event Counter0 Value Register

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Register 2, Masked Interrupt Status Register

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Register 2, Raw Interrupt Status Register

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Register 7, Cache Maintenance Operations

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Reset and configuration signal timing parameters

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Slave port 0 I/O signal timing parameters

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Slave port 1 I/O signal timing parameters

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Peripheral slave port signal timing parameters

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Master port 0 I/O signal timing parameters

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Master port 1 I/O signal timing parameters

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Cache interrupt ports signal timing parameters

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MBIST interface signal timing parameters

# metadata.contentDescription
This is the TRM for the L220 Cache Controller.