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CoreSight Components Technical Reference Manual

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CoreSight Components Technical Reference Manual

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Typical CoreSight Design Kit debugging environment

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Common debug port features and registers

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Differentiation between system and access port initiated error responses

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APB-AP Control/Status Word Register, CSW, 0x00

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APB-AP Transfer Address Register, TAR, 0x04

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APB-AP Data Read/Write Register, DRW, 0x0C

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APB-AP Banked Data Registers, BD0-BD3, 0x10-0x1C

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APB-Mux arbitration and APB Mux connectivity

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Authentication requirements for Debug Access Port

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CTI handshaking, synchronization, and clocks

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CTI Interrupt Acknowledge Register, CTIINTACK, 0x010

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CTI Application Trigger Set Register, CTIAPPSET, 0x014

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CTI Application Trigger Clear Register, CTIAPPCLEAR, 0x018

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CTI Application Pulse Register, CTIAPPPULSE, 0x01C

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CTI Trigger to Channel Enable Registers, CTIINEN0-7, 0x020-0x03C

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CTI Channel to Trigger Enable Registers, CTIOUTEN0-7, 0x0A0-0x0BC

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CTI Trigger In Status Register, CTITRIGINSTATUS, 0x130

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CTI Trigger Out Status Register, CTITRIGOUTSTATUS, 0x134

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CTI Channel In Status Register, CTICHINSTATUS, 0x138

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CTI Channel Out Status Register, CTICHOUTSTATUS, 0x13C

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Enable CTI Channel Gate Register, CTIGATE, 0x140

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External Multiplexor Control Register, ASICCTL, 0x144

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Authentication requirements for ATB 1:1 Bridge

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Supported Test Patterns/Modes Register, 0x200

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Current Test Patterns/Modes Register, 0x204

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TPIU Test Pattern Repeat Counter Register, 0x208

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Formatter and Flush Status Register, 0x300

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Formatter and Flush Control Register, 0x304

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Capturing trace after an event and stopping

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Only indicating triggers and still flushing

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ETB RAM Read Pointer Register, RRP, 0x014

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ETB RAM Write Pointer Register, RWP, 0x018

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ETB Trigger Counter Register, TRG, 0x01C

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ETB Formatter and Flush Status Register, FFSR, 0x300

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ETB Formatter and Flush Control Register, FFCR, 0x304

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Write address generation for trace data storage

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Authentication requirements for CoreSight ETBs

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ETM architecture version no longer required

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Integration Mode Control Register, 0xF00 [0]

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Claim Tag Set and Clear Registers, 0xFA0 [3:0] and 0xFA4 [3:0]

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Supported Synchronous Port Size Register, SPR, 0x000

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Current Synchronous Port Size Register, CPR, 0x004

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Current Output Divisor Register, CODR, 0x010

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Selected Pin Protocol Register, SPPR, 0xF0

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Supported Trigger Mode Register, STMR, 0x100

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Supported Test Patterns and Modes Register, STPR, 0x200

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Formatter and Flush Status Register, FFSR, 0x300

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Formatter and Flush Control Register, FFCR, 0x304

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Integration Test ATB Data Register 0, ITATBDATA0, 0xEEC

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Integration Test ATB Control Register 2, ITATBCTR2, 0xEF0

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Integration Test ATB Control Register 0, ITATBCTR0, 0xEF8

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About the Instrumentation Trace Macrocell

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Integration Mode Control Register, 0xF00

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Claim Tag Set Register, 0xFA0, and Claim Tag Clear Register, 0xFA4

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Lock Access Register, 0xFB0, and Lock Status Register, 0xFB4

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Synchronization Control Register, SCR, 0xE90

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Integration Test Trigger Out Acknowledge Register, ITTRIGOUTACK, 0xEE4

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Integration Test Trigger Out Register, ITTRIGOUT, 0xEE8

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Integration Test ATB Data Register 0, ITATBDATA0, 0xEEC

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Integration Test ATB Control Register 2, ITATBCTR2, 0xEF0

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Integration Test ATB Control Register 1, ITATBCTR1, 0xEF4

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Integration Test ATB Control Register 0, ITATBCTR0, 0xEF8

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Serial Wire Debug and JTAG Trace Connector

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20-way connector pinouts including trace

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About the deprecated SWJ-DP switching sequences

# metadata.contentDescription
The CoreSight components provide a multi-core debug and trace solution with high bandwidth for whole systems, including trace and monitor of the system bus.