# title
ARM1156T2F-S Technical Reference Manual r0p4

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ARM1156T2F-S architecture with Thumb-2 core technology

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Modification of PSR bits by MSR instructions

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Imprecise Data Abort mask in the CPSR/SPSR

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System control processor functional groups

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c9, Data and instruction cache lockdown registers

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c15, Instruction cache Tag RAM operation

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c15, Instruction Cache Data RAM operation

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c15, Cache Data RAM parity read operations

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c15, Instruction Cache Master Valid Register

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c15, Data Cache Valid RAM and Dirty RAM bit write operation

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c15, Performance Monitor Control Register

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System control coprocessor reference data

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Instruction Memory Barrier (IMB) instruction

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Ordering requirements for memory accesses

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C and B bit, and type extension field encodings

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Unaligned and Mixed-Endian Data Access Support

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About unaligned and mixed-endian support

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Word-invariant mode and ARMv6 configurations

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Word-invariant data access in ARMv6 (U=0)

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Support for unaligned data access in ARMv6 (U=1)

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ARMv6 unaligned data access restrictions

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Load double, load multiple, load coprocessor (little-endian, E = 0)

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Load double, load multiple, load coprocessor (big-endian, E=1)

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Store double, store multiple, store coprocessor (little-endian, E=0)

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Store double, store multiple, store coprocessor (big-endian, E=1)

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Differences between BE-32 and BE-8 buses

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Interaction between the Bus protocol and the core endianness

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Word-invariant fixed instruction and data endianness

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Instructions to reverse bytes in a general-purpose register

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Cacheable Write-Through or Noncacheable STRB

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Cacheable Write-Through or Noncacheable STRH

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Cacheable Write-Through or Noncacheable STR or STM1

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Cacheable Write-Through or Noncacheable STRD or STM2

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Cacheable Write-Through or Noncacheable STM3

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Cacheable Write-Through or Noncacheable STM4

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Cacheable Write-Through or Noncacheable STM5

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Cacheable Write-Through or Noncacheable STM6

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Cacheable Write-Through or Noncacheable STM7

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Cacheable Write-Through or Noncacheable STM8

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Cacheable Write-Through or Noncacheable STM9

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Cacheable Write-Through or Noncacheable STM10

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Cacheable Write-Through or Noncacheable STM11

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Cacheable Write-Through or Noncacheable STM12

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Cacheable Write-Through or Noncacheable STM13

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Cacheable Write-Through or Noncacheable STM14

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Cacheable Write-Through or Noncacheable STM15

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Cacheable Write-Through or Noncacheable STM16

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Communication to the Power Management Controller

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About the PL192 Vectored Interrupt Controller

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CP14 c1, Debug Status and Control Register (DSCR)

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CP14 c6, Watchpoint Fault Address Register (WFAR)

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CP14 c64-c69, Breakpoint Value Registers (BVR)

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CP14 c80-c85, Breakpoint Control Registers (BCR)

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CP14 c96-c97, Watchpoint Value Registers (WVR)

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CP14 c112-c113, Watchpoint Control Registers (WCR)

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Behavior of the processor on debug events

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Effect of a debug event on CP15 registers

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Behavior on the execution state bits in Debug state

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Setting breakpoints, watchpoints, and vector catch debug events

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Setting software breakpoint debug events (BKPT)

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Debug Test Access Port and Halting debug-mode

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Transferring data between the host and the core

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Target to host debug communications channel sequence

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Host to target debug communications channel

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Reading a current mode ARM register in the range r0-r14

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Writing a current mode ARM register in the range r0-r14

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General notes about reading and writing memory

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Setting breakpoints, watchpoints and vector catches

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About cycle timings and interlock behavior

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QADD, QDADD, QSUB, and QDSUB instructions

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Load and Store Multiples, other than Load Multiples including the PC

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Load Multiples, where the PC is in the register list

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SVC, BKPT, undefined, and prefetch aborted instructions

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Maintaining consistency in register precision

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Data transfer between memory and VFP11 registers

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Access to register banks in CDP operations

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An IEEE 754 standard-compliant implementation

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Complete implementation of the IEEE 754 standard

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IEEE 754 standard implementation choices

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Floating-Point System ID Register, FPSID

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Floating-Point Status and Control Register, FPSCR

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Instruction registers, FPINST and FPINST2

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Scoreboard operation when an instruction bounces

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Load multiple-short vector CDP RAW hazard example

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Short vector CDP-load multiple WAR hazard example

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Short vector CDP-load multiple WAR hazard example

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Load multiple-load-CDP resource hazard example

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Load multiple-short vector CDP resource hazard example

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Short vector CDP-CDP resource hazard example

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Potential or actual exception that the VFP11 coprocessor cannot handle

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Potential or actual exception with the exception enable bit set

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Determination of the trigger instruction

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Exception processing for CDP scalar instructions

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Exception processing for CDP short vector instructions

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Examples of exception detection for vector instructions

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Interrupt signals (including VIC interface signals)

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Debug interface signals (including JTAG)

# metadata.contentDescription
This is the technical reference manual for the ARM1156T2F-S processor. In this manual the generic term processor means the ARM1156T2F-S processor.