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L210 Cache Controller Technical Reference Manual r0p5

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L210 Cache Controller Technical Reference Manual

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RAM configuration versus associativity and way size

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MBIST testing of cache controller data RAM

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MBIST testing of cache controller data parity RAM

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MBIST testing of the cache controller tag RAMs

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MBIST testing of the cache controller dirty RAM

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Cache controller interface signal timing parameters

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ARM926EJ-S and ARM1026EJ-S memory systems

# metadata.contentDescription
This is the Technical Reference Manual (TRM) for the ARM PrimeCell L210 Level 2 Cache Controller (L210). For purposes of this manual the cache controller refers to the L210 Cache Controller.