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MultiPort Memory Controller (GX176) Technical Reference Manual r0p1

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MultiPort Memory Controller (GX176) Technical Reference Manual

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Micron style V-synchronous flash devices

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Overview of a MPMC, ASIC, or ASSP system

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Worst case transaction latency for the highest priority AHB memory port

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Worst case transaction latency for the lower priority AHB memory ports

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System factors affecting worst case latency

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Sharing memory bandwidth between AHB ports

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Typical AHB port TimeOut value given bandwidth requirement

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Typical AHB port TimeOut value given percentage of memory bandwidth requirement

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Typical AHB bandwidth requirement example

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Typical AHB percentage bandwidth example

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Chip select 1 static memory configuration

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Chip select 5 SDRAM memory configuration

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Boot from flash, SRAM remapped after boot

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Example of a boot from flash, SDRAM remapped after boot

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Dynamic Memory Read Configuration Register

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Dynamic Memory Precharge Command Period Register

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Dynamic Memory Active To Precharge Command Period Register

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Dynamic Memory Self-refresh Exit Time Register

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Dynamic Memory Write Recovery Time Register

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Dynamic Memory Active To Active Command Period Register

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Dynamic Memory Auto-refresh Period Register

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Dynamic Memory Exit Self-refresh Register

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Dynamic Memory Active Bank A-B Time Register

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Dynamic Memory Last Data In To Read Command Time Register

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Dynamic Memory Configuration Registers 0-3

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Dynamic Memory RAS and CAS Delay Registers 0-3

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Static Memory Configuration Registers 0-3

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Static Memory Write Enable Delay Registers 0-3

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Static Memory Output Enable Delay Registers 0-3

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Static Memory Page Mode Read Delay Registers 0-3

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Static Memory Turnaround Delay Registers 0-3

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NAND Memory Address Vectors 1-4 Register

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Non-AMBA intra-chip integration test strategy

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Test Interface Controller (TIC) AHB signals

# metadata.contentDescription
This document is the technical reference manual for the ARM MultiPort Memory Controller (MPMC).