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MultiPort Memory Controller (GX175) Technical Reference Manual r0p2

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MultiPort Memory Controller (GX175) Technical Reference Manual

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Examples of Micron style SyncFlash devices

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Examples of JEDEC low-power SDRAM devices

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Overview of a MPMC, ASIC, or ASSP system

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Worst case transaction latency for the highest priority AHB memory port

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Worst case transaction latency for the lower priority AHB memory ports

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System factors affecting worst case latency

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Sharing memory bandwidth between AHB ports

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Typical AHB port TimeOut value given bandwidth requirement

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Typical AHB port TimeOut value given percentage of memory bandwidth requirement

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Typical AHB bandwidth requirement example

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Typical AHB percentage bandwidth example

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Chip select 1 static memory configuration

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Chip select 5 SDRAM memory configuration

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Boot from flash, SRAM remapped after boot

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Example of a boot from flash, SDRAM remapped after boot

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Dynamic Memory Refresh Timer Register, MPMCDynamicRefresh

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Dynamic Memory Precharge Command Period Register, MPMCDynamictRP

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Dynamic Memory Active To Precharge Command Period Register, MPMCDynamictRAS

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Dynamic Memory Self-refresh Exit Time Register, MPMCDynamictSREX

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Dynamic Memory Write Recovery Time Register, MPMCDynamictWR

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Dynamic Memory Active To Active Command Period Register, MPMCDynamictRC

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Dynamic Memory Auto-refresh Period Register, MPMCDynamictRFC

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Dynamic Memory Exit Self-refresh Register, MPMCDynamictXSR register

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Dynamic Memory Active Bank A To Active Bank B Time Register, MPMCDynamictRRD

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Dynamic Memory Load Mode Register, MPMCDynamictMRD register

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Dynamic Memory Last Data In To Read Command Time Register, MPMCDynamictCDLR

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Static Memory Extended Wait Register, MPMCStaticExtendedWait

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Dynamic Memory RAS and CAS Delay Registers 0-3, MPMCDynamicRasCas0-3

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Static Memory Write Enable Delay Registers 0-3, MPMCStaticWaitWen0-3

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Static Memory Output Enable Delay Registers 0-3, MPMCStaticWaitOen0-3

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Static Memory Read Delay Registers 0-3, MPMCStaticWaitRd0-3

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Static Memory Page Mode Read Delay Registers 0-3, MPMCStaticWaitPage0-3

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Static Memory Write Delay Registers 0-3, MPMCStaticWaitWr0-3

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Static Memory Turn Round Delay Registers 0-3, MPMCStaticWaitTurn0-3

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AHB Control Registers 0-4, MPMCAHBControl0-4

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AHB Status Registers 0-4, MPMCAHBStatus0-4

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AHB TimeOut Registers 0-4, MPMCAHBTimeOut0-4

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Non-AMBA intra-chip integration test strategy

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Test Interface Controller (TIC) AHB signals

# metadata.contentDescription
This is the Technical Reference Manual (TRM) for the ARM PrimeCell (GX175) MultiPort Memory Controller (MPMC).