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VFP11 Vector Floating-point Coprocessor Technical Reference Manual r1p5

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VFP11 Vector Floating-point Coprocessor Technical Reference Manual

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Loading operands from ARM1136JF-S registers

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Maintaining consistency in register precision

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Data transfer between memory and VFP11 registers

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Access to register banks in CDP operations

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An IEEE 754 standard-compliant implementation

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Complete implementation of the IEEE 754 standard

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IEEE 754 standard implementation choices

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Floating-Point System ID Register, FPSID

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Floating-Point Status and Control Register, FPSCR

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Floating Point Instruction Registers, FPINST and FPINST2

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Scoreboard operation when an instruction bounces

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Load multiple-short vector CDP RAW hazard example

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Short vector CDP-load multiple WAR hazard example

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Short vector CDP-load multiple WAR hazard example

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Load multiple-load-CDP resource hazard example

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Load multiple-short vector CDP resource hazard example

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Short vector CDP-CDP resource hazard example

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Potential or actual exception that the VFP11 coprocessor cannot handle

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Potential or actual exception with the exception enable bit set

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Determination of the trigger instruction

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Exception processing for CDP scalar instructions

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Exception processing for CDP short vector instructions

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Examples of exception detection for vector instructions

# metadata.contentDescription
This is the technical reference manual for the VFP11 coprocessor.