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ARM PrimeCell Vectored Interrupt Controller (PL192) Technical Reference Manual

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PL192 PrimeCell Vectored Interrupt Controller

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ARM PrimeCell Vectored Interrupt Controller (PL192) Technical Reference Manual

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Feedback on the ARM PrimeCell Vectored Interrupt Controller (PL192)

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About the ARM PrimeCell Vectored Interrupt Controller (PL192)

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Vectored interrupt flow sequence using AHB

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Nonvectored interrupt flow sequence using AHB

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Vectored IRQ interrupt flow sequence using VIC port

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Single interrupt controller connectivity to a processor without VIC port

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Daisy-chained interrupt controller connectivity to processor without VIC port

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Raw Interrupt Status Register, VICRAWINTR

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Interrupt Enable Clear Register, VICINTENCLEAR

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ARM7TDMI FIQ interrupt latency during LDM

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IRQ during IRQ in an example ARMv5 system

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IRQ during IRQ in an example ARMv6 system

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Integration Test Input Register 1, VICITIP1

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Integration Test Input Register 2, VICITIP2

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Integration Test Output Register 1, VICITOP1

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Integration Test Output Register 2, VICITOP2

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Sampled Interrupt Source Status Register, VICINTSSTATUS

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Sampled Interrupt Source Status Clear Register, VICINTSSTATUSCLEAR

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Daisy-chained vectored interrupt service routine

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Highest level vectored IRQ interrupt service routine

# metadata.contentDescription
This document is the technical reference manual for the ARM PrimeCell Vectored Interrupt Controller (VIC).