# title
ARM PrimeCell MultiPort Memory Controller (PL176) Technical Reference Manual r0p1

# topic.label
ARM PrimeCell MultiPort Memory Controller (PL176) Technical Reference Manual

# topic.topics[].topics[].topics[].label
Feedback on the ARM PrimeCell MPMC (PL176)

# topic.topics[].topics[].topics[].label
Micron style V-synchronous flash devices

# topic.topics[].topics[].label
Overview of a PrimeCell MPMC, ASIC, or ASSP system

# topic.topics[].topics[].topics[].label
Worst case transaction latency for the highest priority AHB memory port

# topic.topics[].topics[].topics[].label
Worst case transaction latency for the lower priority AHB memory ports

# topic.topics[].topics[].topics[].label
System factors affecting worst case latency

# topic.topics[].topics[].label
Sharing memory bandwidth between AHB ports

# topic.topics[].topics[].topics[].label
Typical AHB port TimeOut value given bandwidth requirement

# topic.topics[].topics[].topics[].label
Typical AHB port TimeOut value given percentage of memory bandwidth requirement

# topic.topics[].topics[].topics[].label
Typical AHB bandwidth requirement example

# topic.topics[].topics[].topics[].label
Typical AHB percentage bandwidth example

# topic.topics[].topics[].topics[].label
Chip select 1 static memory configuration

# topic.topics[].topics[].topics[].label
Chip select 5 SDRAM memory configuration

# topic.topics[].topics[].topics[].label
Example of a boot from flash, SRAM remapped after boot

# topic.topics[].topics[].topics[].label
Example of a boot from flash, SDRAM remapped after boot

# topic.topics[].topics[].topics[].label
Dynamic Memory Refresh Timer Register, MPMCDynamicRefresh

# topic.topics[].topics[].topics[].label
Dynamic Memory Precharge Command Period Register, MPMCDynamictRP

# topic.topics[].topics[].topics[].label
Dynamic Memory Active To Precharge Command Period Register, MPMCDynamictRAS

# topic.topics[].topics[].topics[].label
Dynamic Memory Self-refresh Exit Time Register, MPMCDynamictSREX

# topic.topics[].topics[].topics[].label
Dynamic Memory Write Recovery Time Register, MPMCDynamictWR

# topic.topics[].topics[].topics[].label
Dynamic Memory Active To Active Command Period Register, MPMCDynamictRC

# topic.topics[].topics[].topics[].label
Dynamic Memory Auto-refresh Period Register, MPMCDynamictRFC

# topic.topics[].topics[].topics[].label
Dynamic Memory Exit Self-refresh Register, MPMCDynamictXSR

# topic.topics[].topics[].topics[].label
Dynamic Memory Active Bank A To Active Bank B Time Register, MPMCDynamictRRD

# topic.topics[].topics[].topics[].label
Dynamic Memory Load Mode Register, MPMCDynamictMRD

# topic.topics[].topics[].topics[].label
Dynamic Memory Last Data In To Read Command Time Register, MPMCDynamictCDLR

# topic.topics[].topics[].topics[].label
Static Memory Extended Wait Register, MPMCStaticExtendedWait

# topic.topics[].topics[].topics[].label
Dynamic Memory RAS and CAS Delay Registers 0-3, MPMCDynamicRasCas0-3

# topic.topics[].topics[].topics[].label
Static Memory Write Enable Delay Registers 0-3, MPMCStaticWaitWen0-3

# topic.topics[].topics[].topics[].label
Static Memory Output Enable Delay Registers 0-3, MPMCStaticWaitOen0-3

# topic.topics[].topics[].topics[].label
Static Memory Read Delay Registers 0-3, MPMCStaticWaitRd0-3

# topic.topics[].topics[].topics[].label
Static Memory Page Mode Read Delay Registers 0-3, MPMCStaticWaitPage0-3

# topic.topics[].topics[].topics[].label
Static Memory Write Delay Registers 0-3, MPMCStaticWaitWr0-3

# topic.topics[].topics[].topics[].label
Static Memory Turn Round Delay Registers 0-3, MPMCStaticWaitTurn0-3

# topic.topics[].topics[].topics[].label
NAND Memory Control Vector Register, MPMCNANDControl

# topic.topics[].topics[].topics[].label
NAND Memory Address Vectors 1-4 Register, MPMCNANDAddress1

# topic.topics[].topics[].topics[].label
NAND Memory Address Vector 5 Register, MPMCNANDAddress2

# topic.topics[].topics[].topics[].label
NAND Memory Timing Value 1 Register, MPMCNANDTiming1

# topic.topics[].topics[].topics[].label
NAND Memory Timing Value 2 Register, MPMCNANDTiming2

# topic.topics[].topics[].topics[].label
NAND Status Information Register, MPMCNANDStatus

# topic.topics[].topics[].topics[].label
AHB Control Registers 0-9, MPMCAHBControl0-9

# topic.topics[].topics[].topics[].label
AHB Status Registers 0-9, MPMCAHBStatus0-9

# topic.topics[].topics[].topics[].label
AHB Timeout Registers 0-9, MPMCAHBTimeOut0-9

# topic.topics[].topics[].topics[].label
Non-AMBA intra-chip integration test strategy

# topic.topics[].topics[].label
Elimination of floating bytes on the external interface

# topic.topics[].topics[].topics[].label
Memory banks constructed from 8-bit or non byte-partitioned memory devices

# topic.topics[].topics[].topics[].label
Memory banks constructed from 16 or 32-bit memory devices

# topic.topics[].topics[].topics[].label
Accessing other memory during NAND flash transfers

# topic.topics[].topics[].topics[].label
Single 64-bit read from SDR-SDRAM, row open

# topic.topics[].topics[].topics[].label
Single 64-bit write to SDR-SDRAM, row open

# topic.topics[].topics[].topics[].label
Burst 4 (INCR/INCR4/WRAP4) 64-bit read from 64-bit SDR-SDRAM, row open

# topic.topics[].topics[].topics[].label
Burst 4 (INCR/INCR4/WRAP4) 64-bit read from 64-bit SDR-SDRAM, bank precharged

# topic.topics[].topics[].topics[].label
Burst 4 (INCR/INCR4/WRAP4) 64-bit read from 64-bit SDR-SDRAM, different row open

# topic.topics[].topics[].topics[].label
Burst 4 (INCR/INCR4/WRAP4) 64-bit write to 64-bit SDR-SDRAM, row open

# topic.topics[].topics[].topics[].label
Burst 4 (INCR/INCR4/WRAP4) 64-bit write to 64-bit SDR-SDRAM, bank precharged

# topic.topics[].topics[].topics[].label
Burst 4 (INCR/INCR4/WRAP4) 64-bit write to 64-bit SDR-SDRAM, different row open

# topic.topics[].topics[].topics[].label
Two back-to-back burst 4 (INCR/INCR4/WRAP4) 64-bit read from 64-bit SDR-SDRAM, row open

# topic.topics[].topics[].topics[].label
Two back-to-back burst 4 (INCR/INCR4/WRAP4) 64-bit write to 64-bit SDR-SDRAM, row open

# topic.topics[].topics[].topics[].label
32-bit wide data bus address mappings (BRC) (SDR-SDRAM)

# topic.topics[].topics[].topics[].label
32-bit wide data bus address mappings (RBC) (SDR-SDRAM)

# topic.topics[].topics[].topics[].label
16-bit wide data bus address mappings (BRC) (SDR-SDRAM)

# topic.topics[].topics[].topics[].label
16-bit wide data bus address mappings (RBC) (SDR-SDRAM)

# topic.topics[].topics[].topics[].label
64-bit wide data bus address mappings (BRC) (SDR-SDRAM)

# topic.topics[].topics[].topics[].label
64-bit wide data bus address mappings (RBC) (SDR-SDRAM)

# topic.topics[].topics[].topics[].label
32-bit wide data bus address mappings (BSRSC) (V-SyncFlash)

# topic.topics[].topics[].topics[].label
16-bit wide data bus address mappings (BSRSC) (V-SyncFlash)

# topic.topics[].topics[].topics[].label
64-bit wide data bus address mappings (BSRSC) (V-SyncFlash)

# topic.topics[].topics[].label
Dynamic memory controller command descriptions

# topic.topics[].topics[].label
Micron MT48LC4M16A2 SDRAM initialization example

# topic.topics[].topics[].label
Micron SyncFlash and V-SyncFlash commands

# topic.topics[].topics[].label
Sequence of events leading to entry into TIC test mode

# topic.topics[].topics[].topics[].label
Methodologies in setting configuration tie-offs

# topic.topics[].topics[].topics[].label
Power Management Unit (PMU) self-refresh entry

# topic.topics[].topics[].topics[].label
Pin count reduction by reducing data bus width

# topic.topics[].topics[].topics[].label
Pin count reduction by removing functionality

# topic.topics[].topics[].topics[].label
Multiplexing static and dynamic memory pins

# topic.topics[].topics[].topics[].label
Command delay plus zero SDRAM timing diagrams

# topic.topics[].topics[].topics[].label
Command delay plus one SDRAM timing diagrams

# topic.topics[].topics[].topics[].label
Command delay plus two SDRAM timing diagrams

# topic.topics[].topics[].topics[].label
Generating feedback clock from bidirectional pad

# topic.topics[].topics[].label
Memory clock and feedback clock strategy

# topic.topics[].topics[].label
Methods to minimize the effects of delay and skew

# topic.topics[].topics[].label
Example NAND flash memory timing diagrams

# topic.topics[].topics[].label
Test Interface Controller (TIC) AHB signals

# metadata.contentDescription
This document is the technical reference manual for the ARM PrimeCell MPMC (PL176).