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CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual r3p3

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CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual

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About the CoreLink Level 2 Cache Controller L2C-310

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AXI master and slave interface attributes

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Clock enable usage model in the cache controller AXI interfaces

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TrustZone support in the cache controller

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Tag and Data RAM Latency Control Registers

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Reset and configuration signal timing parameters

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Slave port 0 input and output signal timing parameters

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Slave port 1 input and output signal timing parameters

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Master port 0 input and output signal timing parameters

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Master port 1 input and output signal timing parameters

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Data RAM input and output signal timing parameters

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Tag RAM input and output signal timing parameters

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Event monitor input and output signal timing parameters

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Cache interrupt ports signal timing parameters

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MBIST interface input and output signal timing parameters

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This book is written for hardware and software engineers implementing the CoreLink Level 2 Cache Controller into ASIC designs. It provides information to enable designers to integrate the device into a target system as quickly as possible.