# title
ARM9E-S Core Technical Reference Manual r2p1

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Forwarding, interlocking, and data dependencies

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ARM9E-S block, core, and interface diagrams

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ARM state and Thumb state registers relationship

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Instruction interface data timed signals

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Data interface, coprocessor register transfer cycles

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Withdrawal of memory requests in waited cycles

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Re-enabling interrupts after an interrupt exception

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Coprocessor pipeline operates in step with the ARM9E-S core

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Coprocessor pipeline one cycle behind the ARM9E-S core

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ARM9E-S core behavior on exit from reset

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Introduction to detailed instruction cycle timings

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Thumb Branch, Link, and Exchange <immediate>

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Software interrupt, undefined instruction, and exception entry

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Coprocessor register transfer, from ARM register

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Double coprocessor register transfer, to ARM register

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Double coprocessor register transfer, from ARM register

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Actions of the ARM9E-S core in debug state

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Comms channel monitor mode debug status register

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ARM9E-S core device identification (ID) code register

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Behavior of the program counter during debug

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Programming and reading EmbeddedICE-RT logic registers

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Breakpoint and watchpoint coupling example

# metadata.contentDescription
This is the technical reference manual for the ARM9E-S r2p1 core.