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PrimeCell Synchronous Static Memory Controller (PL093) Technical Reference Manual r0p4

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PrimeCell Synchronous Static Memory Controller (PL093) Technical Reference Manual

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Asynchronous static memory write control

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Synchronous memory devices bus turnaround

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Example of system with single output clock

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Bank Read Wait State Control Registers 0-7

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Bank Write Wait State Control Registers 0-7

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Bank Output Enable Assertion Delay Control Registers 0-7

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Bank Write Enable Assertion Delay Control Registers 0-7

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Bank Burst Read Wait Delay Control Registers 0-7

# metadata.contentDescription
This is the Technical Reference Manual for the PrimeCell Synchronous Static Memory Controller (SSMC).