# title
Arm PrimeCell Single Master DMA Controller (PL081) Technical Reference Manual

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PL081 PrimeCell Single Master DMA Controller

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PrimeCell Single Master DMA Controller (PL081) Technical Reference Manual

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Use with memory management unit based systems

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Interrupt Terminal Count Status Register

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Raw Interrupt Terminal Count Status Register

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Programming the SMDMAC for scatter/gather DMA

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Combined terminal count and error interrupt sequence flow

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Peripheral-to-memory transaction under SMDMAC flow control

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Memory-to-peripheral transaction under SMDMAC flow control

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Memory-to-memory transaction under SMDMAC flow control

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Peripheral-to-peripheral transfer under SMDMAC flow control

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Scatter/gather through linked list operation

# metadata.contentDescription
This is the Technical Reference Manual (TRM) for the ARM PrimeCell Single Master DMA Controller (PL081) (SMDMAC).