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PrimeCell MultiPort Memory Controller (PL172) Technical Reference Manual r2p4

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PrimeCell MultiPort Memory Controller (PL172) Technical Reference Manual

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About the PrimeCell MultiPort Memory Controller (PL172)

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Examples of Micron synchronous flash type devices

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Examples of JEDEC low-power SDRAM devices

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Worst-case transaction latency for the highest priority AHB memory port

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System factors effecting worst-case latency

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Boot from flash, SRAM remapped after boot

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Example of a boot from flash, SDRAM remapped after boot

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Dynamic Memory Read Configuration Register

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Dynamic Memory Precharge Command Period Register

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Dynamic Memory Active To Precharge Command Period Register

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Dynamic Memory Self-refresh Exit Time Register

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Dynamic Memory Last Data Out To Active Time Register

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Dynamic Memory Data-in To Active Command Time Register

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Dynamic Memory Write Recovery Time Register

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Dynamic Memory Active To Active Command Period Register

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Dynamic Memory Auto-refresh Period Register

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Dynamic Memory Exit Self-refresh Register

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Dynamic Memory Active Bank A to Active Bank B Time Register

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Dynamic Memory Load Mode Register To Active Command Time Register

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Dynamic Memory Configuration Registers 0-3

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Dynamic Memory RAS and CAS Delay Registers 0-3

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Static Memory Configuration Registers 0-3

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Static Memory Write Enable Delay Registers 0-3

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Static Memory Output Enable Delay Registers 0-3

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Static Memory Page Mode Read Delay Registers 0-3

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Static Memory Turn Round Delay Registers 0-3

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Non-AMBA intra-chip integration test strategy

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Test Interface Controller (TIC) AHB signals

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This document is the technical reference manual for the PrimeCell MPMC (PL172).