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Feedback on the Technical Reference Manual

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About the ARM7EJ-S processor with Jazelle technology

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Forwarding, interlocking, and data dependencies

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ARM7EJ-S processor block, core, and interface diagrams

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ARM7EJ-S processor instruction set summary

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Relationships between ARM state and Thumb state registers

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Re-enabling interrupts after an interrupt exception

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Using Watchpoints and breakpoints in Jazelle state

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Enabling and disabling the ETM interface

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Thumb Branch, Link, and Exchange immediate

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Software interrupt, undefined instruction, and exception entry

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Coprocessor register transfer (from ARM)

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Double coprocessor register transfer (to ARM)

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Double coprocessor register transfer (from ARM)

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Boundary scan and debug logic output data

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Device IDentification (ID) code register

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Behavior of the program counter during debug

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Jazelle state breakpoints and watchpoints

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Programming and reading EmbeddedICE-RT logic registers

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Breakpoint and watchpoint coupling example

# metadata.contentDescription
This document is the Technical Reference Manual for the ARM7EJ-S processor.