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ARM1136JF-S and ARM1136J-S Technical Reference Manual r1p5

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ARM1136JF-S and ARM1136J-S Technical Reference Manual

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Instruction cycle summary and interlocks

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ARM1136JF-S architecture with Jazelle technology

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ARM state and Thumb state registers relationship

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Modification of PSR bits by MSR instructions

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Imprecise Data Abort mask in the CPSR/SPSR

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System control coprocessor functional groups

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System control coprocessor registers overview

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System control coprocessor register descriptions

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c2, Translation Table Base Register 0, TTBR0

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c2, Translation Table Base Register 1, TTBR1

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c2, Translation Table Base Control Register, TTBCR

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c5, Instruction Fault Status Register, IFSR

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c6, Watchpoint Fault Address Register, WFAR

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c8, TLB Operations Register (invalidate TLB operation)

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c9, Data and Instruction Cache Lockdown Registers

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c11, DMA Identification and Status Registers

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c11, DMA Internal Start Address Registers

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c11, DMA External Start Address Registers

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c15, Performance Monitor Control Register (PMNC)

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c15, Cache and Main TLB Master Valid Registers

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Unaligned and Mixed-Endian Data Access Support

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About unaligned and mixed-endian support

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Word-invariant mode and ARMv6 configurations

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Word-invariant data access in ARMv6 (U=0)

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Support for unaligned data access in ARMv6 (U=1)

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ARMv6 unaligned data access restrictions

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Load double, load multiple, load coprocessor (little-endian, E = 0)

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Load double, load multiple, load coprocessor (big-endian, E=1)

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Store double, store multiple, store coprocessor (little-endian, E=0)

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Store double, store multiple, store coprocessor (big-endian, E=1)

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Word-invariant fixed instruction and data endianness

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Instructions to reverse bytes in a general-purpose register

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Instruction Memory Barrier (IMB) instruction

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Virtual to physical translation mapping restrictions

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C and B bit, and type extension field encodings

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Ordering requirements for memory accesses

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Backwards-compatible page table translation (subpage AP bits enabled)

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ARMv6 page table translation (subpage AP bits disabled)

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Restrictions on page table mappings (page coloring)

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AHB-Lite control signals in the ARM1136JF-S processor

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Instruction Fetch Interface AHB-Lite transfers

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Other AHB-Lite signals for Cacheable and Noncacheable instruction fetches

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Other AHB-Lite signals for Data Read ports

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Other AHB-Lite signals for Data Write port

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Other AHB-Lite signals for Peripheral Interface reads and writes

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Read latency penalty for synchronous operation

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Communication to the Power Management Controller

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About the PL192 Vectored Interrupt Controller

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CP14 c1, Debug Status and Control Register (DSCR)

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Overview of breakpoint and watchpoint registers on the ARM1136JF-S processor

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CP14 c64-c69, Breakpoint Value Registers (BVR)

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CP14 c80-c85, Breakpoint Control Registers (BCR)

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CP14 c96-c97, Watchpoint Value Registers (WVR)

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CP14 c112-c113, Watchpoint Control Registers (WCR)

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Behavior of the processor on debug events

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Effect of a debug event on CP15 registers

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Setting breakpoints, watchpoints, and vector catch debug events

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Setting software breakpoint debug events (BKPT instructions)

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Debug Test Access Port and Halting debug-mode

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Transferring data between the host and the core

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Target to host debug communications channel sequence

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Host to target debug communications channel

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Reading a current mode ARM register in the range R0-R14

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Writing a current mode ARM register in the range R0-R14

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General notes about reading and writing memory

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Setting breakpoints, watchpoints and vector catches

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About cycle timings and interlock behavior

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Cycle counts if destination is not the PC

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QADD, QDADD, QSUB, and QDSUB instructions

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Load and store multiples, other than load multiples including the PC

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Load multiples, where the PC is in the register list

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SWI, BKPT, Undefined, and Prefetch Aborted instructions

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Interrupt signals, including the VIC interface

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Functional changes in the rev1 (r1pn) releases

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Implementation of an Access Flag and Access Flag fault detection

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Register 10, TLB lockdown and remapping registers

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Register 13, Process, Thread ID and Processor ID registers

# metadata.contentDescription
This document is the Technical Reference Manual for the ARM1136JF-S and ARM1136J-S processors.