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PrimeCell Static Memory Controller (PL092) Technical Reference Manual r1p3

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PrimeCell Static Memory Controller (PL092) Technical Reference Manual

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Memory banks constructed from 8-bit or non byte-partitioned memory devices

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Memory banks constructed from 16 or 32-bit memory devices

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Elimination of floating bytes on the external interface

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Byte lane control and data bus steering for little and big-endian configurations

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Using the SMC with an external bus multiplexor or SDRAM controller

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Bank Output Enable Assertion Delay Control Registers 0-7

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Bank Write Enable Assertion Delay Control Registers 0-7

# metadata.contentDescription
This is the Technical Reference Manual (TRM) for the ARM PrimeCell Static Memory Controller (SMC).