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ARM946E-S Technical Reference Manual r1p1

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Register 0, Tightly-coupled Memory Size Register

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Register 2, Cache Configuration Registers

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Register 3, Write Buffer Control Register

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Register 6, Protection Region Base and Size Registers

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Register 9, Tightly-coupled Memory Region Registers

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Register 13, Trace Process Identifier Register

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Enabling and disabling the instruction cache

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Defining the physical and visible size of the Instruction TCM

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Defining the physical and visible size of the Data TCM

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Enabling the Instruction TCM during soft reset

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Stall cycles for Instruction TCM accesses

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Synchronizing the external coprocessor pipeline

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Register 13, Trace Process Identifier Register

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Debug Communication Channel Status Register

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Communications using the communication channel

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About the ARM946E-S processor test methodology

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This document is a reference manual for the ARM946E-S processor.