# title
ARM926EJ-S Technical Reference Manual r0p5

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Summary of ARM926EJ-S system control coprocessor (CP15) registers

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ID Code, Cache Type, and TCM Status Registers, c0

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Cache Lockdown and TCM Region Registers c9

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Fault address and fault status registers

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About the tightly-coupled memory interface

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TCM interface bus cycle types and timing

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Producing byte writable memory using word writable RAM

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Mapping of level one and level two AHB attributes

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About the ARM926EJ-S external coprocessor interface

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About the instruction memory barrier operation

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Synchronize data and instruction streams in level two AHB subsystems

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Dynamic power management (wait for interrupt mode)

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Static power management (leakage control)

# metadata.contentDescription
This is the Technical Reference Manual for the ARM926EJ-S processor.