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Feedback on the ARM920T Technical Reference Manual

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Register 2, translation table base (TTB) register

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Register 3, domain access control register

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Register 15, test configuration register

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Fault address and fault status registers

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Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM

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Enabling and disabling the DCache and write buffer

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Connecting the ARM920T to an AMBA ASB interface

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Cached LDR, cached LDM, and cached fetch

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Dirty data eviction, write-back of 4 or 8 words

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Level 2 cache support and performance analysis

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Enabling and disabling the external coprocessor interface buses

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ARM920T device identification (ID) code register

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Scan chains 4 and 15, the ARM920T memory system

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Determining the core state and system state

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Instructions that can have the SYSSPEED bit set

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The behavior of the program counter during debug

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Creating an ARM920T AMBA functional test

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Behavior of the cache index pointer in AMBA cache test

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Behavior of the TLB Index pointer in AMBA MMU test

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Instruction Cycle Summary and Interlocks

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Timing definitions for the ARM920T Trace Interface Port

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Bits [8:6], disable CP15 register 1, iA and nF

# metadata.contentDescription
This document is the technical reference manual for the ARM920T processor.