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Feedback on the ARM940T Technical Reference Manual

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Register 2, instruction and data cachable registers

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Register 3, write buffer control register

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Register 5, instruction and data space protection registers

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Register 6, protection region base and size registers

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Register 9, instruction and data lockdown registers

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Cached LDR, cached LDM, and cached fetch

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Dirty data eviction, write-back of 4 words

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ARM940T device identification (ID) code register

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Instructions that can have the SYSSPEED bit set

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The behavior of the program counter during debug

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Instruction Cycle Summary and Interlocks

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This document is the technical reference manual for the ARM940T.