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Branch prediction and prefetch unit (PU)

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Summary of ARM1020T system control coprocessor (CP15) registers

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Translation routes for sections and pages

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Fault address and fault status registers

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Interaction of the MMU, caches, and write buffer

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Data cache and write buffer enable/disable

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Flushing the prefetch buffer using the Instruction Memory Barrier (IMB)
                instruction

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Instruction memory barrier instruction (IMB)

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The ARM1020T instruction bus interface unit (I-BIU) overview

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The ARM1020 data bus interface unit (D-BIU) overview

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Scan Chain 1 Debug Status and Control Register (DSCR)

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R1: Debug status and control register (DSCR)

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Register R5: data transfer register (DTR)

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Registers 80-85 breakpoint control registers

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Registers 96 and 97 watchpoint address registers

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Registers 112 and 113 watchpoint control registers (WCR)

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Values in the link register after aborts

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Sending instructions to the integer unit

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Using DSCR[29] for fast data uploads and downloads

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Reading and writing breakpoint and watchpoint registers

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Simultaneous reads and writes in TIC mode

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Functional test mode (ARM1020T integer unit test mode)

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Instruction Cycle summary and Interlocks

# metadata.contentDescription
This is the Technical Reference Manual (TRM) for the ARM 1020T.