# title
Managing Memory Protection Performance Concerns in Cached CortexTM R4/R5 Processors

# topic.label
Managing Memory Protection Performance Concerns in Cached CortexTM R4/R5 Processors Application note 296

# metadata.contentDescription
This document provides guidance for programming the Memory Protection Unit (MPU) in the ARM Cortex-R4 and Cortex-R5 processors when the protection configuration is changed during a context switch.