# title
The Dangers of Living with an X (bugs hidden in your Verilog)

# topic.label
The Dangers of Living with an X (bugs hidden in your Verilog) Research paper

# metadata.contentDescription
The semantics of X in Verilog RTL are extremely dangerous as RTL bugs can be masked, allowing RTL simulations to incorrectly pass where netlist simulations can fail. Such X-bugs are often missed because formal equivalence checkers are configured to ignore them, which is a particular concern given that equivalence checking is fast replacing netlist simulations. This paper gives examples of such problems in order to raise awareness of X issues in many different parts of the design flow, which are often poorly understood by RTL designers and EDA vendors alike.