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Arm Cortex-R52 Processor MP040 Software Developer Errata Notice

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Arm® Cortex®-R52 Processor MP040 Software Developer Errata Notice

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2130897 VLDM/VSTM may corrupt data under certain conditions

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786955 Wrong DFSR.STATUS or HSR.DFSC is set on asynchronous aborts because of detected errors on BRESPMx signals

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827402 A stream of data cache maintenance operations can lead to a deadlock

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1412115 False DCLS errors can be generated in configurations without bus protection

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2743885 GICR_TYPER registers do not reflect affinity configuration inputs

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2918152 Executing LDM instruction might cause data corruption when HSCTLR.FI is set

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844709 Advanced SIMD integer multiply instructions in IT block might cause data corruption

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752456 Store-exclusive to Shareable Device memory might cause core to deadlock/livelock

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763109 Undefined exception might be taken on an instruction cache ECC error

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779430 Bus timeout combined with online MBIST entry might lead to deadlock

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818201 Accesses to direct-mapped EL2-controlled MPU registers are not unallocated when no programmable regions are configured

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836865 An EXOKAY response to a read on the LLPP interface indicates the wrong ADFSR value

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848521 The ETM can enter a low power state when active, potentially corrupting trace when TRCEVENTCTL1R.LPOVERRIDE is set

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857196 Performance Monitors count might be inaccurate for event 0x01B (INST_SPEC)

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857509 Mismatch between EDPRSR.SR and EDPRSR.R

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857511 Debug not entering Memory Access mode without setting EDSCR.ERR

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865776 Repeated asynchronous exceptions might generate false livelock indication

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888346 Implementation defined Data Cache Debug Read operations can only access the first doubleword of a cacheline

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904856 An MBIST request in the middle of pending AXIS requests might cause the core to deadlock

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925639 Debugger read transactions to Device Affinity Registers of CoreSight components return incorrect values

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1050715 Cross trigger interrupt generation does not work using CTIAPPPULSE register

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1328481 The debugger view of the number of cores might be incorrect when switching between Split and Lock modes

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2077568 ATB flush response may be delayed

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2289294 DTR flags not cleared on external debugger access while leaving Debug state

# metadata.contentDescription
This document outlines RTL-level errata that may affect software developers through observable system behavior.