# title
Arm C1-Nano Core (MP205) Software Developer Errata Notice

# topic.label
Arm® C1-Nano Core (MP205) Software Developer Errata Notice

# topic.topics[].topics[].topics[].label
3412219 Core might execute an incorrect instruction when receiving an I-cache invalidation

# topic.topics[].topics[].topics[].label
3812929 Core performance while executing non-SME instructions might degrade after executing SME instructions

# topic.topics[].topics[].topics[].label
3272423 TLB invalidation or I-cache maintenance operation ordering might be incorrect on a denied power-down

# topic.topics[].topics[].topics[].label
3299725 Enabling PMU after leaving Streaming SVE mode might cause memory instruction failure

# topic.topics[].topics[].topics[].label
3357947 A core in Streaming SVE mode might not take interrupts in finite time

# topic.topics[].topics[].topics[].label
3387722 Power transition in complex shared power domain might deadlock

# topic.topics[].topics[].topics[].label
3392149 The core might deadlock when receiving an I-cache invalidation

# topic.topics[].topics[].topics[].label
3419531 Store operations might modify data twice

# topic.topics[].topics[].topics[].label
3437202 Consecutive store instructions might lead to data corruption

# topic.topics[].topics[].topics[].label
3444215 Ordering required by FEAT_ETS2 might not be correctly followed

# topic.topics[].topics[].topics[].label
3516455 Non-SME instruction abort might cause the core to deadlock in streaming mode

# topic.topics[].topics[].topics[].label
3616450 SME, SIMD&FP, or SVE load or store might result in data corruption under uncommon micro-architectural conditions

# topic.topics[].topics[].topics[].label
3630925 CPU non-secure physical timer event interrupt might be triggered incorrectly

# topic.topics[].topics[].topics[].label
3684075 Incorrect ESR_EL1.ISS.WPT for SVE First-Fault Load Instructions

# topic.topics[].topics[].topics[].label
3711442 Incorrect SME priority computation by the core when SCR_EL3.HXEN = 0 or in Host mode

# topic.topics[].topics[].topics[].label
3754876 A core might deadlock during power down if TRBE is enabled

# topic.topics[].topics[].topics[].label
3806270 Clock is not gated in synchronous configurations when in FULL_RET power mode

# topic.topics[].topics[].topics[].label
3919697 Power transition might deadlock on Utility Bus or APB access

# topic.topics[].topics[].topics[].label
4019818 Permission fault might not generate correctly for some Cache Maintenance Operations (CMO)

# topic.topics[].topics[].topics[].label
4394104 Core might not enter low-power state or might deadlock when data prefetcher is disabled

# topic.topics[].topics[].topics[].label
4497400 Faulting load might disclose data from previous load through side channel

# topic.topics[].topics[].topics[].label
3244511 Interrupt signals generated by cores might be deasserted when in retention

# topic.topics[].topics[].topics[].label
3267301 Power transition from EMU_OFF to OFF might not complete

# topic.topics[].topics[].topics[].label
3268763 Some PMU events from the CME can corrupt event counters

# topic.topics[].topics[].topics[].label
3274754 A hardware update of the dirty bit might occur speculatively when in streaming mode

# topic.topics[].topics[].topics[].label
3281889 External registers PMCEID2 and PMCEID3 are not implemented

# topic.topics[].topics[].topics[].label
3300748 Debug access to powered off core might deadlock

# topic.topics[].topics[].topics[].label
3306448 Programming PMU in Streaming SVE mode might cause memory instruction failure

# topic.topics[].topics[].topics[].label
3314670 PMU events might not be sent to trace unit in Streaming SVE mode

# topic.topics[].topics[].topics[].label
3350092 ERR0STATUS.IERR in the Complex RAS node might be incorrect when pseudo-fault generation is used

# topic.topics[].topics[].topics[].label
3410086 STREX instruction might update the memory when a synchronous abort is raised

# topic.topics[].topics[].topics[].label
3437306 Some PMU events do not count correctly

# topic.topics[].topics[].topics[].label
3466279 Writes to Cycle Counter filter register in Streaming SVE mode corrupt event counter 0

# topic.topics[].topics[].topics[].label
3501986 TRBE might record the wrong status/syndrome information in the TRBSR_EL1 register

# topic.topics[].topics[].topics[].label
3504323 Spurious watchpoint hit for 512-bit unaligned unpredicted SME instruction might happen

# topic.topics[].topics[].topics[].label
3518149 Direct memory access to L1 Data cache TAG RAM does not return the RAM protection bit

# topic.topics[].topics[].topics[].label
3531281 Incorrect WPT number might be recorded in ESR_ELx register

# topic.topics[].topics[].topics[].label
3532863 A Non-cacheable store exclusive instruction receiving an NDErr or DErr response might update memory and raise synchronous abort

# topic.topics[].topics[].topics[].label
3534009 Load/Store instruction might get unexpected translation fault

# topic.topics[].topics[].topics[].label
3534381 Branch with link at top of virtual memory might forward incorrect LR value to PAC instruction

# topic.topics[].topics[].topics[].label
3576152 Core might not execute some instructions in debug state after a reset catch debug event is generated

# topic.topics[].topics[].topics[].label
3609645 Core might deadlock after executing SYS_IMP_CDBGL1ICTR with CPU_CACHE_PROTECTION enabled

# topic.topics[].topics[].topics[].label
3614494 CPU might incorrectly wake up from WFE state due to a virtual event stream when in FULL_RET power mode

# topic.topics[].topics[].topics[].label
3616572 External register control of PMU with CME present might cause inaccuracy

# topic.topics[].topics[].topics[].label
3621945 Core RAS feature register ERR0FR incorrect when CPU_CACHE_PROTECTION is FALSE

# topic.topics[].topics[].topics[].label
3636381 Cache debug operations targeting upper bits of L2 Data RAM might record incorrect data

# topic.topics[].topics[].topics[].label
3641489 Single stepping might fail for standardized memory operations on ECC error

# topic.topics[].topics[].topics[].label
3644841 A MOVPRFX, followed by an instruction that cannot be predictably prefixed by a MOVPRFX instruction, might lead to data corruption or deadlock

# topic.topics[].topics[].topics[].label
3649692 Core in a dual core complex might complete power transition to OFF while a CTI trigger is in progress

# topic.topics[].topics[].topics[].label
3657417 Core performance might drop for MTE checked store operation

# topic.topics[].topics[].topics[].label
3665121 PMU events from CME unit might not count correctly after changing settings

# topic.topics[].topics[].topics[].label
3669229 Some PMU events do not count correctly

# topic.topics[].topics[].topics[].label
3673964 CTI trigger events from a core in Standby state might not be sent correctly

# topic.topics[].topics[].topics[].label
3675972 The wrong attributes may be selected for instruction fetches when HCR_EL2.FWB == 1 while accessing a Non-shareable memory region

# topic.topics[].topics[].topics[].label
3683751 External debug request while transitioning to emulated off might cause core to deadlock

# topic.topics[].topics[].topics[].label
3688112 IRG produces biased tag generation when GCR_EL1.RRND == 1

# topic.topics[].topics[].topics[].label
3719556 Incorrect ESR_EL1.ISS.EX or ESR_EL2.ISS.EX for Software Step Exceptions

# topic.topics[].topics[].topics[].label
3721134 Consecutive CTI trigger events from the same ELA output might not be sent to the CTI

# topic.topics[].topics[].topics[].label
3723871 Performance might drop for core 1 in a 2-core complex configuration

# topic.topics[].topics[].topics[].label
3787998 ERXMISC0 or ERXMISC1 register for L2 RAS node might be corrupted on a write to the register

# topic.topics[].topics[].topics[].label
3803950 Affinity ID info in Complex_RAS.ERRDEVAFF register is not correct in single-core complex configuration

# topic.topics[].topics[].topics[].label
3807484 A core might deadlock when a store instruction linefill receives an NDErr or DErr response

# topic.topics[].topics[].topics[].label
3962972 An ECC error might generate data corruption

# topic.topics[].topics[].topics[].label
4106084 ETE and ELA timestamps are not accurate

# topic.topics[].topics[].topics[].label
4185708 L1 Instruction cache tag RAM ECC Error might be reported multiple times

# topic.topics[].topics[].topics[].label
4421051 TRBE might not record the TRBSR_EL1.WRAP bit correctly

# topic.topics[].topics[].topics[].label
4431238 Some PMU Events might be counted incorrectly

# topic.topics[].topics[].topics[].label
4495847 Memory-mapped reads of AMEVCNTR12 and AMEVCNTR13 return incorrect values

# topic.topics[].topics[].topics[].label
4188050 Core might not stall when trace unit stalling is enabled

# metadata.contentDescription
This document outlines RTL-level errata that may affect software developers through observable system behavior.